[PATCH v3 0/7] ARM: at91: move aic driver to drivers/irqchips

[PATCH v3 0/7] ARM: at91: move aic driver to drivers/irqchips

[Boris BREZILLON]

Hello,

This series moves the AIC driver to the irqchip directory and make use of
the generic chip framework whenever possible.

This driver only support DT boards (all legacy board files should be soon
replaced by their DT versions).

Best Regards,

Boris

Changes since v2:
 - remove irq line muxing definition
 - rework Kconfig options

Changes since v1:
 - rework the irq-mux bindings

Boris BREZILLON (7):
  genirq: generic chip: export irq_map_generic_chip function
  irqchip: atmel-aic: move binding doc to interrupt-controller directory
  irqchip: atmel-aic: add new atmel AIC driver
  ARM: at91: introduce OLD_IRQ_AT91 Kconfig option
  ARM: at91: enclose at91_aic_xx calls in
    IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks
  ARM: at91: make use of the new AIC driver for dt enabled boards
  ARM: at91: remove old irq material

 .../devicetree/bindings/arm/atmel-aic.txt          |  42 --
 .../bindings/interrupt-controller/atmel,aic.txt    |  42 ++
 arch/arm/mach-at91/Kconfig                         |  17 +-
 arch/arm/mach-at91/Kconfig.non_dt                  |   6 +
 arch/arm/mach-at91/Makefile                        |   3 +-
 arch/arm/mach-at91/board-dt-rm9200.c               |  13 -
 arch/arm/mach-at91/board-dt-sam9.c                 |  13 -
 arch/arm/mach-at91/board-dt-sama5.c                |  13 -
 arch/arm/mach-at91/irq.c                           | 270 +-------
 arch/arm/mach-at91/pm.c                            |  32 +-
 arch/arm/mach-at91/setup.c                         |   3 +-
 drivers/irqchip/Kconfig                            |   7 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-atmel-aic.c                    | 700 +++++++++++++++++++++
 include/linux/irq.h                                |   2 +
 kernel/irq/generic-chip.c                          |   5 +-
 16 files changed, 800 insertions(+), 369 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/atmel-aic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
 create mode 100644 drivers/irqchip/irq-atmel-aic.c

-- 
1.8.3.2

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[PATCH v3 2/7] irqchip: atmel-aic: move binding doc to interrupt-controller directory

[Boris BREZILLON]

Move atmel aic driver doc to the interrupt-controller directory as the new
driver now lays in drivers/irqchip/atmel-aic.c.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
 .../devicetree/bindings/arm/atmel-aic.txt          | 42 ----------------------
 .../bindings/interrupt-controller/atmel,aic.txt    | 42 ++++++++++++++++++++++
 2 files changed, 42 insertions(+), 42 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/atmel-aic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt

diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
deleted file mode 100644
index 2742e9c..0000000
--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-* Advanced Interrupt Controller (AIC)
-
-Required properties:
-- compatible: Should be "atmel,<chip>-aic"
-  <chip> can be "at91rm9200" or "sama5d3"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: For single AIC system, it is an empty property.
-- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
-  The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
-  The second cell is used to specify flags:
-    bits[3:0] trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
-      Valid combinations are 1, 2, 3, 4, 8.
-      Default flag for internal sources should be set to 4 (active high).
-  The third cell is used to specify the irq priority from 0 (lowest) to 7
-  (highest).
-- reg: Should contain AIC registers location and length
-- atmel,external-irqs: u32 array of external irqs.
-
-Examples:
-	/*
-	 * AIC
-	 */
-	aic: interrupt-controller@fffff000 {
-		compatible = "atmel,at91rm9200-aic";
-		interrupt-controller;
-		interrupt-parent;
-		#interrupt-cells = <3>;
-		reg = <0xfffff000 0x200>;
-	};
-
-	/*
-	 * An interrupt generating device that is wired to an AIC.
-	 */
-	dma: dma-controller@ffffec00 {
-		compatible = "atmel,at91sam9g45-dma";
-		reg = <0xffffec00 0x200>;
-		interrupts = <21 4 5>;
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
new file mode 100644
index 0000000..2742e9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
@@ -0,0 +1,42 @@
+* Advanced Interrupt Controller (AIC)
+
+Required properties:
+- compatible: Should be "atmel,<chip>-aic"
+  <chip> can be "at91rm9200" or "sama5d3"
+- interrupt-controller: Identifies the node as an interrupt controller.
+- interrupt-parent: For single AIC system, it is an empty property.
+- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
+  The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
+  The second cell is used to specify flags:
+    bits[3:0] trigger type and level flags:
+      1 = low-to-high edge triggered.
+      2 = high-to-low edge triggered.
+      4 = active high level-sensitive.
+      8 = active low level-sensitive.
+      Valid combinations are 1, 2, 3, 4, 8.
+      Default flag for internal sources should be set to 4 (active high).
+  The third cell is used to specify the irq priority from 0 (lowest) to 7
+  (highest).
+- reg: Should contain AIC registers location and length
+- atmel,external-irqs: u32 array of external irqs.
+
+Examples:
+	/*
+	 * AIC
+	 */
+	aic: interrupt-controller@fffff000 {
+		compatible = "atmel,at91rm9200-aic";
+		interrupt-controller;
+		interrupt-parent;
+		#interrupt-cells = <3>;
+		reg = <0xfffff000 0x200>;
+	};
+
+	/*
+	 * An interrupt generating device that is wired to an AIC.
+	 */
+	dma: dma-controller@ffffec00 {
+		compatible = "atmel,at91sam9g45-dma";
+		reg = <0xffffec00 0x200>;
+		interrupts = <21 4 5>;
+	};
-- 
1.8.3.2

[PATCH v3 6/7] ARM: at91: make use of the new AIC driver for dt enabled boards

[Boris BREZILLON]

Remove selection of OLD_IRQ_AT91 when selecting dt boards.
Select ATMEL_AIC_IRQ for sama5 SoCs (a kernel compiled for this SoC will
always use ATMEL_AIC_IRQ driver).
Select ATMEL_AIC_IRQ for at91rm9200 and at91sam9 SoCs only if OLD_IRQ_AT91
is not selected (which means we are compiling a pure DT kernel, without
any legacy board support).

Remove specific irq init code in all dt board files: this init procedure
is automatically handled in of_irq_init which is called by the arm irq core
code and is in charge of calling the appropriate aic init functions.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
 arch/arm/mach-at91/Kconfig           |  6 +++---
 arch/arm/mach-at91/board-dt-rm9200.c | 13 -------------
 arch/arm/mach-at91/board-dt-sam9.c   | 13 -------------
 arch/arm/mach-at91/board-dt-sama5.c  | 13 -------------
 4 files changed, 3 insertions(+), 42 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index fbc1b68..7526a93 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -52,12 +52,14 @@ config SOC_AT91SAM9
 	select AT91_SAM9_TIME
 	select CPU_ARM926T
 	select GENERIC_CLOCKEVENTS
+	select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
 
 config SOC_SAMA5
 	bool
 	select AT91_SAM9_TIME
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
+	select ATMEL_AIC_IRQ
 	select USE_OF
 
 menu "Atmel AT91 System-on-Chip"
@@ -111,6 +113,7 @@ config SOC_AT91RM9200
 	select CPU_ARM920T
 	select GENERIC_CLOCKEVENTS
 	select HAVE_AT91_DBGU0
+	select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
 	select AT91_USE_OLD_CLK
 	select HAVE_AT91_USB_CLK
 
@@ -198,7 +201,6 @@ config MACH_AT91RM9200_DT
 	bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
 	depends on SOC_AT91RM9200
 	select USE_OF
-	select OLD_IRQ_AT91
 	help
 	  Select this if you want to experiment device-tree with
 	  an Atmel RM9200 Evaluation Kit.
@@ -207,7 +209,6 @@ config MACH_AT91SAM9_DT
 	bool "Atmel AT91SAM Evaluation Kits with device-tree support"
 	depends on SOC_AT91SAM9
 	select USE_OF
-	select OLD_IRQ_AT91
 	help
 	  Select this if you want to experiment device-tree with
 	  an Atmel Evaluation Kit.
@@ -216,7 +217,6 @@ config MACH_SAMA5_DT
 	bool "Atmel SAMA5 Evaluation Kits with device-tree support"
 	depends on SOC_SAMA5
 	select USE_OF
-	select OLD_IRQ_AT91
 	select PHYLIB if NETDEVICES
 	help
 	  Select this if you want to experiment device-tree with
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3a185fa..61ea214 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -24,17 +24,6 @@
 #include "at91_aic.h"
 #include "generic.h"
 
-
-static const struct of_device_id irq_of_match[] __initconst = {
-	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91rm9200_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static const char *at91rm9200_dt_board_compat[] __initdata = {
 	"atmel,at91rm9200",
 	NULL
@@ -43,8 +32,6 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
 DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
 	.init_time      = at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91rm9200_dt_initialize,
-	.init_irq	= at91rm9200_dt_init_irq,
 	.dt_compat	= at91rm9200_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 575b0be..dfa8d48 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -34,17 +34,6 @@ static void __init sam9_dt_timer_init(void)
 	at91sam926x_pit_init();
 }
 
-static const struct of_device_id irq_of_match[] __initconst = {
-
-	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static const char *at91_dt_board_compat[] __initdata = {
 	"atmel,at91sam9",
 	NULL
@@ -54,8 +43,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	/* Maintainer: Atmel */
 	.init_time	= sam9_dt_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91_dt_initialize,
-	.init_irq	= at91_dt_init_irq,
 	.dt_compat	= at91_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 075ec05..d6fe04b 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -35,17 +35,6 @@ static void __init sama5_dt_timer_init(void)
 	at91sam926x_pit_init();
 }
 
-static const struct of_device_id irq_of_match[] __initconst = {
-
-	{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static int ksz9021rn_phy_fixup(struct phy_device *phy)
 {
 	int value;
@@ -82,9 +71,7 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
 	/* Maintainer: Atmel */
 	.init_time	= sama5_dt_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic5_handle_irq,
 	.init_early	= at91_dt_initialize,
-	.init_irq	= at91_dt_init_irq,
 	.init_machine	= sama5_dt_device_init,
 	.dt_compat	= sama5_dt_board_compat,
 MACHINE_END
-- 
1.8.3.2

[PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Boris BREZILLON]

Export the generic irq map function in order to provide irq_domain ops with
generic mapping and specific of xlate function (needed by the new atmel
AIC driver).

Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 include/linux/irq.h       | 2 ++
 kernel/irq/generic-chip.c | 5 +++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 0d998d8..62af592 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
 
 /* Setup functions for irq_chip_generic */
+int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
+			 irq_hw_number_t hw_irq);
 struct irq_chip_generic *
 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
 		       void __iomem *reg_base, irq_flow_handler_t handler);
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index 452d6f2..cf80e7b 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
 /*
  * irq_map_generic_chip - Map a generic chip for an irq domain
  */
-static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
-				irq_hw_number_t hw_irq)
+int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
+			 irq_hw_number_t hw_irq)
 {
 	struct irq_data *data = irq_get_irq_data(virq);
 	struct irq_domain_chip_generic *dgc = d->gc;
@@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
 	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(irq_map_generic_chip);
 
 struct irq_domain_ops irq_generic_chip_ops = {
 	.map	= irq_map_generic_chip,
-- 
1.8.3.2

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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Jason Cooper]

On Fri, Jun 20, 2014 at 05:01:21PM +0200, Boris BREZILLON wrote:
> Export the generic irq map function in order to provide irq_domain ops with
> generic mapping and specific of xlate function (needed by the new atmel
> AIC driver).
> 
> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
>  include/linux/irq.h       | 2 ++
>  kernel/irq/generic-chip.c | 5 +++--
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/include/linux/irq.h b/include/linux/irq.h
> index 0d998d8..62af592 100644
> --- a/include/linux/irq.h
> +++ b/include/linux/irq.h
> @@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
>  int irq_gc_set_wake(struct irq_data *d, unsigned int on);
>  
>  /* Setup functions for irq_chip_generic */
> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> +			 irq_hw_number_t hw_irq);
>  struct irq_chip_generic *
>  irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
>  		       void __iomem *reg_base, irq_flow_handler_t handler);
> diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
> index 452d6f2..cf80e7b 100644
> --- a/kernel/irq/generic-chip.c
> +++ b/kernel/irq/generic-chip.c
> @@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
>  /*
>   * irq_map_generic_chip - Map a generic chip for an irq domain
>   */
> -static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> -				irq_hw_number_t hw_irq)
> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> +			 irq_hw_number_t hw_irq)
>  {
>  	struct irq_data *data = irq_get_irq_data(virq);
>  	struct irq_domain_chip_generic *dgc = d->gc;
> @@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>  	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(irq_map_generic_chip);
>  
>  struct irq_domain_ops irq_generic_chip_ops = {
>  	.map	= irq_map_generic_chip,

Why can't you use irq_generic_chip_ops.map in your code and avoid this
patch entirely?

thx,

Jason.
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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Boris BREZILLON]

On 22/06/2014 01:51, Jason Cooper wrote:
> On Fri, Jun 20, 2014 at 05:01:21PM +0200, Boris BREZILLON wrote:
>> Export the generic irq map function in order to provide irq_domain ops with
>> generic mapping and specific of xlate function (needed by the new atmel
>> AIC driver).
>>
>> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> ---
>>  include/linux/irq.h       | 2 ++
>>  kernel/irq/generic-chip.c | 5 +++--
>>  2 files changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/include/linux/irq.h b/include/linux/irq.h
>> index 0d998d8..62af592 100644
>> --- a/include/linux/irq.h
>> +++ b/include/linux/irq.h
>> @@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
>>  int irq_gc_set_wake(struct irq_data *d, unsigned int on);
>>  
>>  /* Setup functions for irq_chip_generic */
>> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>> +			 irq_hw_number_t hw_irq);
>>  struct irq_chip_generic *
>>  irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
>>  		       void __iomem *reg_base, irq_flow_handler_t handler);
>> diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
>> index 452d6f2..cf80e7b 100644
>> --- a/kernel/irq/generic-chip.c
>> +++ b/kernel/irq/generic-chip.c
>> @@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
>>  /*
>>   * irq_map_generic_chip - Map a generic chip for an irq domain
>>   */
>> -static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>> -				irq_hw_number_t hw_irq)
>> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>> +			 irq_hw_number_t hw_irq)
>>  {
>>  	struct irq_data *data = irq_get_irq_data(virq);
>>  	struct irq_domain_chip_generic *dgc = d->gc;
>> @@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>  	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
>>  	return 0;
>>  }
>> +EXPORT_SYMBOL_GPL(irq_map_generic_chip);
>>  
>>  struct irq_domain_ops irq_generic_chip_ops = {
>>  	.map	= irq_map_generic_chip,
> Why can't you use irq_generic_chip_ops.map in your code and avoid this
> patch entirely?

Because in this case I'll have to remove constness from my
irq_domain_ops struct and initialize it in my init function.
This is not a big concern, but in general I tend to declare ops struct
with a const constraint.

Tell me if you still want me to drop this patch and rework my init process.

Best Regards,

Boris


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Jason Cooper]

On Sun, Jun 22, 2014 at 09:59:44AM +0200, Boris BREZILLON wrote:
> 
> On 22/06/2014 01:51, Jason Cooper wrote:
> > On Fri, Jun 20, 2014 at 05:01:21PM +0200, Boris BREZILLON wrote:
> >> Export the generic irq map function in order to provide irq_domain ops with
> >> generic mapping and specific of xlate function (needed by the new atmel
> >> AIC driver).
> >>
> >> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >> ---
> >>  include/linux/irq.h       | 2 ++
> >>  kernel/irq/generic-chip.c | 5 +++--
> >>  2 files changed, 5 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/include/linux/irq.h b/include/linux/irq.h
> >> index 0d998d8..62af592 100644
> >> --- a/include/linux/irq.h
> >> +++ b/include/linux/irq.h
> >> @@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
> >>  int irq_gc_set_wake(struct irq_data *d, unsigned int on);
> >>  
> >>  /* Setup functions for irq_chip_generic */
> >> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> >> +			 irq_hw_number_t hw_irq);
> >>  struct irq_chip_generic *
> >>  irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
> >>  		       void __iomem *reg_base, irq_flow_handler_t handler);
> >> diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
> >> index 452d6f2..cf80e7b 100644
> >> --- a/kernel/irq/generic-chip.c
> >> +++ b/kernel/irq/generic-chip.c
> >> @@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
> >>  /*
> >>   * irq_map_generic_chip - Map a generic chip for an irq domain
> >>   */
> >> -static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> >> -				irq_hw_number_t hw_irq)
> >> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> >> +			 irq_hw_number_t hw_irq)
> >>  {
> >>  	struct irq_data *data = irq_get_irq_data(virq);
> >>  	struct irq_domain_chip_generic *dgc = d->gc;
> >> @@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> >>  	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
> >>  	return 0;
> >>  }
> >> +EXPORT_SYMBOL_GPL(irq_map_generic_chip);
> >>  
> >>  struct irq_domain_ops irq_generic_chip_ops = {
> >>  	.map	= irq_map_generic_chip,
> > Why can't you use irq_generic_chip_ops.map in your code and avoid this

s/code/declaration/, sorry for the misunderstanding.

> > patch entirely?
> 
> Because in this case I'll have to remove constness from my
> irq_domain_ops struct and initialize it in my init function.
> This is not a big concern, but in general I tend to declare ops struct
> with a const constraint.

/*
 * We're the only user of irq_map_generic_chip() who
 * doesn't also use irq_domain_xlate_onetwocell()
 */
static const struct irq_domain_ops aic_irq_ops = {
	.map    = irq_generic_chip_ops.map,
        .xlate  = aic_irq_domain_xlate,
};

Wouldn't work?

> Tell me if you still want me to drop this patch and rework my init process.

If the above is satisfactory for you, please do so.  If we get a few
more chips that need one function, but not the other, then we'll revisit
what we're exporting.  The comment should bring the issue up in a
future grep.

thx,

Jason.
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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Boris BREZILLON]

On 23/06/2014 15:07, Jason Cooper wrote:
> On Sun, Jun 22, 2014 at 09:59:44AM +0200, Boris BREZILLON wrote:
>> On 22/06/2014 01:51, Jason Cooper wrote:
>>> On Fri, Jun 20, 2014 at 05:01:21PM +0200, Boris BREZILLON wrote:
>>>> Export the generic irq map function in order to provide irq_domain ops with
>>>> generic mapping and specific of xlate function (needed by the new atmel
>>>> AIC driver).
>>>>
>>>> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>>> ---
>>>>  include/linux/irq.h       | 2 ++
>>>>  kernel/irq/generic-chip.c | 5 +++--
>>>>  2 files changed, 5 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/include/linux/irq.h b/include/linux/irq.h
>>>> index 0d998d8..62af592 100644
>>>> --- a/include/linux/irq.h
>>>> +++ b/include/linux/irq.h
>>>> @@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
>>>>  int irq_gc_set_wake(struct irq_data *d, unsigned int on);
>>>>  
>>>>  /* Setup functions for irq_chip_generic */
>>>> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>>> +			 irq_hw_number_t hw_irq);
>>>>  struct irq_chip_generic *
>>>>  irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
>>>>  		       void __iomem *reg_base, irq_flow_handler_t handler);
>>>> diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
>>>> index 452d6f2..cf80e7b 100644
>>>> --- a/kernel/irq/generic-chip.c
>>>> +++ b/kernel/irq/generic-chip.c
>>>> @@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
>>>>  /*
>>>>   * irq_map_generic_chip - Map a generic chip for an irq domain
>>>>   */
>>>> -static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>>> -				irq_hw_number_t hw_irq)
>>>> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>>> +			 irq_hw_number_t hw_irq)
>>>>  {
>>>>  	struct irq_data *data = irq_get_irq_data(virq);
>>>>  	struct irq_domain_chip_generic *dgc = d->gc;
>>>> @@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>>>  	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
>>>>  	return 0;
>>>>  }
>>>> +EXPORT_SYMBOL_GPL(irq_map_generic_chip);
>>>>  
>>>>  struct irq_domain_ops irq_generic_chip_ops = {
>>>>  	.map	= irq_map_generic_chip,
>>> Why can't you use irq_generic_chip_ops.map in your code and avoid this
> s/code/declaration/, sorry for the misunderstanding.
>
>>> patch entirely?
>> Because in this case I'll have to remove constness from my
>> irq_domain_ops struct and initialize it in my init function.
>> This is not a big concern, but in general I tend to declare ops struct
>> with a const constraint.
> /*
>  * We're the only user of irq_map_generic_chip() who
>  * doesn't also use irq_domain_xlate_onetwocell()
>  */
> static const struct irq_domain_ops aic_irq_ops = {
> 	.map    = irq_generic_chip_ops.map,
>         .xlate  = aic_irq_domain_xlate,
> };
>
> Wouldn't work?

No, it fails  with :

"error: initializer element is not constant"


>
>> Tell me if you still want me to drop this patch and rework my init process.
> If the above is satisfactory for you, please do so.  If we get a few
> more chips that need one function, but not the other, then we'll revisit
> what we're exporting.  The comment should bring the issue up in a
> future grep.
>
> thx,
>
> Jason.

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Jason Cooper]

On Mon, Jun 23, 2014 at 05:07:47PM +0200, Boris BREZILLON wrote:
> 
> On 23/06/2014 15:07, Jason Cooper wrote:
> > On Sun, Jun 22, 2014 at 09:59:44AM +0200, Boris BREZILLON wrote:
> >> On 22/06/2014 01:51, Jason Cooper wrote:
> >>> On Fri, Jun 20, 2014 at 05:01:21PM +0200, Boris BREZILLON wrote:
> >>>> Export the generic irq map function in order to provide irq_domain ops with
> >>>> generic mapping and specific of xlate function (needed by the new atmel
> >>>> AIC driver).
> >>>>
> >>>> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >>>> ---
> >>>>  include/linux/irq.h       | 2 ++
> >>>>  kernel/irq/generic-chip.c | 5 +++--
> >>>>  2 files changed, 5 insertions(+), 2 deletions(-)
> >>>>
> >>>> diff --git a/include/linux/irq.h b/include/linux/irq.h
> >>>> index 0d998d8..62af592 100644
> >>>> --- a/include/linux/irq.h
> >>>> +++ b/include/linux/irq.h
> >>>> @@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
> >>>>  int irq_gc_set_wake(struct irq_data *d, unsigned int on);
> >>>>  
> >>>>  /* Setup functions for irq_chip_generic */
> >>>> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> >>>> +			 irq_hw_number_t hw_irq);
> >>>>  struct irq_chip_generic *
> >>>>  irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
> >>>>  		       void __iomem *reg_base, irq_flow_handler_t handler);
> >>>> diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
> >>>> index 452d6f2..cf80e7b 100644
> >>>> --- a/kernel/irq/generic-chip.c
> >>>> +++ b/kernel/irq/generic-chip.c
> >>>> @@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
> >>>>  /*
> >>>>   * irq_map_generic_chip - Map a generic chip for an irq domain
> >>>>   */
> >>>> -static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> >>>> -				irq_hw_number_t hw_irq)
> >>>> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> >>>> +			 irq_hw_number_t hw_irq)
> >>>>  {
> >>>>  	struct irq_data *data = irq_get_irq_data(virq);
> >>>>  	struct irq_domain_chip_generic *dgc = d->gc;
> >>>> @@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> >>>>  	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
> >>>>  	return 0;
> >>>>  }
> >>>> +EXPORT_SYMBOL_GPL(irq_map_generic_chip);
> >>>>  
> >>>>  struct irq_domain_ops irq_generic_chip_ops = {
> >>>>  	.map	= irq_map_generic_chip,
> >>> Why can't you use irq_generic_chip_ops.map in your code and avoid this
> > s/code/declaration/, sorry for the misunderstanding.
> >
> >>> patch entirely?
> >> Because in this case I'll have to remove constness from my
> >> irq_domain_ops struct and initialize it in my init function.
> >> This is not a big concern, but in general I tend to declare ops struct
> >> with a const constraint.
> > /*
> >  * We're the only user of irq_map_generic_chip() who
> >  * doesn't also use irq_domain_xlate_onetwocell()
> >  */
> > static const struct irq_domain_ops aic_irq_ops = {
> > 	.map    = irq_generic_chip_ops.map,
> >         .xlate  = aic_irq_domain_xlate,
> > };
> >
> > Wouldn't work?
> 
> No, it fails  with :
> 
> "error: initializer element is not constant"

Gah!  Of course.  That's what I get for pseudo-coding without sufficient
coffee. :)

I won't have a chance to dig deeper into this until tonight or the next
few days.  But my primary concern is that they chose to export the
struct for a reason.  I'd like to dig through the history and find out
why.

Assuming there's no big reason not to export the function(s) directly,
I'm fine with exporting them.  But it would be nice to get Thomas' Ack
before I take the original patch since it touches core code.

thx,

Jason.
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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Boris BREZILLON]

On 23/06/2014 19:50, Jason Cooper wrote:
> On Mon, Jun 23, 2014 at 05:07:47PM +0200, Boris BREZILLON wrote:
>> On 23/06/2014 15:07, Jason Cooper wrote:
>>> On Sun, Jun 22, 2014 at 09:59:44AM +0200, Boris BREZILLON wrote:
>>>> On 22/06/2014 01:51, Jason Cooper wrote:
>>>>> On Fri, Jun 20, 2014 at 05:01:21PM +0200, Boris BREZILLON wrote:
>>>>>> Export the generic irq map function in order to provide irq_domain ops with
>>>>>> generic mapping and specific of xlate function (needed by the new atmel
>>>>>> AIC driver).
>>>>>>
>>>>>> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>>>>> ---
>>>>>>  include/linux/irq.h       | 2 ++
>>>>>>  kernel/irq/generic-chip.c | 5 +++--
>>>>>>  2 files changed, 5 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/include/linux/irq.h b/include/linux/irq.h
>>>>>> index 0d998d8..62af592 100644
>>>>>> --- a/include/linux/irq.h
>>>>>> +++ b/include/linux/irq.h
>>>>>> @@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
>>>>>>  int irq_gc_set_wake(struct irq_data *d, unsigned int on);
>>>>>>  
>>>>>>  /* Setup functions for irq_chip_generic */
>>>>>> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>>>>> +			 irq_hw_number_t hw_irq);
>>>>>>  struct irq_chip_generic *
>>>>>>  irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
>>>>>>  		       void __iomem *reg_base, irq_flow_handler_t handler);
>>>>>> diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
>>>>>> index 452d6f2..cf80e7b 100644
>>>>>> --- a/kernel/irq/generic-chip.c
>>>>>> +++ b/kernel/irq/generic-chip.c
>>>>>> @@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
>>>>>>  /*
>>>>>>   * irq_map_generic_chip - Map a generic chip for an irq domain
>>>>>>   */
>>>>>> -static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>>>>> -				irq_hw_number_t hw_irq)
>>>>>> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>>>>> +			 irq_hw_number_t hw_irq)
>>>>>>  {
>>>>>>  	struct irq_data *data = irq_get_irq_data(virq);
>>>>>>  	struct irq_domain_chip_generic *dgc = d->gc;
>>>>>> @@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>>>>>>  	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
>>>>>>  	return 0;
>>>>>>  }
>>>>>> +EXPORT_SYMBOL_GPL(irq_map_generic_chip);
>>>>>>  
>>>>>>  struct irq_domain_ops irq_generic_chip_ops = {
>>>>>>  	.map	= irq_map_generic_chip,
>>>>> Why can't you use irq_generic_chip_ops.map in your code and avoid this
>>> s/code/declaration/, sorry for the misunderstanding.
>>>
>>>>> patch entirely?
>>>> Because in this case I'll have to remove constness from my
>>>> irq_domain_ops struct and initialize it in my init function.
>>>> This is not a big concern, but in general I tend to declare ops struct
>>>> with a const constraint.
>>> /*
>>>  * We're the only user of irq_map_generic_chip() who
>>>  * doesn't also use irq_domain_xlate_onetwocell()
>>>  */
>>> static const struct irq_domain_ops aic_irq_ops = {
>>> 	.map    = irq_generic_chip_ops.map,
>>>         .xlate  = aic_irq_domain_xlate,
>>> };
>>>
>>> Wouldn't work?
>> No, it fails  with :
>>
>> "error: initializer element is not constant"
> Gah!  Of course.  That's what I get for pseudo-coding without sufficient
> coffee. :)
>
> I won't have a chance to dig deeper into this until tonight or the next
> few days.  But my primary concern is that they chose to export the
> struct for a reason.  I'd like to dig through the history and find out
> why.

IMHO exporting both (the struct and the functions independently) makes
sense.
The struct can be used by drivers that have a standard behaviour for
both xslate and map functions, and functions (irq_map_generic_chip or
irq_domain_xlate_onetwocell) could be used when only one end of the
implementation is standard.

BTW, shouldn't we declare irq_generic_chip_ops as a const instance to
prevent users from modifying its content ?

>
> Assuming there's no big reason not to export the function(s) directly,
> I'm fine with exporting them.  But it would be nice to get Thomas' Ack
> before I take the original patch since it touches core code.

Sure.

Thanks for your help.

Best Regards,

Boris

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Jason Cooper]

> On 23/06/2014 19:50, Jason Cooper wrote:
...
> > I won't have a chance to dig deeper into this until tonight or the next
> > few days.  But my primary concern is that they chose to export the
> > struct for a reason.  I'd like to dig through the history and find out
> > why.

Ok, I took a look.  It seems that was the most expedient way to
implement the linear domain registration.  No mention of avoiding
exporting the functions directly. :)

thx,

Jason.
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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Jason Cooper]

Thomas,

Would you mind Acking this and letting me know how you'd like me to
handle it?  It's a build requirement for the rest of the series, but
it's in core code.

I can do a separate topic branch for you or just merge it in with
irqchip/core.  Whichever is easiest for you.

On Fri, Jun 20, 2014 at 05:01:21PM +0200, Boris BREZILLON wrote:
> Export the generic irq map function in order to provide irq_domain ops with
> generic mapping and specific of xlate function (needed by the new atmel
> AIC driver).
> 
> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
>  include/linux/irq.h       | 2 ++
>  kernel/irq/generic-chip.c | 5 +++--
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/include/linux/irq.h b/include/linux/irq.h
> index 0d998d8..62af592 100644
> --- a/include/linux/irq.h
> +++ b/include/linux/irq.h
> @@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
>  int irq_gc_set_wake(struct irq_data *d, unsigned int on);
>  
>  /* Setup functions for irq_chip_generic */
> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> +			 irq_hw_number_t hw_irq);
>  struct irq_chip_generic *
>  irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
>  		       void __iomem *reg_base, irq_flow_handler_t handler);
> diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
> index 452d6f2..cf80e7b 100644
> --- a/kernel/irq/generic-chip.c
> +++ b/kernel/irq/generic-chip.c
> @@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
>  /*
>   * irq_map_generic_chip - Map a generic chip for an irq domain
>   */
> -static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> -				irq_hw_number_t hw_irq)
> +int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
> +			 irq_hw_number_t hw_irq)
>  {
>  	struct irq_data *data = irq_get_irq_data(virq);
>  	struct irq_domain_chip_generic *dgc = d->gc;
> @@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
>  	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(irq_map_generic_chip);
>  
>  struct irq_domain_ops irq_generic_chip_ops = {
>  	.map	= irq_map_generic_chip,
> -- 
> 1.8.3.2
> 

thx,

Jason.
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Re: [PATCH v3 1/7] genirq: generic chip: export irq_map_generic_chip function

[Thomas Gleixner]

On Mon, 23 Jun 2014, Jason Cooper wrote:

> Thomas,
> 
> Would you mind Acking this and letting me know how you'd like me to
> handle it?  It's a build requirement for the rest of the series, but
> it's in core code.
> 
> I can do a separate topic branch for you or just merge it in with
> irqchip/core.  Whichever is easiest for you.

Just keep it in the series.

Acked-by: Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
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[PATCH v3 3/7] irqchip: atmel-aic: add new atmel AIC driver

[Boris BREZILLON]

Add new atmel AIC (Advanced Interrupt Controller) driver based on the
generic chip infrastructure.

This driver is only compatible with dt enabled board and replaces the old
implementation found in arch/arm/mach-at91/irq.c.

Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 drivers/irqchip/Kconfig         |   7 +
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-atmel-aic.c | 700 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 708 insertions(+)
 create mode 100644 drivers/irqchip/irq-atmel-aic.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bbb746e..6a7ad81 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,13 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config ATMEL_AIC_IRQ
+	bool
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
+
 config BRCMSTB_L2_IRQ
 	bool
 	depends on ARM
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 62a13e5..c60929c 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)			+= irq-gic.o
 obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o
 obj-$(CONFIG_ARM_VIC)			+= irq-vic.o
+obj-$(CONFIG_ATMEL_AIC_IRQ)		+= irq-atmel-aic.o
 obj-$(CONFIG_IMGPDC_IRQ)		+= irq-imgpdc.o
 obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
 obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
diff --git a/drivers/irqchip/irq-atmel-aic.c b/drivers/irqchip/irq-atmel-aic.c
new file mode 100644
index 0000000..5947ef0
--- /dev/null
+++ b/drivers/irqchip/irq-atmel-aic.c
@@ -0,0 +1,700 @@
+/*
+ * Atmel AT91 AIC (Advanced Interrupt Controller) driver
+ *
+ *  Copyright (C) 2004 SAN People
+ *  Copyright (C) 2004 ATMEL
+ *  Copyright (C) Rick Bronson
+ *  Copyright (C) 2013 Boris BREZILLON <b.brezillon-ZNYIgs0QAGpBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/bitmap.h>
+#include <linux/types.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#include "irqchip.h"
+
+/* Number of irq lines managed by AIC */
+#define NR_AIC_IRQS	32
+#define NR_AIC5_IRQS	128
+
+#define AT91_AIC5_SSR		0x0
+#define		AT91_AIC5_INTSEL_MSK	(0x7f << 0)
+
+#define AT91_AIC_IRQ_MIN_PRIORITY	0
+#define AT91_AIC_IRQ_MAX_PRIORITY	7
+
+#define AT91_AIC_SMR(n)			((n) * 4)
+#define AT91_AIC5_SMR			0x4
+#define AT91_AIC_PRIOR			(7 << 0)
+#define AT91_AIC_SRCTYPE		(3 << 5)
+#define AT91_AIC_SRCTYPE_LOW		(0 << 5)
+#define AT91_AIC_SRCTYPE_FALLING	(1 << 5)
+#define AT91_AIC_SRCTYPE_HIGH		(2 << 5)
+#define AT91_AIC_SRCTYPE_RISING		(3 << 5)
+
+#define AT91_AIC_SVR(n)			(0x80 + ((n) * 4))
+#define AT91_AIC5_SVR			0x8
+#define AT91_AIC_IVR			0x100
+#define AT91_AIC5_IVR			0x10
+#define AT91_AIC_FVR			0x104
+#define AT91_AIC5_FVR			0x14
+#define AT91_AIC_ISR			0x108
+#define AT91_AIC5_ISR			0x18
+#define AT91_AIC_IRQID			(0x1f << 0)
+
+#define AT91_AIC_IPR			0x10c
+#define AT91_AIC5_IPR0			0x20
+#define AT91_AIC5_IPR1			0x24
+#define AT91_AIC5_IPR2			0x28
+#define AT91_AIC5_IPR3			0x2c
+#define AT91_AIC_IMR			0x110
+#define AT91_AIC5_IMR			0x30
+#define AT91_AIC_CISR			0x114
+#define AT91_AIC5_CISR			0x34
+#define AT91_AIC_NFIQ			BIT(0)
+#define AT91_AIC_NIRQ			BIT(1)
+
+#define AT91_AIC_IECR			0x120
+#define AT91_AIC5_IECR			0x40
+#define AT91_AIC_IDCR			0x124
+#define AT91_AIC5_IDCR			0x44
+#define AT91_AIC_ICCR			0x128
+#define AT91_AIC5_ICCR			0x48
+#define AT91_AIC_ISCR			0x12c
+#define AT91_AIC5_ISCR			0x4c
+#define AT91_AIC_EOICR			0x130
+#define AT91_AIC5_EOICR			0x38
+#define AT91_AIC_SPU			0x134
+#define AT91_AIC5_SPU			0x3c
+#define AT91_AIC_DCR			0x138
+#define AT91_AIC5_DCR			0x6c
+#define AT91_AIC_DCR_PROT		BIT(0)
+#define AT91_AIC_DCR_GMSK		BIT(1)
+
+#define AT91_AIC_FFER			0x140
+#define AT91_AIC5_FFER			0x50
+#define AT91_AIC_FFDR			0x144
+#define AT91_AIC5_FFDR			0x54
+#define AT91_AIC_FFSR			0x148
+#define AT91_AIC5_FFSR			0x58
+
+struct aic_chip_data {
+	u32 ext_irqs;
+};
+
+static struct irq_domain *aic_domain;
+
+static asmlinkage void __exception_irq_entry
+aic_handle(struct pt_regs *regs)
+{
+	struct irq_domain_chip_generic *dgc = aic_domain->gc;
+	struct irq_chip_generic *gc = dgc->gc[0];
+	u32 irqnr;
+	u32 irqstat;
+
+	irqnr = irq_reg_readl(gc->reg_base + AT91_AIC_IVR);
+	irqstat = irq_reg_readl(gc->reg_base + AT91_AIC_ISR);
+
+	irqnr = irq_find_mapping(aic_domain, irqnr);
+
+	if (!irqstat)
+		irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
+	else
+		handle_IRQ(irqnr, regs);
+}
+
+static asmlinkage void __exception_irq_entry
+aic5_handle(struct pt_regs *regs)
+{
+	struct irq_domain_chip_generic *dgc = aic_domain->gc;
+	struct irq_chip_generic *gc = dgc->gc[0];
+	u32 irqnr;
+	u32 irqstat;
+
+	irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR);
+	irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR);
+
+	irqnr = irq_find_mapping(aic_domain, irqnr);
+
+	if (!irqstat)
+		irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
+	else
+		handle_IRQ(irqnr, regs);
+}
+
+static void aic5_mask(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct irq_domain_chip_generic *dgc = domain->gc;
+	struct irq_chip_generic *gc = dgc->gc[0];
+
+	/* Disable interrupt on AIC5 */
+	irq_gc_lock(gc);
+	irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
+	irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
+	gc->mask_cache &= ~d->mask;
+	irq_gc_unlock(gc);
+}
+
+static void aic5_unmask(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct irq_domain_chip_generic *dgc = domain->gc;
+	struct irq_chip_generic *gc = dgc->gc[0];
+
+	/* Enable interrupt on AIC5 */
+	irq_gc_lock(gc);
+	irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
+	irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR);
+	gc->mask_cache |= d->mask;
+	irq_gc_unlock(gc);
+}
+
+static int aic_retrigger(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+
+	/* Enable interrupt on AIC5 */
+	irq_gc_lock(gc);
+	irq_reg_writel(d->mask, gc->reg_base + AT91_AIC_ISCR);
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static int aic5_retrigger(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct irq_domain_chip_generic *dgc = domain->gc;
+	struct irq_chip_generic *gc = dgc->gc[0];
+
+	/* Enable interrupt on AIC5 */
+	irq_gc_lock(gc);
+	irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
+	irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR);
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static int aic_to_srctype(struct irq_data *d, unsigned type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct aic_chip_data *aic = gc->private;
+
+	switch (type) {
+	case IRQ_TYPE_LEVEL_HIGH:
+		return AT91_AIC_SRCTYPE_HIGH;
+	case IRQ_TYPE_EDGE_RISING:
+		return AT91_AIC_SRCTYPE_RISING;
+	case IRQ_TYPE_LEVEL_LOW:
+		if (d->mask & aic->ext_irqs)
+			return AT91_AIC_SRCTYPE_LOW;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		if (d->mask & aic->ext_irqs)
+			return AT91_AIC_SRCTYPE_FALLING;
+		break;
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static int aic_set_type(struct irq_data *d, unsigned type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	unsigned int smr;
+	int srctype;
+
+	srctype = aic_to_srctype(d, type);
+	if (srctype < 0)
+		return srctype;
+
+	smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(d->hwirq)) &
+	      ~AT91_AIC_SRCTYPE;
+	irq_reg_writel(smr | srctype, gc->reg_base + AT91_AIC_SMR(d->hwirq));
+
+	return 0;
+}
+
+static int aic5_set_type(struct irq_data *d, unsigned type)
+{
+	struct irq_domain *domain = d->domain;
+	struct irq_domain_chip_generic *dgc = domain->gc;
+	struct irq_chip_generic *gc = dgc->gc[0];
+	unsigned int smr;
+	int srctype;
+
+	srctype = aic_to_srctype(d, type);
+	if (srctype < 0)
+		return srctype;
+
+	irq_gc_lock(gc);
+	irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
+	smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
+	irq_reg_writel(smr | srctype, gc->reg_base + AT91_AIC5_SMR);
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static void aic_shutdown(struct irq_data *d)
+{
+	struct irq_chip_type *ct = irq_data_get_chip_type(d);
+
+	ct->chip.irq_mask(d);
+}
+
+#ifdef CONFIG_PM
+static void aic_suspend(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+
+	irq_gc_lock(gc);
+	irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IDCR);
+	irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IECR);
+	irq_gc_unlock(gc);
+}
+
+static void aic5_suspend(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct irq_domain_chip_generic *dgc = domain->gc;
+	struct irq_chip_generic *bgc = dgc->gc[0];
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	int i;
+	u32 mask;
+
+	irq_gc_lock(bgc);
+	for (i = 0; i < dgc->irqs_per_chip; i++) {
+		mask = 1 << i;
+		if ((mask & gc->mask_cache) == (mask & gc->wake_active))
+			continue;
+
+		irq_reg_writel(i + gc->irq_base,
+			       bgc->reg_base + AT91_AIC5_SSR);
+		if (mask & gc->wake_active)
+			irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
+		else
+			irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
+	}
+	irq_gc_unlock(bgc);
+}
+
+static void aic_resume(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+
+	irq_gc_lock(gc);
+	irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IDCR);
+	irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IECR);
+	irq_gc_unlock(gc);
+}
+
+static void aic5_resume(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct irq_domain_chip_generic *dgc = domain->gc;
+	struct irq_chip_generic *bgc = dgc->gc[0];
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	int i;
+	u32 mask;
+
+	irq_gc_lock(bgc);
+	for (i = 0; i < dgc->irqs_per_chip; i++) {
+		mask = 1 << i;
+		if ((mask & gc->mask_cache) == (mask & gc->wake_active))
+			continue;
+
+		irq_reg_writel(i + gc->irq_base,
+			       bgc->reg_base + AT91_AIC5_SSR);
+		if (mask & gc->mask_cache)
+			irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
+		else
+			irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
+	}
+	irq_gc_unlock(bgc);
+}
+
+static void aic_pm_shutdown(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+
+	irq_gc_lock(gc);
+	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
+	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
+	irq_gc_unlock(gc);
+}
+
+static void aic5_pm_shutdown(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct irq_domain_chip_generic *dgc = domain->gc;
+	struct irq_chip_generic *bgc = dgc->gc[0];
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	int i;
+
+	irq_gc_lock(bgc);
+	for (i = 0; i < dgc->irqs_per_chip; i++) {
+		irq_reg_writel(i + gc->irq_base,
+			       bgc->reg_base + AT91_AIC5_SSR);
+		irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
+		irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR);
+	}
+	irq_gc_unlock(bgc);
+}
+#else
+#define aic_suspend		NULL
+#define aic5_suspend		NULL
+#define aic_resume		NULL
+#define aic5_resume		NULL
+#define aic_pm_shutdown		NULL
+#define aic5_pm_shutdown	NULL
+#endif /* CONFIG_PM */
+
+static void __init aic_hw_init(struct irq_domain *domain)
+{
+	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
+	int i;
+
+	/*
+	 * Perform 8 End Of Interrupt Command to make sure AIC
+	 * will not Lock out nIRQ
+	 */
+	for (i = 0; i < 8; i++)
+		irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
+
+	/*
+	 * Spurious Interrupt ID in Spurious Vector Register.
+	 * When there is no current interrupt, the IRQ Vector Register
+	 * reads the value stored in AIC_SPU
+	 */
+	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_SPU);
+
+	/* No debugging in AIC: Debug (Protect) Control Register */
+	irq_reg_writel(0, gc->reg_base + AT91_AIC_DCR);
+
+	/* Disable and clear all interrupts initially */
+	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
+	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
+
+	for (i = 0; i < 32; i++)
+		irq_reg_writel(i, gc->reg_base + AT91_AIC_SVR(i));
+}
+
+static void __init aic5_hw_init(struct irq_domain *domain)
+{
+	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
+	int i;
+
+	/*
+	 * Perform 8 End Of Interrupt Command to make sure AIC
+	 * will not Lock out nIRQ
+	 */
+	for (i = 0; i < 8; i++)
+		irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
+
+	/*
+	 * Spurious Interrupt ID in Spurious Vector Register.
+	 * When there is no current interrupt, the IRQ Vector Register
+	 * reads the value stored in AIC_SPU
+	 */
+	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU);
+
+	/* No debugging in AIC: Debug (Protect) Control Register */
+	irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR);
+
+	/* Disable and clear all interrupts initially */
+	for (i = 0; i < domain->revmap_size; i++) {
+		irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR);
+		irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR);
+		irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
+		irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR);
+	}
+}
+
+static int at91_aic_common_irq_domain_xlate(struct irq_domain *d,
+					    struct device_node *ctrlr,
+					    const u32 *intspec,
+					    unsigned int intsize,
+					    irq_hw_number_t *out_hwirq,
+					    unsigned int *out_type)
+{
+	if (WARN_ON(intsize < 3))
+		return -EINVAL;
+
+	if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) ||
+		    (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
+		return -EINVAL;
+
+	*out_hwirq = intspec[0];
+	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
+
+	return 0;
+}
+
+static int aic_irq_domain_xlate(struct irq_domain *d,
+				struct device_node *ctrlr,
+				const u32 *intspec, unsigned int intsize,
+				irq_hw_number_t *out_hwirq,
+				unsigned int *out_type)
+{
+	struct irq_domain_chip_generic *dgc = d->gc;
+	struct irq_chip_generic *gc;
+	unsigned long smr;
+	int idx;
+	int ret;
+
+	if (!dgc)
+		return -EINVAL;
+
+	ret = at91_aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
+					       out_hwirq, out_type);
+	if (ret)
+		return ret;
+
+	idx = intspec[0] / dgc->irqs_per_chip;
+	if (idx >= dgc->num_chips)
+		return -EINVAL;
+
+	gc = dgc->gc[idx];
+
+	irq_gc_lock(gc);
+	smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR) & ~AT91_AIC_PRIOR;
+	irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR);
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static const struct irq_domain_ops aic_irq_ops = {
+	.map	= irq_map_generic_chip,
+	.xlate	= aic_irq_domain_xlate,
+};
+
+static int aic5_irq_domain_xlate(struct irq_domain *d,
+				 struct device_node *ctrlr,
+				 const u32 *intspec, unsigned int intsize,
+				 irq_hw_number_t *out_hwirq,
+				 unsigned int *out_type)
+{
+	struct irq_domain_chip_generic *dgc = d->gc;
+	struct irq_chip_generic *gc;
+	unsigned long smr;
+	int ret;
+
+	if (!dgc)
+		return -EINVAL;
+
+	ret = at91_aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
+					       out_hwirq, out_type);
+	if (ret)
+		return ret;
+
+	gc = dgc->gc[0];
+
+	irq_gc_lock(gc);
+	irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR);
+	smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR) & ~AT91_AIC_PRIOR;
+	irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR);
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static const struct irq_domain_ops aic5_irq_ops = {
+	.map	= irq_map_generic_chip,
+	.xlate	= aic5_irq_domain_xlate,
+};
+
+static void __init aic_ext_irq_of_init(struct irq_domain *domain)
+{
+	struct device_node *node = domain->of_node;
+	struct irq_chip_generic *gc;
+	struct aic_chip_data *aic;
+	struct property *prop;
+	const __be32 *p;
+	u32 hwirq;
+
+	gc = irq_get_domain_generic_chip(aic_domain, 0);
+
+	aic = gc->private;
+	aic->ext_irqs |= 1;
+
+	of_property_for_each_u32(node, "atmel,external-irqs", prop, p, hwirq) {
+		gc = irq_get_domain_generic_chip(aic_domain, hwirq);
+		if (!gc) {
+			pr_warn("AIC: external irq %d >= %d skip it\n",
+				hwirq, domain->revmap_size);
+			continue;
+		}
+
+		aic = gc->private;
+		aic->ext_irqs |= (1 << (hwirq % 32));
+	}
+}
+
+static int __init aic_common_of_init(struct device_node *node,
+				     const struct irq_domain_ops *ops,
+				     const char *name, int nirqs)
+{
+	struct irq_chip_generic *gc;
+	struct aic_chip_data *aic;
+	void __iomem *reg_base;
+	int nchips;
+	int ret;
+	int i;
+
+	if (aic_domain)
+		return -EEXIST;
+
+	nchips = DIV_ROUND_UP(nirqs, 32);
+
+	reg_base = of_iomap(node, 0);
+	if (!reg_base)
+		return -ENOMEM;
+
+	aic = kcalloc(nchips, sizeof(*aic), GFP_KERNEL);
+	if (!aic) {
+		ret = -ENOMEM;
+		goto err_iounmap;
+	}
+
+	aic_domain = irq_domain_add_linear(node, nchips * 32, ops, aic);
+	if (!aic_domain) {
+		ret = -ENOMEM;
+		goto err_free_aic;
+	}
+
+	ret = irq_alloc_domain_generic_chips(aic_domain, 32, 1, name,
+					     handle_level_irq, 0, 0,
+					     IRQCHIP_SKIP_SET_WAKE);
+	if (ret)
+		goto err_domain_remove;
+
+	for (i = 0; i < nchips; i++) {
+		gc = irq_get_domain_generic_chip(aic_domain, i * 32);
+
+		gc->reg_base = reg_base;
+
+		gc->unused = 0;
+		gc->wake_enabled = ~0;
+		gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK;
+		gc->chip_types[0].handler = handle_fasteoi_irq;
+		gc->chip_types[0].chip.irq_eoi = irq_gc_eoi;
+		gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
+		gc->chip_types[0].chip.irq_shutdown = aic_shutdown;
+		gc->private = &aic[i];
+	}
+
+	aic_ext_irq_of_init(aic_domain);
+
+	return 0;
+
+err_domain_remove:
+	irq_domain_remove(aic_domain);
+
+err_free_aic:
+	kfree(aic);
+
+err_iounmap:
+	iounmap(reg_base);
+
+	return ret;
+}
+
+static int __init aic_of_init(struct device_node *node,
+			      struct device_node *parent)
+{
+	struct irq_chip_generic *gc;
+	int ret;
+
+	ret = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
+				 NR_AIC_IRQS);
+	if (ret)
+		return ret;
+
+	gc = irq_get_domain_generic_chip(aic_domain, 0);
+
+	gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
+	gc->chip_types[0].regs.enable = AT91_AIC_IECR;
+	gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
+	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
+	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
+	gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
+	gc->chip_types[0].chip.irq_set_type = aic_set_type;
+	gc->chip_types[0].chip.irq_suspend = aic_suspend;
+	gc->chip_types[0].chip.irq_resume = aic_resume;
+	gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;
+
+	aic_hw_init(aic_domain);
+	set_handle_irq(aic_handle);
+
+	return 0;
+}
+IRQCHIP_DECLARE(at91_aic, "atmel,at91rm9200-aic", aic_of_init);
+
+static int __init aic5_of_init(struct device_node *node,
+			       struct device_node *parent,
+			       int nirqs)
+{
+	struct irq_chip_generic *gc;
+	int ret;
+	int i;
+	int nchips;
+
+	if (nirqs > NR_AIC5_IRQS)
+		return -EINVAL;
+
+	ret = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5",
+				 nirqs);
+	if (ret)
+		return ret;
+
+	nchips = aic_domain->revmap_size / 32;
+	for (i = 0; i < nchips; i++) {
+		gc = irq_get_domain_generic_chip(aic_domain, i * 32);
+
+		gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;
+		gc->chip_types[0].chip.irq_mask = aic5_mask;
+		gc->chip_types[0].chip.irq_unmask = aic5_unmask;
+		gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;
+		gc->chip_types[0].chip.irq_set_type = aic5_set_type;
+		gc->chip_types[0].chip.irq_suspend = aic5_suspend;
+		gc->chip_types[0].chip.irq_resume = aic5_resume;
+		gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;
+	}
+
+	aic5_hw_init(aic_domain);
+	set_handle_irq(aic5_handle);
+
+	return 0;
+}
+
+#define NR_SAMA5D3_IRQS		50
+
+static int __init sama5d3_aic5_of_init(struct device_node *node,
+				       struct device_node *parent)
+{
+	return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
+}
+IRQCHIP_DECLARE(at91_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);
-- 
1.8.3.2

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Re: [PATCH v3 3/7] irqchip: atmel-aic: add new atmel AIC driver

[Boris BREZILLON]

On 20/06/2014 17:01, Boris BREZILLON wrote:
> Add new atmel AIC (Advanced Interrupt Controller) driver based on the
> generic chip infrastructure.
>
> This driver is only compatible with dt enabled board and replaces the old
> implementation found in arch/arm/mach-at91/irq.c.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
>  drivers/irqchip/Kconfig         |   7 +
>  drivers/irqchip/Makefile        |   1 +
>  drivers/irqchip/irq-atmel-aic.c | 700 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 708 insertions(+)
>  create mode 100644 drivers/irqchip/irq-atmel-aic.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index bbb746e..6a7ad81 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -30,6 +30,13 @@ config ARM_VIC_NR
>  	  The maximum number of VICs available in the system, for
>  	  power management.
>  

[...]

> +
> +static int at91_aic_common_irq_domain_xlate(struct irq_domain *d,

This function should be named aic_common_irq_domain_xslate to be
consistent with other function names.
I'll fix that for the next version.


Best Regards,

Boris

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v3 3/7] irqchip: atmel-aic: add new atmel AIC driver

[Jason Cooper]

Boris,

On Sun, Jun 22, 2014 at 10:56:54PM +0200, Boris BREZILLON wrote:
> 
> On 20/06/2014 17:01, Boris BREZILLON wrote:
> > Add new atmel AIC (Advanced Interrupt Controller) driver based on the
> > generic chip infrastructure.
> >
> > This driver is only compatible with dt enabled board and replaces the old
> > implementation found in arch/arm/mach-at91/irq.c.
> >
> > Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> > ---
> >  drivers/irqchip/Kconfig         |   7 +
> >  drivers/irqchip/Makefile        |   1 +
> >  drivers/irqchip/irq-atmel-aic.c | 700 ++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 708 insertions(+)
> >  create mode 100644 drivers/irqchip/irq-atmel-aic.c
> >
> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > index bbb746e..6a7ad81 100644
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -30,6 +30,13 @@ config ARM_VIC_NR
> >  	  The maximum number of VICs available in the system, for
> >  	  power management.
> >  
> 
> [...]
> 
> > +
> > +static int at91_aic_common_irq_domain_xlate(struct irq_domain *d,
> 
> This function should be named aic_common_irq_domain_xslate to be
> consistent with other function names.
> I'll fix that for the next version.

Other than this one change, this series looks good wrt to irqchip.  When
you respin, please adjust the patch subject lines like so:

  irqchip: atmel-aic: Add new atmel AIC driver

Note the capitalization.  Also, if you could add Thomas' Ack to the
first patch, that would be appreciated.

Once you post the new series, I assume it's ok to apply patches 1-3 to
irqchip/core, or are there some dependency considerations?

thx,

Jason.
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Re: [PATCH v3 3/7] irqchip: atmel-aic: add new atmel AIC driver

[Boris BREZILLON]

Hello Jason,

On 24/06/2014 14:56, Jason Cooper wrote:
> Boris,
>
> On Sun, Jun 22, 2014 at 10:56:54PM +0200, Boris BREZILLON wrote:
>> On 20/06/2014 17:01, Boris BREZILLON wrote:
>>> Add new atmel AIC (Advanced Interrupt Controller) driver based on the
>>> generic chip infrastructure.
>>>
>>> This driver is only compatible with dt enabled board and replaces the old
>>> implementation found in arch/arm/mach-at91/irq.c.
>>>
>>> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>> ---
>>>  drivers/irqchip/Kconfig         |   7 +
>>>  drivers/irqchip/Makefile        |   1 +
>>>  drivers/irqchip/irq-atmel-aic.c | 700 ++++++++++++++++++++++++++++++++++++++++
>>>  3 files changed, 708 insertions(+)
>>>  create mode 100644 drivers/irqchip/irq-atmel-aic.c
>>>
>>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>>> index bbb746e..6a7ad81 100644
>>> --- a/drivers/irqchip/Kconfig
>>> +++ b/drivers/irqchip/Kconfig
>>> @@ -30,6 +30,13 @@ config ARM_VIC_NR
>>>  	  The maximum number of VICs available in the system, for
>>>  	  power management.
>>>  
>> [...]
>>
>>> +
>>> +static int at91_aic_common_irq_domain_xlate(struct irq_domain *d,
>> This function should be named aic_common_irq_domain_xslate to be
>> consistent with other function names.
>> I'll fix that for the next version.
> Other than this one change, this series looks good wrt to irqchip.  When
> you respin, please adjust the patch subject lines like so:
>
>   irqchip: atmel-aic: Add new atmel AIC driver
>
> Note the capitalization.  Also, if you could add Thomas' Ack to the
> first patch, that would be appreciated.

Sure, I'll fix the commit message and add Thomas' ack.

>
> Once you post the new series, I assume it's ok to apply patches 1-3 to
> irqchip/core, or are there some dependency considerations?

Patches 6 and 7 depend on the 3 first patches, but we should be able to
merge them through the at91/arm-soc tree (Nicolas might have to rebase
its tree for 3.17 on irqchip/core after you have applied patches 1-3).

Anyway, I'd like to wait for at91 maintainers/developers reviews before
posting a new version.

Thanks for your support on this series.

Best Regards,

Boris

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v3 3/7] irqchip: atmel-aic: add new atmel AIC driver

[Jason Cooper]

On Tue, Jun 24, 2014 at 06:14:27PM +0200, Boris BREZILLON wrote:
> On 24/06/2014 14:56, Jason Cooper wrote:
...
> > Once you post the new series, I assume it's ok to apply patches 1-3 to
> > irqchip/core, or are there some dependency considerations?
> 
> Patches 6 and 7 depend on the 3 first patches, but we should be able to
> merge them through the at91/arm-soc tree (Nicolas might have to rebase
> its tree for 3.17 on irqchip/core after you have applied patches 1-3).

I'll create a topic branch for you when the time comes.  That way
arm-soc doesn't have to pull in any code it doesn't actually need (helps
with for-next testing).

Please give me a gentle reminder in the coverletter or comments when you
send the next version.

> Anyway, I'd like to wait for at91 maintainers/developers reviews before
> posting a new version.

Sure.

thx,

Jason.
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Re: [PATCH v3 3/7] irqchip: atmel-aic: add new atmel AIC driver

[Boris BREZILLON]

On 20/06/2014 17:01, Boris BREZILLON wrote:
> Add new atmel AIC (Advanced Interrupt Controller) driver based on the
> generic chip infrastructure.
>
> This driver is only compatible with dt enabled board and replaces the old
> implementation found in arch/arm/mach-at91/irq.c.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
>  drivers/irqchip/Kconfig         |   7 +
>  drivers/irqchip/Makefile        |   1 +
>  drivers/irqchip/irq-atmel-aic.c | 700 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 708 insertions(+)
>  create mode 100644 drivers/irqchip/irq-atmel-aic.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index bbb746e..6a7ad81 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -30,6 +30,13 @@ config ARM_VIC_NR
>  	  The maximum number of VICs available in the system, for
>  	  power management.
>  
> +config ATMEL_AIC_IRQ
> +	bool
> +	select GENERIC_IRQ_CHIP
> +	select IRQ_DOMAIN
> +	select MULTI_IRQ_HANDLER
> +	select SPARSE_IRQ
> +

I just though a bit about it and it might be better to split AIC and
AIC5 support in 2 different drivers, because the AIC is only available
on at91sam9/at91rm9200 SoCs and AIC5 only available on sama5 SoCs, and
AFAICT there is no combination of both controller in a singler SoC.

Jason, Thomas, let me know if you think this worth the trouble, and if
so, should I keep a common implementation (in irq-atmel-aic-common.c/.h)
for the shared functions/structures.

Best Regards,

Boris

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v3 3/7] irqchip: atmel-aic: add new atmel AIC driver

[Jason Cooper]

On Thu, Jun 26, 2014 at 10:20:24PM +0200, Boris BREZILLON wrote:
> 
> On 20/06/2014 17:01, Boris BREZILLON wrote:
> > Add new atmel AIC (Advanced Interrupt Controller) driver based on the
> > generic chip infrastructure.
> >
> > This driver is only compatible with dt enabled board and replaces the old
> > implementation found in arch/arm/mach-at91/irq.c.
> >
> > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> > ---
> >  drivers/irqchip/Kconfig         |   7 +
> >  drivers/irqchip/Makefile        |   1 +
> >  drivers/irqchip/irq-atmel-aic.c | 700 ++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 708 insertions(+)
> >  create mode 100644 drivers/irqchip/irq-atmel-aic.c
> >
> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > index bbb746e..6a7ad81 100644
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -30,6 +30,13 @@ config ARM_VIC_NR
> >  	  The maximum number of VICs available in the system, for
> >  	  power management.
> >  
> > +config ATMEL_AIC_IRQ
> > +	bool
> > +	select GENERIC_IRQ_CHIP
> > +	select IRQ_DOMAIN
> > +	select MULTI_IRQ_HANDLER
> > +	select SPARSE_IRQ
> > +
> 
> I just though a bit about it and it might be better to split AIC and
> AIC5 support in 2 different drivers, because the AIC is only available
> on at91sam9/at91rm9200 SoCs and AIC5 only available on sama5 SoCs, and
> AFAICT there is no combination of both controller in a singler SoC.
> 
> Jason, Thomas, let me know if you think this worth the trouble, and if
> so, should I keep a common implementation (in irq-atmel-aic-common.c/.h)
> for the shared functions/structures.

It sounds sensible, and we have a similar situation brewing with the gic
family.  I'd like to hear from the at91 maintainers, though.

thx,

Jason.

Re: [PATCH v3 3/7] irqchip: atmel-aic: add new atmel AIC driver

[Nicolas Ferre]

On 26/06/2014 22:30, Jason Cooper :
> On Thu, Jun 26, 2014 at 10:20:24PM +0200, Boris BREZILLON wrote:
>>
>> On 20/06/2014 17:01, Boris BREZILLON wrote:
>>> Add new atmel AIC (Advanced Interrupt Controller) driver based on the
>>> generic chip infrastructure.
>>>
>>> This driver is only compatible with dt enabled board and replaces the old
>>> implementation found in arch/arm/mach-at91/irq.c.
>>>
>>> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>> ---
>>>  drivers/irqchip/Kconfig         |   7 +
>>>  drivers/irqchip/Makefile        |   1 +
>>>  drivers/irqchip/irq-atmel-aic.c | 700 ++++++++++++++++++++++++++++++++++++++++
>>>  3 files changed, 708 insertions(+)
>>>  create mode 100644 drivers/irqchip/irq-atmel-aic.c
>>>
>>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>>> index bbb746e..6a7ad81 100644
>>> --- a/drivers/irqchip/Kconfig
>>> +++ b/drivers/irqchip/Kconfig
>>> @@ -30,6 +30,13 @@ config ARM_VIC_NR
>>>  	  The maximum number of VICs available in the system, for
>>>  	  power management.
>>>  
>>> +config ATMEL_AIC_IRQ
>>> +	bool
>>> +	select GENERIC_IRQ_CHIP
>>> +	select IRQ_DOMAIN
>>> +	select MULTI_IRQ_HANDLER
>>> +	select SPARSE_IRQ
>>> +
>>
>> I just though a bit about it and it might be better to split AIC and
>> AIC5 support in 2 different drivers, because the AIC is only available
>> on at91sam9/at91rm9200 SoCs and AIC5 only available on sama5 SoCs, and
>> AFAICT there is no combination of both controller in a singler SoC.
>>
>> Jason, Thomas, let me know if you think this worth the trouble, and if
>> so, should I keep a common implementation (in irq-atmel-aic-common.c/.h)
>> for the shared functions/structures.
> 
> It sounds sensible, and we have a similar situation brewing with the gic
> family.  I'd like to hear from the at91 maintainers, though.

Absolutely Boris and Jason. Re-reading the new AIC code it seems obvious
to split the 2 drivers, now that we have a nice framework in place, no
extra code is needed appart from both form of irq chip implementation.

Let's go this way. And of course, you have on the whole series my:

Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

Thanks, bye,
-- 
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[PATCH v3 4/7] ARM: at91: introduce OLD_IRQ_AT91 Kconfig option

[Boris BREZILLON]

Introduce the OLD_IRQ_AT91 Kconfig option to prepare migration to the
new AIC driver.

Select this option for all at91 SoCs and all available boards so that we
can later move DT enabled boards to the new irq driver and keep the old
implementation when legacy boards are selected.

Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 arch/arm/mach-at91/Kconfig        | 17 +++++++++--------
 arch/arm/mach-at91/Kconfig.non_dt |  6 ++++++
 arch/arm/mach-at91/Makefile       |  3 ++-
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 45b55e0..fbc1b68 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -28,6 +28,11 @@ config OLD_CLK_AT91
 	bool
 	default AT91_PMC_UNIT && AT91_USE_OLD_CLK
 
+config OLD_IRQ_AT91
+	bool
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
+
 config AT91_SAM9_ALT_RESET
 	bool
 	default !ARCH_AT91X40
@@ -47,16 +52,12 @@ config SOC_AT91SAM9
 	select AT91_SAM9_TIME
 	select CPU_ARM926T
 	select GENERIC_CLOCKEVENTS
-	select MULTI_IRQ_HANDLER
-	select SPARSE_IRQ
 
 config SOC_SAMA5
 	bool
 	select AT91_SAM9_TIME
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
-	select MULTI_IRQ_HANDLER
-	select SPARSE_IRQ
 	select USE_OF
 
 menu "Atmel AT91 System-on-Chip"
@@ -70,8 +71,7 @@ config ARCH_AT91X40
 	depends on !MMU
 	select CPU_ARM7TDMI
 	select ARCH_USES_GETTIMEOFFSET
-	select MULTI_IRQ_HANDLER
-	select SPARSE_IRQ
+	select OLD_IRQ_AT91
 
 	help
 	  Select this if you are using one of Atmel's AT91X40 SoC.
@@ -111,8 +111,6 @@ config SOC_AT91RM9200
 	select CPU_ARM920T
 	select GENERIC_CLOCKEVENTS
 	select HAVE_AT91_DBGU0
-	select MULTI_IRQ_HANDLER
-	select SPARSE_IRQ
 	select AT91_USE_OLD_CLK
 	select HAVE_AT91_USB_CLK
 
@@ -200,6 +198,7 @@ config MACH_AT91RM9200_DT
 	bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
 	depends on SOC_AT91RM9200
 	select USE_OF
+	select OLD_IRQ_AT91
 	help
 	  Select this if you want to experiment device-tree with
 	  an Atmel RM9200 Evaluation Kit.
@@ -208,6 +207,7 @@ config MACH_AT91SAM9_DT
 	bool "Atmel AT91SAM Evaluation Kits with device-tree support"
 	depends on SOC_AT91SAM9
 	select USE_OF
+	select OLD_IRQ_AT91
 	help
 	  Select this if you want to experiment device-tree with
 	  an Atmel Evaluation Kit.
@@ -216,6 +216,7 @@ config MACH_SAMA5_DT
 	bool "Atmel SAMA5 Evaluation Kits with device-tree support"
 	depends on SOC_SAMA5
 	select USE_OF
+	select OLD_IRQ_AT91
 	select PHYLIB if NETDEVICES
 	help
 	  Select this if you want to experiment device-tree with
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 44ace32..b774c3d 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -14,31 +14,37 @@ config ARCH_AT91RM9200
 	bool "AT91RM9200"
 	select SOC_AT91RM9200
 	select AT91_USE_OLD_CLK
+	select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9260
 	bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
 	select SOC_AT91SAM9260
 	select AT91_USE_OLD_CLK
+	select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9261
 	bool "AT91SAM9261 or AT91SAM9G10"
 	select SOC_AT91SAM9261
 	select AT91_USE_OLD_CLK
+	select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9263
 	bool "AT91SAM9263"
 	select SOC_AT91SAM9263
 	select AT91_USE_OLD_CLK
+	select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9RL
 	bool "AT91SAM9RL"
 	select SOC_AT91SAM9RL
 	select AT91_USE_OLD_CLK
+	select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9G45
 	bool "AT91SAM9G45"
 	select SOC_AT91SAM9G45
 	select AT91_USE_OLD_CLK
+	select OLD_IRQ_AT91
 
 endchoice
 
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 78e9cec..d972fd6 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,11 +2,12 @@
 # Makefile for the linux kernel.
 #
 
-obj-y		:= irq.o gpio.o setup.o sysirq_mask.o
+obj-y		:= gpio.o setup.o sysirq_mask.o
 obj-m		:=
 obj-n		:=
 obj-		:=
 
+obj-$(CONFIG_OLD_IRQ_AT91)	+= irq.o
 obj-$(CONFIG_OLD_CLK_AT91)	+= clock.o
 obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
 obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
-- 
1.8.3.2

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[PATCH v3 5/7] ARM: at91: enclose at91_aic_xx calls in IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks

[Boris BREZILLON]

Enclose at91_aic_xx calls in IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks in
order to prepare migration to the new AIC driver.

In the new AIC driver the suspend/resume functions are called by the
generic irq framework and are no longer needed in the PM specific code.

Moreover, the new AIC driver no longer exposes the at91_aic_base variable
which is used by the at91_aic_read functions.

Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 arch/arm/mach-at91/pm.c    | 32 ++++++++++++++++++++------------
 arch/arm/mach-at91/setup.c |  3 ++-
 2 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index e955545..5920373 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -206,16 +206,19 @@ static int at91_pm_enter(suspend_state_t state)
 		at91_pinctrl_gpio_suspend();
 	else
 		at91_gpio_suspend();
-	at91_irq_suspend();
 
-	pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
-			/* remember all the always-wake irqs */
-			(at91_pmc_read(AT91_PMC_PCSR)
-					| (1 << AT91_ID_FIQ)
-					| (1 << AT91_ID_SYS)
-					| (at91_get_extern_irq()))
-				& at91_aic_read(AT91_AIC_IMR),
-			state);
+	if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
+		at91_irq_suspend();
+
+		pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
+				/* remember all the always-wake irqs */
+				(at91_pmc_read(AT91_PMC_PCSR)
+						| (1 << AT91_ID_FIQ)
+						| (1 << AT91_ID_SYS)
+						| (at91_get_extern_irq()))
+					& at91_aic_read(AT91_AIC_IMR),
+				state);
+	}
 
 	switch (state) {
 		/*
@@ -280,12 +283,17 @@ static int at91_pm_enter(suspend_state_t state)
 			goto error;
 	}
 
-	pr_debug("AT91: PM - wakeup %08x\n",
-			at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR));
+	if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
+		pr_debug("AT91: PM - wakeup %08x\n",
+			 at91_aic_read(AT91_AIC_IPR) &
+			 at91_aic_read(AT91_AIC_IMR));
 
 error:
 	target_state = PM_SUSPEND_ON;
-	at91_irq_resume();
+
+	if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
+		at91_irq_resume();
+
 	if (of_have_populated_dt())
 		at91_pinctrl_gpio_resume();
 	else
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f7a07a5..0bf893a 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -49,7 +49,8 @@ void __init at91_init_irq_default(void)
 void __init at91_init_interrupts(unsigned int *priority)
 {
 	/* Initialize the AIC interrupt controller */
-	at91_aic_init(priority, at91_boot_soc.extern_irq);
+	if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
+		at91_aic_init(priority, at91_boot_soc.extern_irq);
 
 	/* Enable GPIO interrupts */
 	at91_gpio_irq_setup();
-- 
1.8.3.2

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[PATCH v3 7/7] ARM: at91: remove old irq material

[Boris BREZILLON]

Remove all the material related to AIC5 support: this interrupt controller
driver is now implemented in drivers/irqchip/atmel-aic.c.

Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 arch/arm/mach-at91/irq.c | 270 ++---------------------------------------------
 1 file changed, 6 insertions(+), 264 deletions(-)

diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 3d192c5..cdb3ec9 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -48,11 +48,6 @@ void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
 static struct device_node *at91_aic_np;
 static unsigned int n_irqs = NR_AIC_IRQS;
-static unsigned long at91_aic_caps = 0;
-
-/* AIC5 introduces a Source Select Register */
-#define AT91_AIC_CAP_AIC5	(1 << 0)
-#define has_aic5()		(at91_aic_caps & AT91_AIC_CAP_AIC5)
 
 #ifdef CONFIG_PM
 
@@ -92,50 +87,14 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 
 void at91_irq_suspend(void)
 {
-	int bit = -1;
-
-	if (has_aic5()) {
-		/* disable enabled irqs */
-		while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
-			at91_aic_write(AT91_AIC5_SSR,
-				       bit & AT91_AIC5_INTSEL_MSK);
-			at91_aic_write(AT91_AIC5_IDCR, 1);
-		}
-		/* enable wakeup irqs */
-		bit = -1;
-		while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
-			at91_aic_write(AT91_AIC5_SSR,
-				       bit & AT91_AIC5_INTSEL_MSK);
-			at91_aic_write(AT91_AIC5_IECR, 1);
-		}
-	} else {
-		at91_aic_write(AT91_AIC_IDCR, *backups);
-		at91_aic_write(AT91_AIC_IECR, *wakeups);
-	}
+	at91_aic_write(AT91_AIC_IDCR, *backups);
+	at91_aic_write(AT91_AIC_IECR, *wakeups);
 }
 
 void at91_irq_resume(void)
 {
-	int bit = -1;
-
-	if (has_aic5()) {
-		/* disable wakeup irqs */
-		while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
-			at91_aic_write(AT91_AIC5_SSR,
-				       bit & AT91_AIC5_INTSEL_MSK);
-			at91_aic_write(AT91_AIC5_IDCR, 1);
-		}
-		/* enable irqs disabled for suspend */
-		bit = -1;
-		while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
-			at91_aic_write(AT91_AIC5_SSR,
-				       bit & AT91_AIC5_INTSEL_MSK);
-			at91_aic_write(AT91_AIC5_IECR, 1);
-		}
-	} else {
-		at91_aic_write(AT91_AIC_IDCR, *wakeups);
-		at91_aic_write(AT91_AIC_IECR, *backups);
-	}
+	at91_aic_write(AT91_AIC_IDCR, *wakeups);
+	at91_aic_write(AT91_AIC_IECR, *backups);
 }
 
 #else
@@ -169,21 +128,6 @@ at91_aic_handle_irq(struct pt_regs *regs)
 		handle_IRQ(irqnr, regs);
 }
 
-asmlinkage void __exception_irq_entry
-at91_aic5_handle_irq(struct pt_regs *regs)
-{
-	u32 irqnr;
-	u32 irqstat;
-
-	irqnr = at91_aic_read(AT91_AIC5_IVR);
-	irqstat = at91_aic_read(AT91_AIC5_ISR);
-
-	if (!irqstat)
-		at91_aic_write(AT91_AIC5_EOICR, 0);
-	else
-		handle_IRQ(irqnr, regs);
-}
-
 static void at91_aic_mask_irq(struct irq_data *d)
 {
 	/* Disable interrupt on AIC */
@@ -192,15 +136,6 @@ static void at91_aic_mask_irq(struct irq_data *d)
 	clear_backup(d->hwirq);
 }
 
-static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
-{
-	/* Disable interrupt on AIC5 */
-	at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
-	at91_aic_write(AT91_AIC5_IDCR, 1);
-	/* Update ISR cache */
-	clear_backup(d->hwirq);
-}
-
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
 	/* Enable interrupt on AIC */
@@ -209,15 +144,6 @@ static void at91_aic_unmask_irq(struct irq_data *d)
 	set_backup(d->hwirq);
 }
 
-static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
-{
-	/* Enable interrupt on AIC5 */
-	at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
-	at91_aic_write(AT91_AIC5_IECR, 1);
-	/* Update ISR cache */
-	set_backup(d->hwirq);
-}
-
 static void at91_aic_eoi(struct irq_data *d)
 {
 	/*
@@ -227,11 +153,6 @@ static void at91_aic_eoi(struct irq_data *d)
 	at91_aic_write(AT91_AIC_EOICR, 0);
 }
 
-static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
-{
-	at91_aic_write(AT91_AIC5_EOICR, 0);
-}
-
 static unsigned long *at91_extern_irq;
 
 u32 at91_get_extern_irq(void)
@@ -282,16 +203,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
 	if (srctype < 0)
 		return srctype;
 
-	if (has_aic5()) {
-		at91_aic_write(AT91_AIC5_SSR,
-			       d->hwirq & AT91_AIC5_INTSEL_MSK);
-		smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
-		at91_aic_write(AT91_AIC5_SMR, smr | srctype);
-	} else {
-		smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
-		      & ~AT91_AIC_SRCTYPE;
-		at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
-	}
+	smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
+	at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
 
 	return 0;
 }
@@ -331,177 +244,6 @@ static void __init at91_aic_hw_init(unsigned int spu_vector)
 	at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 }
 
-static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
-{
-	int i;
-
-	/*
-	 * Perform 8 End Of Interrupt Command to make sure AIC
-	 * will not Lock out nIRQ
-	 */
-	for (i = 0; i < 8; i++)
-		at91_aic_write(AT91_AIC5_EOICR, 0);
-
-	/*
-	 * Spurious Interrupt ID in Spurious Vector Register.
-	 * When there is no current interrupt, the IRQ Vector Register
-	 * reads the value stored in AIC_SPU
-	 */
-	at91_aic_write(AT91_AIC5_SPU, spu_vector);
-
-	/* No debugging in AIC: Debug (Protect) Control Register */
-	at91_aic_write(AT91_AIC5_DCR, 0);
-
-	/* Disable and clear all interrupts initially */
-	for (i = 0; i < n_irqs; i++) {
-		at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
-		at91_aic_write(AT91_AIC5_IDCR, 1);
-		at91_aic_write(AT91_AIC5_ICCR, 1);
-	}
-}
-
-#if defined(CONFIG_OF)
-static unsigned int *at91_aic_irq_priorities;
-
-static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
-							irq_hw_number_t hw)
-{
-	/* Put virq number in Source Vector Register */
-	at91_aic_write(AT91_AIC_SVR(hw), virq);
-
-	/* Active Low interrupt, with priority */
-	at91_aic_write(AT91_AIC_SMR(hw),
-		       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
-
-	irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
-	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
-
-	return 0;
-}
-
-static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
-		irq_hw_number_t hw)
-{
-	at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
-
-	/* Put virq number in Source Vector Register */
-	at91_aic_write(AT91_AIC5_SVR, virq);
-
-	/* Active Low interrupt, with priority */
-	at91_aic_write(AT91_AIC5_SMR,
-		       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
-
-	irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
-	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
-
-	return 0;
-}
-
-static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
-				const u32 *intspec, unsigned int intsize,
-				irq_hw_number_t *out_hwirq, unsigned int *out_type)
-{
-	if (WARN_ON(intsize < 3))
-		return -EINVAL;
-	if (WARN_ON(intspec[0] >= n_irqs))
-		return -EINVAL;
-	if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
-		    || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
-		return -EINVAL;
-
-	*out_hwirq = intspec[0];
-	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
-	at91_aic_irq_priorities[*out_hwirq] = intspec[2];
-
-	return 0;
-}
-
-static struct irq_domain_ops at91_aic_irq_ops = {
-	.map	= at91_aic_irq_map,
-	.xlate	= at91_aic_irq_domain_xlate,
-};
-
-int __init at91_aic_of_common_init(struct device_node *node,
-				    struct device_node *parent)
-{
-	struct property *prop;
-	const __be32 *p;
-	u32 val;
-
-	at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
-				  * sizeof(*at91_extern_irq), GFP_KERNEL);
-	if (!at91_extern_irq)
-		return -ENOMEM;
-
-	if (at91_aic_pm_init()) {
-		kfree(at91_extern_irq);
-		return -ENOMEM;
-	}
-
-	at91_aic_irq_priorities = kzalloc(n_irqs
-					  * sizeof(*at91_aic_irq_priorities),
-					  GFP_KERNEL);
-	if (!at91_aic_irq_priorities)
-		return -ENOMEM;
-
-	at91_aic_base = of_iomap(node, 0);
-	at91_aic_np = node;
-
-	at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
-						&at91_aic_irq_ops, NULL);
-	if (!at91_aic_domain)
-		panic("Unable to add AIC irq domain (DT)\n");
-
-	of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
-		if (val >= n_irqs)
-			pr_warn("AIC: external irq %d >= %d skip it\n",
-				val, n_irqs);
-		else
-			set_bit(val, at91_extern_irq);
-	}
-
-	irq_set_default_host(at91_aic_domain);
-
-	return 0;
-}
-
-int __init at91_aic_of_init(struct device_node *node,
-				     struct device_node *parent)
-{
-	int err;
-
-	err = at91_aic_of_common_init(node, parent);
-	if (err)
-		return err;
-
-	at91_aic_hw_init(n_irqs);
-
-	return 0;
-}
-
-int __init at91_aic5_of_init(struct device_node *node,
-				     struct device_node *parent)
-{
-	int err;
-
-	at91_aic_caps |= AT91_AIC_CAP_AIC5;
-	n_irqs = NR_AIC5_IRQS;
-	at91_aic_chip.irq_ack           = at91_aic5_mask_irq;
-	at91_aic_chip.irq_mask		= at91_aic5_mask_irq;
-	at91_aic_chip.irq_unmask	= at91_aic5_unmask_irq;
-	at91_aic_chip.irq_eoi		= at91_aic5_eoi;
-	at91_aic_irq_ops.map		= at91_aic5_irq_map;
-
-	err = at91_aic_of_common_init(node, parent);
-	if (err)
-		return err;
-
-	at91_aic5_hw_init(n_irqs);
-
-	return 0;
-}
-#endif
-
 /*
  * Initialize the AIC interrupt controller.
  */
-- 
1.8.3.2

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Re: [PATCH v3 0/7] ARM: at91: move aic driver to drivers/irqchips

[Nicolas Ferre]

On 20/06/2014 17:01, Boris BREZILLON :
> Hello,
> 
> This series moves the AIC driver to the irqchip directory and make use of
> the generic chip framework whenever possible.
> 
> This driver only support DT boards (all legacy board files should be soon
> replaced by their DT versions).
> 
> Best Regards,

I repeat here for clarity:

Boris,
Once the AIC and AIC5 drivers are split, you can add my:

Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

And send the whole series to Jason.

Jason,
like you said in your response to patch #3/7, we can share a topic
branch so that both arm-soc and yourself have this material in our trees
and can go forward with other patch series on top of this one...

Thanks for your work and review. Bye,


> Changes since v2:
>  - remove irq line muxing definition
>  - rework Kconfig options
> 
> Changes since v1:
>  - rework the irq-mux bindings
> 
> Boris BREZILLON (7):
>   genirq: generic chip: export irq_map_generic_chip function
>   irqchip: atmel-aic: move binding doc to interrupt-controller directory
>   irqchip: atmel-aic: add new atmel AIC driver
>   ARM: at91: introduce OLD_IRQ_AT91 Kconfig option
>   ARM: at91: enclose at91_aic_xx calls in
>     IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks
>   ARM: at91: make use of the new AIC driver for dt enabled boards
>   ARM: at91: remove old irq material
> 
>  .../devicetree/bindings/arm/atmel-aic.txt          |  42 --
>  .../bindings/interrupt-controller/atmel,aic.txt    |  42 ++
>  arch/arm/mach-at91/Kconfig                         |  17 +-
>  arch/arm/mach-at91/Kconfig.non_dt                  |   6 +
>  arch/arm/mach-at91/Makefile                        |   3 +-
>  arch/arm/mach-at91/board-dt-rm9200.c               |  13 -
>  arch/arm/mach-at91/board-dt-sam9.c                 |  13 -
>  arch/arm/mach-at91/board-dt-sama5.c                |  13 -
>  arch/arm/mach-at91/irq.c                           | 270 +-------
>  arch/arm/mach-at91/pm.c                            |  32 +-
>  arch/arm/mach-at91/setup.c                         |   3 +-
>  drivers/irqchip/Kconfig                            |   7 +
>  drivers/irqchip/Makefile                           |   1 +
>  drivers/irqchip/irq-atmel-aic.c                    | 700 +++++++++++++++++++++
>  include/linux/irq.h                                |   2 +
>  kernel/irq/generic-chip.c                          |   5 +-
>  16 files changed, 800 insertions(+), 369 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/atmel-aic.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
>  create mode 100644 drivers/irqchip/irq-atmel-aic.c
> 


-- 
Nicolas Ferre
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