From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tuomas Tynkkynen Subject: Re: [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124 Date: Fri, 11 Jul 2014 18:11:41 +0300 Message-ID: <53BFFEAD.7000405@nvidia.com> References: <1405028569-14253-1-git-send-email-ttynkkynen@nvidia.com> <1405028569-14253-13-git-send-email-ttynkkynen@nvidia.com> <20140711091207.GY23218@tbergstrom-lnx.Nvidia.com> <20140711145735.GB6523@ulmo> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20140711145735.GB6523@ulmo> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding , Peter De Schrijver Cc: Viresh Kumar , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Linux Kernel Mailing List , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Stephen Warren , Prashant Gaikwad , Mike Turquette , "Rafael J. Wysocki" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org On 11/07/14 17:57, Thierry Reding wrote: >> I don't think that's going to work? The voltage scaling is handled in hw. > > Do we have to handle it in hardware or can we opt to do it in software, > too? > With the PLLX, voltage scaling is done entirely in SW. With the DFLL, it's possible to stay in open-loop mode and do it in SW, but there's not much point in that. -- nvpublic