From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tuomas Tynkkynen Subject: Re: [PATCH 01/13] clk: tegra: Add binding for the Tegra124 DFLL clocksource Date: Fri, 11 Jul 2014 20:21:27 +0300 Message-ID: <53C01D17.2050906@nvidia.com> References: <1405028569-14253-1-git-send-email-ttynkkynen@nvidia.com> <1405028569-14253-2-git-send-email-ttynkkynen@nvidia.com> <53C01558.3090607@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Andrew Bresticker Cc: "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Prashant Gaikwad , Mike Turquette , Stephen Warren , Viresh Kumar , Peter De Schrijver , "Rafael J. Wysocki" , Thierry Reding List-Id: devicetree@vger.kernel.org On 11/07/14 20:08, Andrew Bresticker wrote: > On Fri, Jul 11, 2014 at 9:48 AM, Tuomas Tynkkynen wrote: >> >> >> On 11/07/14 19:28, Andrew Bresticker wrote: >>> >>> On Thu, Jul 10, 2014 at 2:42 PM, Tuomas Tynkkynen >>> wrote: >>>> >>>> The DFLL is the main clocksource for the fast CPU cluster on Tegra124 >>>> and also provides automatic CPU rail voltage scaling as well. The DFLL >>>> is a separate IP block from the usual Tegra124 clock-and-reset >>>> controller, so it gets its own node in the device tree. >>> >>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt >>>> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt >>> >>> >>>> +- nvidia,pmic-voltage-table: Array of 2-tuples. Each entry should have >>>> the >>>> + form , indicating the register value >>>> that >>>> + needs to be programmed to the PMIC for changing the VDD_CPU voltage to >>>> + the specified voltage. The table must be in ascending order by the >>>> voltage. >>> >>> >>> Instead of listing the register values for each voltage in the DT, >>> can't you use regulator_list_voltage() to create this map? >>> >> >> I don't see a way to get the register values that way, unless we assume that >> the mapping is linear and doesn't have holes. > > Hmm... I guess if you don't assume it's linear and continuous you'd > have to iterate over all 256 selectors. > I don't think we can assume that each selector maps to a concrete register value, though I'm not sure. include/linux/regulator/driver.h documents for @list_voltage "Selectors range from zero to one less regulator_desc.n_voltages." but maybe the consumer API could take different values. -- nvpublic