From mboxrd@z Thu Jan 1 00:00:00 1970 From: caesar Subject: Re: [PATCH v4 2/2] pwm: rockchip: Added to support for RK3288 SoC Date: Thu, 07 Aug 2014 11:37:21 +0800 Message-ID: <53E2F471.6020701@rock-chips.com> References: <1406197295-10604-1-git-send-email-caesar.wang@rock-chips.com> <1406197295-10604-3-git-send-email-caesar.wang@rock-chips.com> <53E2D605.2000704@rock-chips.com> <53E2F11A.1040109@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: Sender: linux-pwm-owner@vger.kernel.org To: Doug Anderson Cc: Thierry Reding , =?UTF-8?B?SGVpa28gU3TDvGJu?= =?UTF-8?B?ZXI=?= , Beniamino Galvani , Rob Herring , Ian Campbell , Randy Dunlap , Kumar Gala , Eddie Cai , Tao Huang , Jianqun Xu , Addy Ke , =?UTF-8?B?6ZmI5riQ6aOe?= , han jiang , "linux-arm-kernel@lists.infradead.org" , linux-pwm , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" List-Id: devicetree@vger.kernel.org Doug, =E5=9C=A8 2014=E5=B9=B408=E6=9C=8807=E6=97=A5 11:26, Doug Anderson =E5=86= =99=E9=81=93: > caesar, > > On Wed, Aug 6, 2014 at 8:23 PM, caesar w= rote: >> =E5=9C=A8 2014=E5=B9=B408=E6=9C=8807=E6=97=A5 10:16, Doug Anderson =E5= =86=99=E9=81=93: >> >>> Caesar, >>> >>> On Wed, Aug 6, 2014 at 6:27 PM, caesar = wrote: >>>> Doug, >>>> >>>> =E5=9C=A8 2014=E5=B9=B408=E6=9C=8807=E6=97=A5 06:46, Doug Anderson= =E5=86=99=E9=81=93: >>>> >>>>> Caesar, >>>>> >>>>> On Thu, Jul 24, 2014 at 3:21 AM, Caesar Wang >>>>> >>>>> wrote: >>>>>> +static const struct rockchip_pwm_data pwm_data_v1 =3D { >>>>>> + .regs.duty =3D PWM_HRC, >>>>>> + .regs.period =3D PWM_LRC, >>>>>> + .regs.cntr =3D PWM_CNTR, >>>>>> + .regs.ctrl =3D PWM_CTRL, >>>>>> + .prescaler =3D PRESCALER, >>>>>> + .set_enable =3D rockchip_pwm_set_enable_v1, >>>>>> +}; >>>>>> + >>>>>> +static const struct rockchip_pwm_data pwm_data_v2 =3D { >>>>>> + .regs.duty =3D PWM_LRC, >>>>>> + .regs.period =3D PWM_HRC, >>>>>> + .regs.cntr =3D PWM_CNTR, >>>>>> + .regs.ctrl =3D PWM_CTRL, >>>>>> + .prescaler =3D PRESCALER-1, >>>>>> + .set_enable =3D rockchip_pwm_set_enable_v2, >>>>>> +}; >>>>>> + >>>>>> +static const struct rockchip_pwm_data pwm_data_vop =3D { >>>>>> + .regs.duty =3D PWM_LRC, >>>>>> + .regs.period =3D PWM_HRC, >>>>>> + .regs.cntr =3D PWM_CTRL, >>>>>> + .regs.ctrl =3D PWM_CNTR, >>>>> Did you really mean to flip CTRL and CNTR here? If so, that's su= per >>>>> confusing and deserves a comment. AKA, I think the above should = not >>>>> be: >>>>> >>>>> + .regs.cntr =3D PWM_CTRL, >>>>> + .regs.ctrl =3D PWM_CNTR, >>>>> >>>>> ...but should be >>>>> >>>>> + .regs.cntr =3D PWM_CNTR, >>>>> + .regs.ctrl =3D PWM_CTRL, >>>>> >>>>> If you didn't mean to flip CTRL and CNTR here, then just get rid = of >>>>> pwm_data_vop and refer to pwm_data_v2. In fact, I'd suggest that= you >>>>> totally remove the "rockchip,vop-pwm" since there's nothing diffe= rent >>>>> between "rockchip,rk3288-pwm" and "rockchip,vop-pwm". >>>> >>>> Sorry,I think it's no problem. the "rockchip,rk3288-pwm" and >>>> "rockchip,vop-pwm" are seperate PWM controllers. >>>> They are just different registers address between CNTR and CTRL . >>> OK, I looked up in the TRM. Right, the CNTR and CTRL are flipped o= n >>> the vop. So I think that the only change you need is to add: >>> >>> #define PWM_VOP_CTRL 0x00 >>> #define PWM_VOP_CNTR 0x0c >>> >>> ...then use these new #defines for the vop structure. >>> >>> >>> As you have the code written right now it's very confusing. The ne= w >>> #defines will fix this. >>> >> yeah, I think they can be used in the same context. >> >> I will fix it in patch v5 if it is really need. > I think you should fix this, but if Thierry doesn't think so then it'= s > really his decision. I remember In patch v2 [1],Thierry suggests me to fix it so if I have n= o=20 to get wrong. [1]: https://lkml.org/lkml/2014/7/21/113 > >