Re: [PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

[Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>]

On 8/14/14, 1:54 PM, Pavel Machek wrote:
> On Thu 2014-08-14 10:51:31, dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>> From: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>
>> The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to
>> bring secondary cores online. This patch adds a /memreserve/ section to
>> reserve the first 4K for the SMP trampoline code.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>> ---
>>  arch/arm/boot/dts/socfpga_arria5.dtsi   | 1 +
>>  arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 +
>>  2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
>> index 468fc4c..73b939e 100644
>> --- a/arch/arm/boot/dts/socfpga_arria5.dtsi
>> +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
>> @@ -15,6 +15,7 @@
>>   */
>>  
>>  /dts-v1/;
>> +/memreserve/ 0x00000000 0x0001000;
> 
> Actually, comment here explaining that ROM code uses 0x0 for the
> trampoline would be nice here... if I understand it correctly.

Sure...I'll add a single line comment.

Dinh
> 
> Thanks,
> 									Pavel
> 
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