From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
martin.petersen@oracle.com, jejb@linux.ibm.com,
andersson@kernel.org, vkoul@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org,
quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org
Subject: Re: [PATCH 03/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode
Date: Sun, 30 Oct 2022 00:54:38 +0300 [thread overview]
Message-ID: <53bc627f-0c3b-3417-d8af-6ced80eecc97@linaro.org> (raw)
In-Reply-To: <20221029141633.295650-4-manivannan.sadhasivam@linaro.org>
On 29/10/2022 17:16, Manivannan Sadhasivam wrote:
> Add separate tables_hs_g4 instance to allow the PHY driver to configure the
> PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and
> PCS register setting in tables_hs_g4 and the UFS driver can request the
> Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
(Especially if changed to qmp_ufs_init_registers()).
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 4c6a2b5afc9a..5f2a012707b7 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -553,6 +553,8 @@ struct qmp_phy_cfg {
> const struct qmp_phy_cfg_tables tables;
> /* Additional sequence for HS Series B */
> const struct qmp_phy_cfg_tables tables_hs_b;
> + /* Additional sequence for HS G4 */
> + const struct qmp_phy_cfg_tables tables_hs_g4;
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -587,6 +589,7 @@ struct qmp_phy_cfg {
> * @pcs_misc: iomapped memory space for lane's pcs_misc
> * @qmp: QMP phy to which this lane belongs
> * @mode: PHY mode configured by the UFS driver
> + * @submode: PHY submode configured by the UFS driver
> */
> struct qmp_phy {
> struct phy *phy;
> @@ -600,6 +603,7 @@ struct qmp_phy {
> void __iomem *pcs_misc;
> struct qcom_qmp *qmp;
> u32 mode;
> + u32 submode;
> };
>
> /**
> @@ -993,8 +997,12 @@ static int qmp_ufs_power_on(struct phy *phy)
> qmp_ufs_serdes_init(qphy, &cfg->tables_hs_b);
>
> qmp_ufs_lanes_init(qphy, &cfg->tables);
> + if (qphy->submode == UFS_HS_G4)
> + qmp_ufs_lanes_init(qphy, &cfg->tables_hs_g4);
>
> qmp_ufs_pcs_init(qphy, &cfg->tables);
> + if (qphy->submode == UFS_HS_G4)
> + qmp_ufs_pcs_init(qphy, &cfg->tables_hs_g4);
>
> ret = reset_control_deassert(qmp->ufs_reset);
> if (ret)
> @@ -1083,6 +1091,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> struct qmp_phy *qphy = phy_get_drvdata(phy);
>
> qphy->mode = mode;
> + qphy->submode = submode;
>
> return 0;
> }
--
With best wishes
Dmitry
next prev parent reply other threads:[~2022-10-29 21:54 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-29 14:16 [PATCH 00/15] ufs: qcom: Add HS-G4 support Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 01/15] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tables struct Manivannan Sadhasivam
2022-10-29 21:50 ` Dmitry Baryshkov
2022-10-31 15:46 ` Manivannan Sadhasivam
2022-10-31 18:50 ` Dmitry Baryshkov
2022-11-01 14:41 ` Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 02/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Manivannan Sadhasivam
2022-10-29 21:51 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 03/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Manivannan Sadhasivam
2022-10-29 21:54 ` Dmitry Baryshkov [this message]
2022-10-29 14:16 ` [PATCH 04/15] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Manivannan Sadhasivam
2022-10-29 21:55 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 05/15] phy: qcom-qmp-ufs: Move HS Rate B register setting to tables_hs_b Manivannan Sadhasivam
2022-10-29 21:55 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 06/15] dt-bindings: ufs: Add "max-gear" property for UFS device Manivannan Sadhasivam
2022-10-31 21:35 ` Rob Herring
2022-10-29 14:16 ` [PATCH 07/15] arm64: dts: qcom: qrb5165-rb5: Add max-gear property to UFS node Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 08/15] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Manivannan Sadhasivam
2022-10-29 21:56 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 09/15] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 10/15] scsi: ufs: ufs-qcom: Use bitfields where appropriate Manivannan Sadhasivam
2022-10-29 21:58 ` Dmitry Baryshkov
2022-10-31 14:50 ` Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 11/15] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Manivannan Sadhasivam
2022-10-29 21:33 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 12/15] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Manivannan Sadhasivam
2022-10-29 22:06 ` Dmitry Baryshkov
2022-10-31 14:50 ` Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 13/15] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 14/15] scsi: ufs: ufs-qcom: Add support for finding HS gear on new UFS versions Manivannan Sadhasivam
2022-10-29 21:48 ` Dmitry Baryshkov
2022-10-31 14:56 ` Manivannan Sadhasivam
2022-10-31 18:52 ` Dmitry Baryshkov
2022-11-02 20:05 ` Krzysztof Kozlowski
2022-11-03 12:18 ` Manivannan Sadhasivam
2022-10-31 15:39 ` Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 15/15] MAINTAINERS: Add myself as the maintainer for Qcom UFS driver Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=53bc627f-0c3b-3417-d8af-6ced80eecc97@linaro.org \
--to=dmitry.baryshkov@linaro.org \
--cc=andersson@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jejb@linux.ibm.com \
--cc=konrad.dybcio@somainline.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=linux-scsi@vger.kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=martin.petersen@oracle.com \
--cc=quic_cang@quicinc.com \
--cc=robh+dt@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).