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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3341be36bdesm4757664a91.24.2025.09.25.00.39.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Sep 2025 00:39:49 -0700 (PDT) Message-ID: <53d63dd6-a022-4e80-a317-3218976a7474@oss.qualcomm.com> Date: Thu, 25 Sep 2025 15:39:43 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC To: =?UTF-8?Q?Krzysztof_Koz=C5=82owski?= , Jingyi Wang Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Ronak Raheja References: <20250924-knp-dts-v1-0-3fdbc4b9e1b1@oss.qualcomm.com> <20250924-knp-dts-v1-6-3fdbc4b9e1b1@oss.qualcomm.com> Content-Language: en-US From: "Aiqun(Maria) Yu" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: RfCGqfEfl0rAaGIBUEwzfsLwN3K6wf-l X-Authority-Analysis: v=2.4 cv=RO2zH5i+ c=1 sm=1 tr=0 ts=68d4f1c8 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=_8C6HiND3MtPFSYwXacA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAyNSBTYWx0ZWRfX5HMk5hIGfhKl No4UaBkCgYHiyNPWSVmYGkMe7kdClLJuXm1xpZ5eurzHB89gN/Fci9jwqhvFTB2MoSSbWudYgK7 NBg/DsEe76OJplEsonb/3EHLJ0Oox2HuhLdkSSng+tq83IHXsRNJOOWSjTeJjxZuYGViWbXCin2 C4SfXuCPuOvS2XOl3rA0em0suo4sWlRxnXI97x8Qi5tVIEt1CHhRKeokUuovol7yxIOR3iN6Ijh X8HGchJIzSj5V+Y96ySUbOsrVpA7Lw+QyRC2X/1IgcSxj/dqN2VGxMVxlVPFi5bUoS3z/CGNB/t PE4kz5/Syc9Vihrz6zikcik8ad/nrbQJimayK+vrBIxZpiHOFseX7jdOe0Wgw+FL32ktJ89U4vs mlhTKxLM X-Proofpoint-ORIG-GUID: RfCGqfEfl0rAaGIBUEwzfsLwN3K6wf-l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-24_07,2025-09-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200025 On 9/25/2025 9:50 AM, Krzysztof Kozłowski wrote: > On Thu, 25 Sept 2025 at 09:17, Jingyi Wang wrote: >> >> From: Ronak Raheja >> >> Add the base USB devicetree definitions for Kaanapali platform. The overall >> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY >> (rev. v8) and M31 eUSB2 PHY. >> >> Signed-off-by: Ronak Raheja >> Signed-off-by: Jingyi Wang >> --- >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++ >> 1 file changed, 155 insertions(+) >> > > > Second try, without HTML: > > I really don't understand why you created such huge patchset. Year > ago, two years ago, we were discussing it already and explained that's > just inflating the patchset without reason. > > New Soc is one logical change. Maybe two. Not 18! It was previously squashed into the base soc dtsi patch and mark like: Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto), Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and Jinlong Mao(added coresight). While it is over 4000+ lines when we squash it together. Also as offline reviewed with Bjorn, he suggested us to split out the USB and other parts. > > Not one patch per node or feature. > > This hides big picture, makes difficult to review everything, > difficult to test. Your patch count for LWN stats doesn't matter to > us. With the current splitting, the different author as each co-developer can get the meaningful LWN stats.> > NAK and I'm really disappointed I have to repeat the same review . Currently, there are 10 SoC DTSI patches sent, structured as follows: SoC initial Base MTP board SoC PCIe0 SoC SDC2 SoC USB SoC remoteproc SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight SoC additional features SoC audio SoC CAMSS SoC video Which parts would you prefer to squash into pls? -- Thx and BRs, Aiqun(Maria) Yu