* [PATCH V2 1/4] dt-bindings: clock: Add crypto clock and reset definitions
2023-05-15 15:07 [PATCH V2 0/4] Enable crypto for ipq9574 Anusha Rao
@ 2023-05-15 15:07 ` Anusha Rao
2023-05-15 16:14 ` Krzysztof Kozlowski
2023-05-16 7:45 ` Bhupesh Sharma
2023-05-15 15:07 ` [PATCH V2 2/4] clk: qcom: gcc-ipq9574: Enable crypto clocks Anusha Rao
` (2 subsequent siblings)
3 siblings, 2 replies; 9+ messages in thread
From: Anusha Rao @ 2023-05-15 15:07 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, thara.gopinath, herbert, davem,
robh+dt, krzysztof.kozlowski+dt, conor+dt, mturquette, sboyd,
p.zabel, bhupesh.sharma, linux-arm-msm, linux-crypto, devicetree,
linux-kernel, linux-clk
Cc: quic_srichara, quic_gokulsri, quic_sjaganat, quic_kathirav,
quic_arajkuma, quic_poovendh
Add crypto clock and reset ID definitions for ipq9574.
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
---
Changes in V2:
- Separated out the clock/reset binding changes to a new patch.
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++
include/dt-bindings/reset/qcom,ipq9574-gcc.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 5a2961bfe893..86790efa10f0 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -210,4 +210,8 @@
#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
+#define CRYPTO_CLK_SRC 204
+#define GCC_CRYPTO_CLK 205
+#define GCC_CRYPTO_AXI_CLK 206
+#define GCC_CRYPTO_AHB_CLK 207
#endif
diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
index d01dc6a24cf1..c709d103673d 100644
--- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
@@ -160,5 +160,6 @@
#define GCC_WCSS_Q6_BCR 151
#define GCC_WCSS_Q6_TBU_BCR 152
#define GCC_TCSR_BCR 153
+#define GCC_CRYPTO_BCR 154
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH V2 1/4] dt-bindings: clock: Add crypto clock and reset definitions
2023-05-15 15:07 ` [PATCH V2 1/4] dt-bindings: clock: Add crypto clock and reset definitions Anusha Rao
@ 2023-05-15 16:14 ` Krzysztof Kozlowski
2023-05-16 7:45 ` Bhupesh Sharma
1 sibling, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-15 16:14 UTC (permalink / raw)
To: Anusha Rao, agross, andersson, konrad.dybcio, thara.gopinath,
herbert, davem, robh+dt, krzysztof.kozlowski+dt, conor+dt,
mturquette, sboyd, p.zabel, bhupesh.sharma, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, linux-clk
Cc: quic_srichara, quic_gokulsri, quic_sjaganat, quic_kathirav,
quic_arajkuma, quic_poovendh
On 15/05/2023 17:07, Anusha Rao wrote:
> Add crypto clock and reset ID definitions for ipq9574.
>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH V2 1/4] dt-bindings: clock: Add crypto clock and reset definitions
2023-05-15 15:07 ` [PATCH V2 1/4] dt-bindings: clock: Add crypto clock and reset definitions Anusha Rao
2023-05-15 16:14 ` Krzysztof Kozlowski
@ 2023-05-16 7:45 ` Bhupesh Sharma
2023-05-16 8:05 ` Anusha Canchi
1 sibling, 1 reply; 9+ messages in thread
From: Bhupesh Sharma @ 2023-05-16 7:45 UTC (permalink / raw)
To: Anusha Rao, agross, andersson, konrad.dybcio, thara.gopinath,
herbert, davem, robh+dt, krzysztof.kozlowski+dt, conor+dt,
mturquette, sboyd, p.zabel, linux-arm-msm, linux-crypto,
devicetree, linux-kernel, linux-clk
Cc: quic_srichara, quic_gokulsri, quic_sjaganat, quic_kathirav,
quic_arajkuma, quic_poovendh
On 5/15/23 8:37 PM, Anusha Rao wrote:
> Add crypto clock and reset ID definitions for ipq9574.
>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> ---
> Changes in V2:
> - Separated out the clock/reset binding changes to a new patch.
>
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++
> include/dt-bindings/reset/qcom,ipq9574-gcc.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> index 5a2961bfe893..86790efa10f0 100644
> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> @@ -210,4 +210,8 @@
> #define GCC_SNOC_PCIE1_1LANE_S_CLK 201
> #define GCC_SNOC_PCIE2_2LANE_S_CLK 202
> #define GCC_SNOC_PCIE3_2LANE_S_CLK 203
> +#define CRYPTO_CLK_SRC 204
For uniformity, please use GCC_ prefix int the above define as well.
Also make the similar changes at the places where this CLOCK_SRC macro
is used.
Thanks,
Bhupesh
> +#define GCC_CRYPTO_CLK 205
> +#define GCC_CRYPTO_AXI_CLK 206
> +#define GCC_CRYPTO_AHB_CLK 207
> #endif
> diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
> index d01dc6a24cf1..c709d103673d 100644
> --- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
> @@ -160,5 +160,6 @@
> #define GCC_WCSS_Q6_BCR 151
> #define GCC_WCSS_Q6_TBU_BCR 152
> #define GCC_TCSR_BCR 153
> +#define GCC_CRYPTO_BCR 154
>
> #endif
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH V2 1/4] dt-bindings: clock: Add crypto clock and reset definitions
2023-05-16 7:45 ` Bhupesh Sharma
@ 2023-05-16 8:05 ` Anusha Canchi
0 siblings, 0 replies; 9+ messages in thread
From: Anusha Canchi @ 2023-05-16 8:05 UTC (permalink / raw)
To: Bhupesh Sharma, agross, andersson, konrad.dybcio, thara.gopinath,
herbert, davem, robh+dt, krzysztof.kozlowski+dt, conor+dt,
mturquette, sboyd, p.zabel, linux-arm-msm, linux-crypto,
devicetree, linux-kernel, linux-clk
Cc: quic_srichara, quic_gokulsri, quic_sjaganat, quic_kathirav,
quic_arajkuma, quic_poovendh
On 5/16/2023 1:15 PM, Bhupesh Sharma wrote:
>
> On 5/15/23 8:37 PM, Anusha Rao wrote:
>> Add crypto clock and reset ID definitions for ipq9574.
>>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> ---
>> Changes in V2:
>> - Separated out the clock/reset binding changes to a new patch.
>>
>> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++
>> include/dt-bindings/reset/qcom,ipq9574-gcc.h | 1 +
>> 2 files changed, 5 insertions(+)
>>
>> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> index 5a2961bfe893..86790efa10f0 100644
>> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> @@ -210,4 +210,8 @@
>> #define GCC_SNOC_PCIE1_1LANE_S_CLK 201
>> #define GCC_SNOC_PCIE2_2LANE_S_CLK 202
>> #define GCC_SNOC_PCIE3_2LANE_S_CLK 203
>> +#define CRYPTO_CLK_SRC 204
>
> For uniformity, please use GCC_ prefix int the above define as well.
> Also make the similar changes at the places where this CLOCK_SRC macro
> is used.
Sure, will update in the next spin.
Thanks,
Anusha
>
> Thanks,
> Bhupesh
>
>> +#define GCC_CRYPTO_CLK 205
>> +#define GCC_CRYPTO_AXI_CLK 206
>> +#define GCC_CRYPTO_AHB_CLK 207
>> #endif
>> diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h
>> b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
>> index d01dc6a24cf1..c709d103673d 100644
>> --- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h
>> +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
>> @@ -160,5 +160,6 @@
>> #define GCC_WCSS_Q6_BCR 151
>> #define GCC_WCSS_Q6_TBU_BCR 152
>> #define GCC_TCSR_BCR 153
>> +#define GCC_CRYPTO_BCR 154
>> #endif
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V2 2/4] clk: qcom: gcc-ipq9574: Enable crypto clocks
2023-05-15 15:07 [PATCH V2 0/4] Enable crypto for ipq9574 Anusha Rao
2023-05-15 15:07 ` [PATCH V2 1/4] dt-bindings: clock: Add crypto clock and reset definitions Anusha Rao
@ 2023-05-15 15:07 ` Anusha Rao
2023-05-15 15:07 ` [PATCH V2 3/4] dt-bindings: qcom-qce: add SoC compatible string for ipq9574 Anusha Rao
2023-05-15 15:07 ` [PATCH V2 4/4] arm64: dts: qcom: ipq9574: Enable crypto nodes Anusha Rao
3 siblings, 0 replies; 9+ messages in thread
From: Anusha Rao @ 2023-05-15 15:07 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, thara.gopinath, herbert, davem,
robh+dt, krzysztof.kozlowski+dt, conor+dt, mturquette, sboyd,
p.zabel, bhupesh.sharma, linux-arm-msm, linux-crypto, devicetree,
linux-kernel, linux-clk
Cc: quic_srichara, quic_gokulsri, quic_sjaganat, quic_kathirav,
quic_arajkuma, quic_poovendh
Enable the clocks required for crypto operation.
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
---
Changes in V2:
- Moved the clock/reset binding changes to a new patch.
drivers/clk/qcom/gcc-ipq9574.c | 72 ++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 7b0505f5c255..b203e7aae145 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
},
};
+static const struct freq_tbl ftbl_crypto_clk_src[] = {
+ F(160000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 crypto_clk_src = {
+ .cmd_rcgr = 0x16004,
+ .freq_tbl = ftbl_crypto_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "crypto_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_crypto_clk = {
+ .halt_reg = 0x1600c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(14),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_crypto_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &crypto_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x24018,
.halt_check = BRANCH_HALT_VOTED,
@@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
},
};
+static struct clk_branch gcc_crypto_axi_clk = {
+ .halt_reg = 0x16010,
+ .clkr = {
+ .enable_reg = 0x16010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_crypto_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_bfdcd_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_ahb_clk = {
+ .halt_reg = 0x16014,
+ .clkr = {
+ .enable_reg = 0x16014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_crypto_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_bfdcd_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_nsscfg_clk = {
.halt_reg = 0x1702c,
.clkr = {
@@ -4036,6 +4103,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
+ [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
+ [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+ [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+ [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq9574_resets[] = {
@@ -4193,6 +4264,7 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
+ [GCC_CRYPTO_BCR] = { 0x16000, 0 },
};
static const struct of_device_id gcc_ipq9574_match_table[] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH V2 3/4] dt-bindings: qcom-qce: add SoC compatible string for ipq9574
2023-05-15 15:07 [PATCH V2 0/4] Enable crypto for ipq9574 Anusha Rao
2023-05-15 15:07 ` [PATCH V2 1/4] dt-bindings: clock: Add crypto clock and reset definitions Anusha Rao
2023-05-15 15:07 ` [PATCH V2 2/4] clk: qcom: gcc-ipq9574: Enable crypto clocks Anusha Rao
@ 2023-05-15 15:07 ` Anusha Rao
2023-05-15 17:36 ` Conor Dooley
2023-05-15 15:07 ` [PATCH V2 4/4] arm64: dts: qcom: ipq9574: Enable crypto nodes Anusha Rao
3 siblings, 1 reply; 9+ messages in thread
From: Anusha Rao @ 2023-05-15 15:07 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, thara.gopinath, herbert, davem,
robh+dt, krzysztof.kozlowski+dt, conor+dt, mturquette, sboyd,
p.zabel, bhupesh.sharma, linux-arm-msm, linux-crypto, devicetree,
linux-kernel, linux-clk
Cc: quic_srichara, quic_gokulsri, quic_sjaganat, quic_kathirav,
quic_arajkuma, quic_poovendh
Document the compatible string for ipq9574.
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
---
Changes in V2:
- Added a new compatible for ipq9574 SoC.
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index e375bd981300..0d1deae06e2d 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -28,6 +28,7 @@ properties:
- enum:
- qcom,ipq6018-qce
- qcom,ipq8074-qce
+ - qcom,ipq9574-qce
- qcom,msm8996-qce
- qcom,sdm845-qce
- const: qcom,ipq4019-qce
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH V2 3/4] dt-bindings: qcom-qce: add SoC compatible string for ipq9574
2023-05-15 15:07 ` [PATCH V2 3/4] dt-bindings: qcom-qce: add SoC compatible string for ipq9574 Anusha Rao
@ 2023-05-15 17:36 ` Conor Dooley
0 siblings, 0 replies; 9+ messages in thread
From: Conor Dooley @ 2023-05-15 17:36 UTC (permalink / raw)
To: Anusha Rao
Cc: agross, andersson, konrad.dybcio, thara.gopinath, herbert, davem,
robh+dt, krzysztof.kozlowski+dt, conor+dt, mturquette, sboyd,
p.zabel, bhupesh.sharma, linux-arm-msm, linux-crypto, devicetree,
linux-kernel, linux-clk, quic_srichara, quic_gokulsri,
quic_sjaganat, quic_kathirav, quic_arajkuma, quic_poovendh
[-- Attachment #1: Type: text/plain, Size: 1022 bytes --]
On Mon, May 15, 2023 at 08:37:21PM +0530, Anusha Rao wrote:
> Document the compatible string for ipq9574.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> ---
> Changes in V2:
> - Added a new compatible for ipq9574 SoC.
>
> Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> index e375bd981300..0d1deae06e2d 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -28,6 +28,7 @@ properties:
> - enum:
> - qcom,ipq6018-qce
> - qcom,ipq8074-qce
> + - qcom,ipq9574-qce
> - qcom,msm8996-qce
> - qcom,sdm845-qce
> - const: qcom,ipq4019-qce
> --
> 2.17.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V2 4/4] arm64: dts: qcom: ipq9574: Enable crypto nodes
2023-05-15 15:07 [PATCH V2 0/4] Enable crypto for ipq9574 Anusha Rao
` (2 preceding siblings ...)
2023-05-15 15:07 ` [PATCH V2 3/4] dt-bindings: qcom-qce: add SoC compatible string for ipq9574 Anusha Rao
@ 2023-05-15 15:07 ` Anusha Rao
3 siblings, 0 replies; 9+ messages in thread
From: Anusha Rao @ 2023-05-15 15:07 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, thara.gopinath, herbert, davem,
robh+dt, krzysztof.kozlowski+dt, conor+dt, mturquette, sboyd,
p.zabel, bhupesh.sharma, linux-arm-msm, linux-crypto, devicetree,
linux-kernel, linux-clk
Cc: quic_srichara, quic_gokulsri, quic_sjaganat, quic_kathirav,
quic_arajkuma, quic_poovendh
Enable crypto support for ipq9574.
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
---
Changes in V2:
- Removed the deprecated compatible 'qcom,crypto-v5.1' and
added SoC specific compatible string.
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index fea15f3cf910..6e52d35a6a15 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -123,6 +123,26 @@
clock-names = "core";
};
+ cryptobam: dma-controller@704000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x00704000 0x20000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <1>;
+ qcom,controlled-remotely;
+ };
+
+ crypto: crypto@73a000 {
+ compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
+ reg = <0x0073a000 0x6000>;
+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc GCC_CRYPTO_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 2>, <&cryptobam 3>;
+ dma-names = "rx", "tx";
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq9574-tlmm";
reg = <0x01000000 0x300000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread