From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EBF1C43334 for ; Fri, 22 Jul 2022 09:04:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230409AbiGVJE0 (ORCPT ); Fri, 22 Jul 2022 05:04:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231621AbiGVJE0 (ORCPT ); Fri, 22 Jul 2022 05:04:26 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AD907E306 for ; Fri, 22 Jul 2022 02:04:24 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id t1so6627337lft.8 for ; Fri, 22 Jul 2022 02:04:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language :from:to:cc:references:in-reply-to:content-transfer-encoding; bh=l3h9J6UBwtKZvJITANmcz+24NubjgVssRtaWr316TZs=; b=mirn+CGqVXafmKCSE26H4UOWDduWcnDa1FtZoLehw1N8nxaLCn+AZTl0tCocMNRkMl 9jHl8872M72LJOGhgi+2bxsYa7R/Ow5nJPcX85G4FteaQlUCyyp/ScmU05UVqinn6Q0T DPCz6N/vqp2UqZKa1QcZceEQ9y+craPhLT4VabCGwNU3V6NhR56mkCL9Ub0PXOmgR6yr vVdx0n3HyGk+mBUXEBoA1zVALL0WUVm7pl7V0EafzwLIGdcJMe/hIGFmmcfTejYU+FKH pxJeMWG6nk1izMokmiYi6SAcWpOweO02it7CmwLhtJUXVl5dtlm49OajBLWycLIyFmER fUAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:from:to:cc:references:in-reply-to :content-transfer-encoding; bh=l3h9J6UBwtKZvJITANmcz+24NubjgVssRtaWr316TZs=; b=GD+xsZCQ4BKKwU/XHcdYDT9WEx3fhz+Sglprlei3lUvswWGNnrPERVOthGqKy+zesk oupUvgLXRU6ZUxQ12GT+5tjxhhYDNmACF82zb+mJg6wFqPR+/5mnDJXM+hHomDII8uCS nWBZYxZAA29FMXVknBMd6wmcUlCAlMkMWh7UyK0wOQNGaEBNyuzR/n581JDPSEBo60Qi z9Zf4beTx5m9ZKBhDWvPY52+vHI5TaoNxujW6UL0spP3UY4K72CQGM5pcMWnSvJGt/gE s21Hsai0HFjvwoUrKNPJ+2Wa++s48Lk4FCb3hRT8A03Pjg6YesuzZ6nEpJaRbbt3fBfi vjXA== X-Gm-Message-State: AJIora9a3WB2QTGrl55Ki+mX/wi26XH0JdoVYE6snws/duN6UyJMela2 PB6W5Th9WU2I1e3ksxdCZ5ajYQ== X-Google-Smtp-Source: AGRyM1uKGad0HYgW1xNRavLGPomXqqpMS6YPuafQWGsFlmZ49umoCJNqxnl9rMo/IIJozjp4rrkX5w== X-Received: by 2002:ac2:5084:0:b0:48a:6e29:bf8 with SMTP id f4-20020ac25084000000b0048a6e290bf8mr971373lfm.572.1658480662753; Fri, 22 Jul 2022 02:04:22 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id o18-20020ac24c52000000b0047f933622c8sm942056lfk.163.2022.07.22.02.04.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Jul 2022 02:04:22 -0700 (PDT) Message-ID: <53dfe37d-c976-0ffe-dd46-48b681144c6c@linaro.org> Date: Fri, 22 Jul 2022 12:04:20 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v17 0/6] PCI: dwc: Fix higher MSI vectors handling Content-Language: en-GB From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold References: <20220707134733.2436629-1-dmitry.baryshkov@linaro.org> <84004850-026a-980d-6c9c-3668182fc458@linaro.org> In-Reply-To: <84004850-026a-980d-6c9c-3668182fc458@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 14/07/2022 14:58, Dmitry Baryshkov wrote: > On 07/07/2022 16:47, Dmitry Baryshkov wrote: >> I have replied with my Tested-by to the patch at [2], which has landed >> in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: >> Add support for handling MSIs from 8 endpoints"). However lately I >> noticed that during the tests I still had 'pcie_pme=nomsi', so the >> device was not forced to use higher MSI vectors. >> >> After removing this option I noticed that hight MSI vectors are not >> delivered on tested platforms. After additional research I stumbled upon >> a patch in msm-4.14 ([1]), which describes that each group of MSI >> vectors is mapped to the separate interrupt. Implement corresponding >> mapping. > > [skipped] > > Gracious ping. Does this series stand a chance of getting into 5.20? Bjorn, please excuse my insistence. Given that it's not merged (yet), probably it will not make it into 5.20. Is there anything preventing it from being accepted for 5.21? dwc patches were reviewed by Rob, Mani and Johan. Stanimir has acked the bindings patch. The dts patch should probably go via the arm-soc tree (together with additional patches adding multiple MSI IRQs to other Qualcomm SoCs). > >> Dmitry Baryshkov (6): >>    PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() >>    PCI: dwc: Convert msi_irq to the array >>    PCI: dwc: split MSI IRQ parsing/allocation to a separate function >>    PCI: dwc: Handle MSIs routed to multiple GIC interrupts >>    dt-bindings: PCI: qcom: Support additional MSI interrupts >>    arm64: dts: qcom: sm8250: provide additional MSI interrupts >> >>   .../devicetree/bindings/pci/qcom,pcie.yaml    |  51 +++++- >>   arch/arm64/boot/dts/qcom/sm8250.dtsi          |  12 +- >>   drivers/pci/controller/dwc/pci-dra7xx.c       |   2 +- >>   drivers/pci/controller/dwc/pci-exynos.c       |   2 +- >>   .../pci/controller/dwc/pcie-designware-host.c | 164 +++++++++++++----- >>   drivers/pci/controller/dwc/pcie-designware.h  |   2 +- >>   drivers/pci/controller/dwc/pcie-keembay.c     |   2 +- >>   drivers/pci/controller/dwc/pcie-spear13xx.c   |   2 +- >>   drivers/pci/controller/dwc/pcie-tegra194.c    |   2 +- >>   9 files changed, 185 insertions(+), 54 deletions(-) >> > > -- With best wishes Dmitry