From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: Re: [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp Date: Mon, 8 Sep 2014 20:03:39 +0530 Message-ID: <540DBE43.50403@ti.com> References: <1409758637-28654-1-git-send-email-gabriel.fernandez@linaro.org> <1409758637-28654-2-git-send-email-gabriel.fernandez@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1409758637-28654-2-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Grant Likely Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, kernel-F5mvAk5X5gdBDgjK7y7TUQ@public.gmane.org, Gabriel Fernandez , alexandre torgue , Giuseppe Cavallaro List-Id: devicetree@vger.kernel.org Hi, On Wednesday 03 September 2014 09:07 PM, Gabriel FERNANDEZ wrote: > The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe > or USB3 devices. > > Signed-off-by: alexandre torgue > Signed-off-by: Giuseppe Cavallaro > Signed-off-by: Gabriel Fernandez > --- > .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ > 1 file changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > new file mode 100644 > index 0000000..5e307af > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > @@ -0,0 +1,126 @@ > +STMicroelectronics STi MIPHY28LP PHY binding > +============================================ > + > +This binding describes a miphy device that is used to control PHY hardware > +for SATA, PCIe or USB3. > + > +Required properties (controller (parent) node): > +- compatible : Should be "st,miphy28lp-phy" > +- st,syscfg : Should be a phandle of the system configuration register group > + which contain the SATA, PCIe or USB3 mode setting bits > + > +Required nodes : A sub-node is required for each channel the controller > + provides. Address range information including the usual > + 'reg' and 'reg-names' properties are used inside these > + nodes to describe the controller's topology. These nodes > + are translated by the driver's .xlate() function. > + > +Required properties (port (child) node): > +- #phy-cells : Should be 1 (See second example) > + Cell after port phandle is device type from: > + - MIPHY_TYPE_SATA > + - MIPHY_TYPE_PCI > + - MIPHY_TYPE_USB3 > +- reg : Address and length of the register set for the device > +- reg-names : The names of the register addresses corresponding to the registers > + filled in "reg". Is can also contain the offset of the system configuration %s/Is/It Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html