[PATCH v2 0/2] Add DRA7xx CPSW Ethernet support in Device Tree

[PATCH v2 0/2] Add DRA7xx CPSW Ethernet support in Device Tree

[Mugunthan V N]

Adding device tree entry for CPSW to make it work in Dual EMAC mode.
These patches were tested with DRA7 hwmod patches on top of linux-next.
Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed
my tree to [2].

Did a boot test with CPSW and ping test with suspend/resume, the boot logs
on DRA7xx EVM are posted at [3]

[1] git://github.com/nmenon/linux-2.6-playground.git testing/v3.17/cpu-idle-suspend-dra7-omap5-framework
[2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git v3.17/dra7-evm-cpsw
[3] http://pastebin.ubuntu.com/8309289/

Changes from initial version:
* Dropped patch for pinoff states
* Changed pinoff state to mode15

Mugunthan V N (2):
  ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7
  ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM

 arch/arm/boot/dts/dra7-evm.dts | 107 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi    |  59 +++++++++++++++++++++++
 2 files changed, 166 insertions(+)

-- 
2.1.0

[PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7

[Mugunthan V N]

Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d678152..8d79321 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
 		serial3 = &uart4;
 		serial4 = &uart5;
 		serial5 = &uart6;
+		ethernet0 = &cpsw_emac0;
+		ethernet1 = &cpsw_emac1;
 	};
 
 	timer {
@@ -1262,6 +1264,63 @@
 			ti,irqs-skip = <10 133 139 140>;
 			ti,irqs-safe-map = <0>;
 		};
+
+		mac: ethernet@4a100000 {
+			compatible = "ti,cpsw";
+			ti,hwmods = "gmac";
+			cpdma_channels = <8>;
+			ale_entries = <1024>;
+			bd_ram_size = <0x2000>;
+			no_bd_ram = <0>;
+			rx_descs = <64>;
+			mac_control = <0x20>;
+			slaves = <2>;
+			active_slave = <0>;
+			cpts_clock_mult = <0x80000000>;
+			cpts_clock_shift = <29>;
+			reg = <0x48484000 0x1000
+			       0x48485200 0x2E00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/*
+			 * rx_thresh_pend
+			 * rx_pend
+			 * tx_pend
+			 * misc_pend
+			 */
+			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+			ranges;
+			status = "disabled";
+
+			davinci_mdio: mdio@48485000 {
+				compatible = "ti,davinci_mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				ti,hwmods = "davinci_mdio";
+				bus_freq = <1000000>;
+				reg = <0x48485000 0x100>;
+			};
+
+			cpsw_emac0: slave@48480200 {
+				/* Filled in by U-Boot */
+				mac-address = [ 00 00 00 00 00 00 ];
+			};
+
+			cpsw_emac1: slave@48480300 {
+				/* Filled in by U-Boot */
+				mac-address = [ 00 00 00 00 00 00 ];
+			};
+
+			phy_sel: cpsw-phy-sel@4a002554 {
+				compatible = "ti,dra7xx-cpsw-phy-sel";
+				reg= <0x4a002554 0x4>;
+				reg-names = "gmii-sel";
+			};
+		};
+
 	};
 };
 
-- 
2.1.0

Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7

[Nishanth Menon]

On 09/10/2014 08:37 AM, Mugunthan V N wrote:
> Add CPSW and MDIO related device tree data for DRA7XX and made as status
> disabled. Phy-id, pinmux for active and sleep state needs to be added in
> board dts files and enable the CPSW device.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  arch/arm/boot/dts/dra7.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index d678152..8d79321 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -34,6 +34,8 @@
>  		serial3 = &uart4;
>  		serial4 = &uart5;
>  		serial5 = &uart6;
> +		ethernet0 = &cpsw_emac0;
> +		ethernet1 = &cpsw_emac1;

should this rather be in board dts?

>  	};
>  
>  	timer {
> @@ -1262,6 +1264,63 @@
>  			ti,irqs-skip = <10 133 139 140>;
>  			ti,irqs-safe-map = <0>;
>  		};
> +
> +		mac: ethernet@4a100000 {
> +			compatible = "ti,cpsw";
> +			ti,hwmods = "gmac";
> +			cpdma_channels = <8>;
> +			ale_entries = <1024>;
> +			bd_ram_size = <0x2000>;
> +			no_bd_ram = <0>;
> +			rx_descs = <64>;
> +			mac_control = <0x20>;
> +			slaves = <2>;
> +			active_slave = <0>;
> +			cpts_clock_mult = <0x80000000>;
> +			cpts_clock_shift = <29>;
> +			reg = <0x48484000 0x1000
> +			       0x48485200 0x2E00>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			/*
> +			 * rx_thresh_pend
> +			 * rx_pend
> +			 * tx_pend
> +			 * misc_pend
> +			 */
> +			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
> +			ranges;
> +			status = "disabled";
> +
> +			davinci_mdio: mdio@48485000 {
> +				compatible = "ti,davinci_mdio";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				ti,hwmods = "davinci_mdio";
> +				bus_freq = <1000000>;
> +				reg = <0x48485000 0x100>;
> +			};
> +
> +			cpsw_emac0: slave@48480200 {
> +				/* Filled in by U-Boot */
> +				mac-address = [ 00 00 00 00 00 00 ];

should be disabled? what about platforms that do not have both emac ports?

> +			};
> +
> +			cpsw_emac1: slave@48480300 {
> +				/* Filled in by U-Boot */
> +				mac-address = [ 00 00 00 00 00 00 ];

should be disabled? what about platforms that do not have both emac ports?

> +			};
> +
> +			phy_sel: cpsw-phy-sel@4a002554 {
> +				compatible = "ti,dra7xx-cpsw-phy-sel";
> +				reg= <0x4a002554 0x4>;
> +				reg-names = "gmii-sel";
> +			};
> +		};
> +
>  	};
>  };
>  
> 


-- 
Regards,
Nishanth Menon

Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7

[Mugunthan V N]

On Wednesday 10 September 2014 07:20 PM, Nishanth Menon wrote:
> On 09/10/2014 08:37 AM, Mugunthan V N wrote:
>> Add CPSW and MDIO related device tree data for DRA7XX and made as status
>> disabled. Phy-id, pinmux for active and sleep state needs to be added in
>> board dts files and enable the CPSW device.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm-l0cyMroinI0@public.gmane.org>
>> ---
>>  arch/arm/boot/dts/dra7.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 59 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index d678152..8d79321 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -34,6 +34,8 @@
>>  		serial3 = &uart4;
>>  		serial4 = &uart5;
>>  		serial5 = &uart6;
>> +		ethernet0 = &cpsw_emac0;
>> +		ethernet1 = &cpsw_emac1;
> 
> should this rather be in board dts?

This should be here as the MAC address is filled in uboot with ethernet0
and ethernet1, moving this to dts, the ordering of the ethernet can go
for toss when they have other ethernet devices other than cpsw.

> 
>>  	};
>>  
>>  	timer {
>> @@ -1262,6 +1264,63 @@
>>  			ti,irqs-skip = <10 133 139 140>;
>>  			ti,irqs-safe-map = <0>;
>>  		};
>> +
>> +		mac: ethernet@4a100000 {
>> +			compatible = "ti,cpsw";
>> +			ti,hwmods = "gmac";
>> +			cpdma_channels = <8>;
>> +			ale_entries = <1024>;
>> +			bd_ram_size = <0x2000>;
>> +			no_bd_ram = <0>;
>> +			rx_descs = <64>;
>> +			mac_control = <0x20>;
>> +			slaves = <2>;
>> +			active_slave = <0>;
>> +			cpts_clock_mult = <0x80000000>;
>> +			cpts_clock_shift = <29>;
>> +			reg = <0x48484000 0x1000
>> +			       0x48485200 0x2E00>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			/*
>> +			 * rx_thresh_pend
>> +			 * rx_pend
>> +			 * tx_pend
>> +			 * misc_pend
>> +			 */
>> +			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
>> +			ranges;
>> +			status = "disabled";
>> +
>> +			davinci_mdio: mdio@48485000 {
>> +				compatible = "ti,davinci_mdio";
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				ti,hwmods = "davinci_mdio";
>> +				bus_freq = <1000000>;
>> +				reg = <0x48485000 0x100>;
>> +			};
>> +
>> +			cpsw_emac0: slave@48480200 {
>> +				/* Filled in by U-Boot */
>> +				mac-address = [ 00 00 00 00 00 00 ];
> 
> should be disabled? what about platforms that do not have both emac ports?

the mac node is already disabled, so platforms which doesn't have emac
should not enable this which in-turn emac node will be disabled.

Regards
Mugunthan V N
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Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7

[Lennart Sorensen]

On Thu, Sep 11, 2014 at 12:07:45PM +0530, Mugunthan V N wrote:
> On Wednesday 10 September 2014 07:20 PM, Nishanth Menon wrote:
> > On 09/10/2014 08:37 AM, Mugunthan V N wrote:
> >> Add CPSW and MDIO related device tree data for DRA7XX and made as status
> >> disabled. Phy-id, pinmux for active and sleep state needs to be added in
> >> board dts files and enable the CPSW device.
> >>
> >> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> >> ---
> >>  arch/arm/boot/dts/dra7.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 59 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> >> index d678152..8d79321 100644
> >> --- a/arch/arm/boot/dts/dra7.dtsi
> >> +++ b/arch/arm/boot/dts/dra7.dtsi
> >> @@ -34,6 +34,8 @@
> >>  		serial3 = &uart4;
> >>  		serial4 = &uart5;
> >>  		serial5 = &uart6;
> >> +		ethernet0 = &cpsw_emac0;
> >> +		ethernet1 = &cpsw_emac1;
> > 
> > should this rather be in board dts?
> 
> This should be here as the MAC address is filled in uboot with ethernet0
> and ethernet1, moving this to dts, the ordering of the ethernet can go
> for toss when they have other ethernet devices other than cpsw.
> 
> > 
> >>  	};
> >>  
> >>  	timer {
> >> @@ -1262,6 +1264,63 @@
> >>  			ti,irqs-skip = <10 133 139 140>;
> >>  			ti,irqs-safe-map = <0>;
> >>  		};
> >> +
> >> +		mac: ethernet@4a100000 {
> >> +			compatible = "ti,cpsw";
> >> +			ti,hwmods = "gmac";
> >> +			cpdma_channels = <8>;
> >> +			ale_entries = <1024>;
> >> +			bd_ram_size = <0x2000>;
> >> +			no_bd_ram = <0>;
> >> +			rx_descs = <64>;
> >> +			mac_control = <0x20>;
> >> +			slaves = <2>;
> >> +			active_slave = <0>;
> >> +			cpts_clock_mult = <0x80000000>;
> >> +			cpts_clock_shift = <29>;
> >> +			reg = <0x48484000 0x1000
> >> +			       0x48485200 0x2E00>;
> >> +			#address-cells = <1>;
> >> +			#size-cells = <1>;
> >> +			/*
> >> +			 * rx_thresh_pend
> >> +			 * rx_pend
> >> +			 * tx_pend
> >> +			 * misc_pend
> >> +			 */
> >> +			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
> >> +			ranges;
> >> +			status = "disabled";
> >> +
> >> +			davinci_mdio: mdio@48485000 {
> >> +				compatible = "ti,davinci_mdio";
> >> +				#address-cells = <1>;
> >> +				#size-cells = <0>;
> >> +				ti,hwmods = "davinci_mdio";
> >> +				bus_freq = <1000000>;
> >> +				reg = <0x48485000 0x100>;
> >> +			};
> >> +
> >> +			cpsw_emac0: slave@48480200 {
> >> +				/* Filled in by U-Boot */
> >> +				mac-address = [ 00 00 00 00 00 00 ];
> > 
> > should be disabled? what about platforms that do not have both emac ports?
> 
> the mac node is already disabled, so platforms which doesn't have emac
> should not enable this which in-turn emac node will be disabled.

I have the mac but I don't want to use both ports on the 2 port switch.
In fact in our case ethernet1 is a pru_eth interface.  Can a board dts
override the alias for ethernet1 or is that a syntax error?  I don't
think I tried that yet.

-- 
Len Sorensen

Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7

[Mugunthan V N]

On Friday 12 September 2014 02:59 AM, Lennart Sorensen wrote:
> I have the mac but I don't want to use both ports on the 2 port switch.
> In fact in our case ethernet1 is a pru_eth interface.  Can a board dts
> override the alias for ethernet1 or is that a syntax error?  I don't
> think I tried that yet.

You can override it in board dts file

Regards
Mugunthan V N
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Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7

[Lennart Sorensen]

On Wed, Sep 10, 2014 at 07:07:26PM +0530, Mugunthan V N wrote:
> Add CPSW and MDIO related device tree data for DRA7XX and made as status
> disabled. Phy-id, pinmux for active and sleep state needs to be added in
> board dts files and enable the CPSW device.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  arch/arm/boot/dts/dra7.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index d678152..8d79321 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -34,6 +34,8 @@
>  		serial3 = &uart4;
>  		serial4 = &uart5;
>  		serial5 = &uart6;
> +		ethernet0 = &cpsw_emac0;
> +		ethernet1 = &cpsw_emac1;
>  	};
>  
>  	timer {
> @@ -1262,6 +1264,63 @@
>  			ti,irqs-skip = <10 133 139 140>;
>  			ti,irqs-safe-map = <0>;
>  		};
> +
> +		mac: ethernet@4a100000 {
> +			compatible = "ti,cpsw";
> +			ti,hwmods = "gmac";
> +			cpdma_channels = <8>;
> +			ale_entries = <1024>;
> +			bd_ram_size = <0x2000>;
> +			no_bd_ram = <0>;
> +			rx_descs = <64>;
> +			mac_control = <0x20>;
> +			slaves = <2>;

How am I supposed to override this in the board dtb when my board only
uses 1 slave?

> +			active_slave = <0>;
> +			cpts_clock_mult = <0x80000000>;
> +			cpts_clock_shift = <29>;
> +			reg = <0x48484000 0x1000
> +			       0x48485200 0x2E00>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			/*
> +			 * rx_thresh_pend
> +			 * rx_pend
> +			 * tx_pend
> +			 * misc_pend
> +			 */
> +			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
> +			ranges;
> +			status = "disabled";
> +
> +			davinci_mdio: mdio@48485000 {
> +				compatible = "ti,davinci_mdio";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				ti,hwmods = "davinci_mdio";
> +				bus_freq = <1000000>;
> +				reg = <0x48485000 0x100>;
> +			};
> +
> +			cpsw_emac0: slave@48480200 {
> +				/* Filled in by U-Boot */
> +				mac-address = [ 00 00 00 00 00 00 ];
> +			};
> +
> +			cpsw_emac1: slave@48480300 {
> +				/* Filled in by U-Boot */
> +				mac-address = [ 00 00 00 00 00 00 ];
> +			};

Should I then be setting this to disabled from my board file?  Or does
the disabled for the ethernet overall take care of that?

> +			phy_sel: cpsw-phy-sel@4a002554 {
> +				compatible = "ti,dra7xx-cpsw-phy-sel";
> +				reg= <0x4a002554 0x4>;
> +				reg-names = "gmii-sel";
> +			};

I guess the board file would have to disable that too (we won't have a
phy given we are connecting to a switch chip).

> +		};
> +
>  	};
>  };

-- 
Len Sorensen

Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7

[Mugunthan V N]

On Thursday 11 September 2014 07:08 AM, Lennart Sorensen wrote:
> On Wed, Sep 10, 2014 at 07:07:26PM +0530, Mugunthan V N wrote:
>> Add CPSW and MDIO related device tree data for DRA7XX and made as status
>> disabled. Phy-id, pinmux for active and sleep state needs to be added in
>> board dts files and enable the CPSW device.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> ---
>>  arch/arm/boot/dts/dra7.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 59 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index d678152..8d79321 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -34,6 +34,8 @@
>>  		serial3 = &uart4;
>>  		serial4 = &uart5;
>>  		serial5 = &uart6;
>> +		ethernet0 = &cpsw_emac0;
>> +		ethernet1 = &cpsw_emac1;
>>  	};
>>  
>>  	timer {
>> @@ -1262,6 +1264,63 @@
>>  			ti,irqs-skip = <10 133 139 140>;
>>  			ti,irqs-safe-map = <0>;
>>  		};
>> +
>> +		mac: ethernet@4a100000 {
>> +			compatible = "ti,cpsw";
>> +			ti,hwmods = "gmac";
>> +			cpdma_channels = <8>;
>> +			ale_entries = <1024>;
>> +			bd_ram_size = <0x2000>;
>> +			no_bd_ram = <0>;
>> +			rx_descs = <64>;
>> +			mac_control = <0x20>;
>> +			slaves = <2>;
> 
> How am I supposed to override this in the board dtb when my board only
> uses 1 slave?

slaves = <1>;

> 
>> +			active_slave = <0>;
>> +			cpts_clock_mult = <0x80000000>;
>> +			cpts_clock_shift = <29>;
>> +			reg = <0x48484000 0x1000
>> +			       0x48485200 0x2E00>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			/*
>> +			 * rx_thresh_pend
>> +			 * rx_pend
>> +			 * tx_pend
>> +			 * misc_pend
>> +			 */
>> +			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
>> +			ranges;
>> +			status = "disabled";
>> +
>> +			davinci_mdio: mdio@48485000 {
>> +				compatible = "ti,davinci_mdio";
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				ti,hwmods = "davinci_mdio";
>> +				bus_freq = <1000000>;
>> +				reg = <0x48485000 0x100>;
>> +			};
>> +
>> +			cpsw_emac0: slave@48480200 {
>> +				/* Filled in by U-Boot */
>> +				mac-address = [ 00 00 00 00 00 00 ];
>> +			};
>> +
>> +			cpsw_emac1: slave@48480300 {
>> +				/* Filled in by U-Boot */
>> +				mac-address = [ 00 00 00 00 00 00 ];
>> +			};
> 
> Should I then be setting this to disabled from my board file?  Or does
> the disabled for the ethernet overall take care of that?

overall disable takes care of this

> 
>> +			phy_sel: cpsw-phy-sel@4a002554 {
>> +				compatible = "ti,dra7xx-cpsw-phy-sel";
>> +				reg= <0x4a002554 0x4>;
>> +				reg-names = "gmii-sel";
>> +			};
> 
> I guess the board file would have to disable that too (we won't have a
> phy given we are connecting to a switch chip).

Will add disabled in next version.

Regards
Mugunthan V N

Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7

[Lennart Sorensen]

On Thu, Sep 11, 2014 at 12:02:03PM +0530, Mugunthan V N wrote:
> slaves = <1>;

OK, works for me.

> overall disable takes care of this

Although once I enable cpsw I would need to leave the second port disabled
I suppose, although perhaps settings slaves to 1 would essentially
disable it.

> Will add disabled in next version.

-- 
Len Sorensen
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[PATCH v2 2/2] ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM

[Mugunthan V N]

Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts | 107 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 50f8022..e5c4e33 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -151,6 +151,87 @@
 			0xd0	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_be0n_cle */
 		>;
 	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			0x250 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_tclk */
+			0x254 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_tctl */
+			0x258 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td3 */
+			0x25c (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td2 */
+			0x260 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td1 */
+			0x264 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td0 */
+			0x268 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rclk */
+			0x26c (PIN_INPUT | MUX_MODE0)	/* rgmii1_rctl */
+			0x270 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd3 */
+			0x274 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd2 */
+			0x278 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd1 */
+			0x27c (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd0 */
+
+			/* Slave 2 */
+			0x198 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_tclk */
+			0x19c (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_tctl */
+			0x1a0 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td3 */
+			0x1a4 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td2 */
+			0x1a8 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td1 */
+			0x1ac (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td0 */
+			0x1b0 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rclk */
+			0x1b4 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rctl */
+			0x1b8 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd3 */
+			0x1bc (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd2 */
+			0x1c0 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd1 */
+			0x1c4 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd0 */
+		>;
+
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			0x250 (MUX_MODE15)
+			0x254 (MUX_MODE15)
+			0x258 (MUX_MODE15)
+			0x25c (MUX_MODE15)
+			0x260 (MUX_MODE15)
+			0x264 (MUX_MODE15)
+			0x268 (MUX_MODE15)
+			0x26c (MUX_MODE15)
+			0x270 (MUX_MODE15)
+			0x274 (MUX_MODE15)
+			0x278 (MUX_MODE15)
+			0x27c (MUX_MODE15)
+
+			/* Slave 1 */
+			0x198 (MUX_MODE15)
+			0x19c (MUX_MODE15)
+			0x1a0 (MUX_MODE15)
+			0x1a4 (MUX_MODE15)
+			0x1a8 (MUX_MODE15)
+			0x1ac (MUX_MODE15)
+			0x1b0 (MUX_MODE15)
+			0x1b4 (MUX_MODE15)
+			0x1b8 (MUX_MODE15)
+			0x1bc (MUX_MODE15)
+			0x1c0 (MUX_MODE15)
+			0x1c4 (MUX_MODE15)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mdio_data */
+			0x240 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			0x23c (MUX_MODE15)
+			0x240 (MUX_MODE15)
+		>;
+	};
+
 };
 
 &i2c1 {
@@ -504,3 +585,29 @@
 &usb2_phy2 {
 	phy-supply = <&ldousb_reg>;
 };
+
+&mac {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	dual_emac;
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <2>;
+	phy-mode = "rgmii";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <3>;
+	phy-mode = "rgmii";
+	dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+};
-- 
2.1.0

Re: [PATCH v2 2/2] ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM

[Nishanth Menon]

On 09/10/2014 08:37 AM, Mugunthan V N wrote:
> Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
> sleep states and enable them in board evm dts file.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  arch/arm/boot/dts/dra7-evm.dts | 107 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 107 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index 50f8022..e5c4e33 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -151,6 +151,87 @@
>  			0xd0	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_be0n_cle */
>  		>;
>  	};
> +
> +	cpsw_default: cpsw_default {
> +		pinctrl-single,pins = <
> +			/* Slave 1 */
> +			0x250 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_tclk */
> +			0x254 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_tctl */
> +			0x258 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td3 */
> +			0x25c (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td2 */
> +			0x260 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td1 */
> +			0x264 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td0 */
> +			0x268 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rclk */
> +			0x26c (PIN_INPUT | MUX_MODE0)	/* rgmii1_rctl */
> +			0x270 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd3 */
> +			0x274 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd2 */
> +			0x278 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd1 */
> +			0x27c (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd0 */

Cant we do this based on emac0 and emac1?

> +
> +			/* Slave 2 */
> +			0x198 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_tclk */

NAK. reason comment style -> we use the style:
 /* mode0_name.mode3_name */

> +			0x19c (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_tctl */
> +			0x1a0 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td3 */
> +			0x1a4 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td2 */
> +			0x1a8 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td1 */
> +			0x1ac (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td0 */
> +			0x1b0 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rclk */
> +			0x1b4 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rctl */
> +			0x1b8 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd3 */
> +			0x1bc (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd2 */
> +			0x1c0 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd1 */
> +			0x1c4 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd0 */
> +		>;
> +
> +	};
> +
> +	cpsw_sleep: cpsw_sleep {
> +		pinctrl-single,pins = <
> +			/* Slave 1 */
> +			0x250 (MUX_MODE15)
> +			0x254 (MUX_MODE15)
> +			0x258 (MUX_MODE15)
> +			0x25c (MUX_MODE15)
> +			0x260 (MUX_MODE15)
> +			0x264 (MUX_MODE15)
> +			0x268 (MUX_MODE15)
> +			0x26c (MUX_MODE15)
> +			0x270 (MUX_MODE15)
> +			0x274 (MUX_MODE15)
> +			0x278 (MUX_MODE15)
> +			0x27c (MUX_MODE15)
> +
> +			/* Slave 1 */
^^ Slave 1?
> +			0x198 (MUX_MODE15)
> +			0x19c (MUX_MODE15)
> +			0x1a0 (MUX_MODE15)
> +			0x1a4 (MUX_MODE15)
> +			0x1a8 (MUX_MODE15)
> +			0x1ac (MUX_MODE15)
> +			0x1b0 (MUX_MODE15)
> +			0x1b4 (MUX_MODE15)
> +			0x1b8 (MUX_MODE15)
> +			0x1bc (MUX_MODE15)
> +			0x1c0 (MUX_MODE15)
> +			0x1c4 (MUX_MODE15)
> +		>;
> +	};
> +
> +	davinci_mdio_default: davinci_mdio_default {
> +		pinctrl-single,pins = <
> +			/* MDIO */
^^ you can drop the comment. it is redundant.
> +			0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mdio_data */
> +			0x240 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mdio_clk */
> +		>;
> +	};
> +
> +	davinci_mdio_sleep: davinci_mdio_sleep {
> +		pinctrl-single,pins = <
> +			0x23c (MUX_MODE15)
> +			0x240 (MUX_MODE15)
> +		>;
> +	};
> +
>  };
>  
>  &i2c1 {
> @@ -504,3 +585,29 @@
>  &usb2_phy2 {
>  	phy-supply = <&ldousb_reg>;
>  };
> +
> +&mac {
> +	status = "okay";
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&cpsw_default>;
> +	pinctrl-1 = <&cpsw_sleep>;
> +	dual_emac;
> +};
> +
> +&cpsw_emac0 {
> +	phy_id = <&davinci_mdio>, <2>;
> +	phy-mode = "rgmii";
> +	dual_emac_res_vlan = <1>;
> +};
> +
> +&cpsw_emac1 {
> +	phy_id = <&davinci_mdio>, <3>;
> +	phy-mode = "rgmii";
> +	dual_emac_res_vlan = <2>;
> +};
> +
> +&davinci_mdio {
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&davinci_mdio_default>;
> +	pinctrl-1 = <&davinci_mdio_sleep>;
> +};
> 


-- 
Regards,
Nishanth Menon

Re: [PATCH v2 2/2] ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM

[Mugunthan V N]

On Wednesday 10 September 2014 07:26 PM, Nishanth Menon wrote:
> On 09/10/2014 08:37 AM, Mugunthan V N wrote:
>> Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
>> sleep states and enable them in board evm dts file.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> ---
>>  arch/arm/boot/dts/dra7-evm.dts | 107 +++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 107 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>> index 50f8022..e5c4e33 100644
>> --- a/arch/arm/boot/dts/dra7-evm.dts
>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>> @@ -151,6 +151,87 @@
>>  			0xd0	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_be0n_cle */
>>  		>;
>>  	};
>> +
>> +	cpsw_default: cpsw_default {
>> +		pinctrl-single,pins = <
>> +			/* Slave 1 */
>> +			0x250 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_tclk */
>> +			0x254 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_tctl */
>> +			0x258 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td3 */
>> +			0x25c (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td2 */
>> +			0x260 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td1 */
>> +			0x264 (PIN_OUTPUT | MUX_MODE0)	/* rgmii1_td0 */
>> +			0x268 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rclk */
>> +			0x26c (PIN_INPUT | MUX_MODE0)	/* rgmii1_rctl */
>> +			0x270 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd3 */
>> +			0x274 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd2 */
>> +			0x278 (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd1 */
>> +			0x27c (PIN_INPUT | MUX_MODE0)	/* rgmii1_rd0 */
> 
> Cant we do this based on emac0 and emac1?

Cant because CPSW is a single ethernet device and dual EMAC is just a
feature done by register two network device.

> 
>> +
>> +			/* Slave 2 */
>> +			0x198 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_tclk */
> 
> NAK. reason comment style -> we use the style:
>  /* mode0_name.mode3_name */

Will fix this in next version

> 
>> +			0x19c (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_tctl */
>> +			0x1a0 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td3 */
>> +			0x1a4 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td2 */
>> +			0x1a8 (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td1 */
>> +			0x1ac (PIN_OUTPUT | MUX_MODE3)	/* rgmii2_td0 */
>> +			0x1b0 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rclk */
>> +			0x1b4 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rctl */
>> +			0x1b8 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd3 */
>> +			0x1bc (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd2 */
>> +			0x1c0 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd1 */
>> +			0x1c4 (PIN_INPUT | MUX_MODE3)	/* rgmii2_rd0 */
>> +		>;
>> +
>> +	};
>> +
>> +	cpsw_sleep: cpsw_sleep {
>> +		pinctrl-single,pins = <
>> +			/* Slave 1 */
>> +			0x250 (MUX_MODE15)
>> +			0x254 (MUX_MODE15)
>> +			0x258 (MUX_MODE15)
>> +			0x25c (MUX_MODE15)
>> +			0x260 (MUX_MODE15)
>> +			0x264 (MUX_MODE15)
>> +			0x268 (MUX_MODE15)
>> +			0x26c (MUX_MODE15)
>> +			0x270 (MUX_MODE15)
>> +			0x274 (MUX_MODE15)
>> +			0x278 (MUX_MODE15)
>> +			0x27c (MUX_MODE15)
>> +
>> +			/* Slave 1 */
> ^^ Slave 1?

Will fix this in next version

>> +			0x198 (MUX_MODE15)
>> +			0x19c (MUX_MODE15)
>> +			0x1a0 (MUX_MODE15)
>> +			0x1a4 (MUX_MODE15)
>> +			0x1a8 (MUX_MODE15)
>> +			0x1ac (MUX_MODE15)
>> +			0x1b0 (MUX_MODE15)
>> +			0x1b4 (MUX_MODE15)
>> +			0x1b8 (MUX_MODE15)
>> +			0x1bc (MUX_MODE15)
>> +			0x1c0 (MUX_MODE15)
>> +			0x1c4 (MUX_MODE15)
>> +		>;
>> +	};
>> +
>> +	davinci_mdio_default: davinci_mdio_default {
>> +		pinctrl-single,pins = <
>> +			/* MDIO */
> ^^ you can drop the comment. it is redundant.

Will remove this in next version

>> +			0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mdio_data */
>> +			0x240 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mdio_clk */
>> +		>;
>> +	};
>> +
>> +	davinci_mdio_sleep: davinci_mdio_sleep {
>> +		pinctrl-single,pins = <
>> +			0x23c (MUX_MODE15)
>> +			0x240 (MUX_MODE15)
>> +		>;
>> +	};
>> +
>>  };
>>  
>>  &i2c1 {
>> @@ -504,3 +585,29 @@
>>  &usb2_phy2 {
>>  	phy-supply = <&ldousb_reg>;
>>  };
>> +
>> +&mac {
>> +	status = "okay";
>> +	pinctrl-names = "default", "sleep";
>> +	pinctrl-0 = <&cpsw_default>;
>> +	pinctrl-1 = <&cpsw_sleep>;
>> +	dual_emac;
>> +};
>> +
>> +&cpsw_emac0 {
>> +	phy_id = <&davinci_mdio>, <2>;
>> +	phy-mode = "rgmii";
>> +	dual_emac_res_vlan = <1>;
>> +};
>> +
>> +&cpsw_emac1 {
>> +	phy_id = <&davinci_mdio>, <3>;
>> +	phy-mode = "rgmii";
>> +	dual_emac_res_vlan = <2>;
>> +};
>> +
>> +&davinci_mdio {
>> +	pinctrl-names = "default", "sleep";
>> +	pinctrl-0 = <&davinci_mdio_default>;
>> +	pinctrl-1 = <&davinci_mdio_sleep>;
>> +};
>>
> 
> 

Re: [PATCH v2 0/2] Add DRA7xx CPSW Ethernet support in Device Tree

[Nishanth Menon]

On 09/10/2014 08:37 AM, Mugunthan V N wrote:
> Adding device tree entry for CPSW to make it work in Dual EMAC mode.
> These patches were tested with DRA7 hwmod patches on top of linux-next.
> Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed
> my tree to [2].
> 
> Did a boot test with CPSW and ping test with suspend/resume, the boot logs
> on DRA7xx EVM are posted at [3]
> 
> [1] git://github.com/nmenon/linux-2.6-playground.git testing/v3.17/cpu-idle-suspend-dra7-omap5-framework
> [2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git v3.17/dra7-evm-cpsw
> [3] http://pastebin.ubuntu.com/8309289/
> 
> Changes from initial version:
> * Dropped patch for pinoff states
> * Changed pinoff state to mode15
> 
> Mugunthan V N (2):
>   ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7
>   ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM
> 
>  arch/arm/boot/dts/dra7-evm.dts | 107 +++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/dra7.dtsi    |  59 +++++++++++++++++++++++
>  2 files changed, 166 insertions(+)
> 
I did apply these on Tony's
"omap-for-v3.18/dt 6e55426 Merge branch .."
they do apply.

However: why are we not sending dra72-evm.dts changes in the same
series since we claim it to be dra7xx support?

Also, in your tests (http://pastebin.ubuntu.com/8309289/)
echo -n "20">/sys/kernel/debug/pm_debug/wakeup_timer_seconds
ping 172.24.188.1  & (or even better do a transfer of large file in
background)
echo mem > /sys/power/state

transfer/ping should resume seamlessly. (only thing you should be
careful is that the server should not timeout for 20 second inactivity)..

It is a valid test to verify peripheral activity after resume, BUT,
equally important is to verify suspend-resume in the middle of activity.

-- 
Regards,
Nishanth Menon
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Re: [PATCH v2 0/2] Add DRA7xx CPSW Ethernet support in Device Tree

[Mugunthan V N]

On Wednesday 10 September 2014 07:31 PM, Nishanth Menon wrote:
> On 09/10/2014 08:37 AM, Mugunthan V N wrote:
>> Adding device tree entry for CPSW to make it work in Dual EMAC mode.
>> These patches were tested with DRA7 hwmod patches on top of linux-next.
>> Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed
>> my tree to [2].
>>
>> Did a boot test with CPSW and ping test with suspend/resume, the boot logs
>> on DRA7xx EVM are posted at [3]
>>
>> [1] git://github.com/nmenon/linux-2.6-playground.git testing/v3.17/cpu-idle-suspend-dra7-omap5-framework
>> [2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git v3.17/dra7-evm-cpsw
>> [3] http://pastebin.ubuntu.com/8309289/
>>
>> Changes from initial version:
>> * Dropped patch for pinoff states
>> * Changed pinoff state to mode15
>>
>> Mugunthan V N (2):
>>   ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7
>>   ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM
>>
>>  arch/arm/boot/dts/dra7-evm.dts | 107 +++++++++++++++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/dra7.dtsi    |  59 +++++++++++++++++++++++
>>  2 files changed, 166 insertions(+)
>>
> I did apply these on Tony's
> "omap-for-v3.18/dt 6e55426 Merge branch .."
> they do apply.
> 
> However: why are we not sending dra72-evm.dts changes in the same
> series since we claim it to be dra7xx support?

Will add dra72x support and submit the next version.

> 
> Also, in your tests (http://pastebin.ubuntu.com/8309289/)
> echo -n "20">/sys/kernel/debug/pm_debug/wakeup_timer_seconds
> ping 172.24.188.1  & (or even better do a transfer of large file in
> background)
> echo mem > /sys/power/state
> 
> transfer/ping should resume seamlessly. (only thing you should be
> careful is that the server should not timeout for 20 second inactivity)..

ping will resume seamlessly will try tftp and update on my next version
submission. Will add ping test across suspend resume with both ports
while posting my next version

Regards
Mugunthan V N

> 
> It is a valid test to verify peripheral activity after resume, BUT,
> equally important is to verify suspend-resume in the middle of activity.
>