On 09/11/14 17:14, Sonny Rao wrote:
What's being forced? The way internal rom jumps to sram? Is there
any other way that secondary CPUs come out of reset on this SoC?
From looking at the code it seems like the only path is internal rom
jumps to sram (where rockchip_secondary_trampoline lives) which
jumps to rockchip_secondary_startup() which then does an invalidate
and jump to secondary_startup(). Linux controls everything besides
the internal rom. Is something different in your case?
I'm thinking we would have a different boot-method for secure vs.
non-secure
and then we would know to configure cntvoff or not based on the boot
method. Isn't that a reasonable way of knowing what should be done?
It seems like we can at least modify the DT for this SoC.
I still wonder if there is such a bootloader/hypervisor/rom that's
putting this SoC into non-secure mode and not configuring cntvoff.
Doug's comments seem to suggest that the whole world would be
different if this were true. Maybe Heiko knows?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation