From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-ID: <541249B8.301@codeaurora.org> Date: Thu, 11 Sep 2014 18:17:44 -0700 From: Stephen Boyd MIME-Version: 1.0 Subject: Re: [PATCH v2] clocksource: arch_timer: Allow the device tree to specify the physical timer References: <1410452204-7277-1-git-send-email-dianders@chromium.org> <20140911164710.GW6158@arm.com> <5411D528.4050605@arm.com> <5411DA67.2040402@arm.com> <5411DF5D.8060906@arm.com> <54123697.4070804@codeaurora.org> In-Reply-To: Content-Type: multipart/alternative; boundary="------------000003020603090500040908" To: Sonny Rao Cc: Marc Zyngier , Doug Anderson , Will Deacon , "olof@lixom.net" , Catalin Marinas , Mark Rutland , Sudeep Holla , Christopher Covington , Lorenzo Pieralisi , Thomas Gleixner , Daniel Lezcano , Nathan Lynch , "linux-arm-kernel@lists.infradead.org" , "robh+dt@kernel.org" , Pawel Moll , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Heiko Stuebner List-ID: This is a multi-part message in MIME format. --------------000003020603090500040908 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 09/11/14 17:14, Sonny Rao wrote: > On Thu, Sep 11, 2014 at 4:56 PM, Stephen Boyd > wrote: > > > Where does this platform jump to when a CPU comes up? Is it > rockchip_secondary_startup()? I wonder if that path could have this > little bit of assembly to poke the cntvoff in monitor mode and > then jump > to secondary_startup()? Before we boot any secondary CPUs we could > also > read the cntvoff for CPU0 in the platform specific layer (where we > know > we're running in secure mode) and then use that value as the "reset" > value for the secondaries. Or does this platform boot up in secure > mode > some times and non-secure mode other times? > > > Yes, In our case, with our firmware, we will go through some internal > Rom code and then jump to rockchip_secondary_startup, but I don't > think it's correct to force all users of this SoC to do it that way. What's being forced? The way internal rom jumps to sram? Is there any other way that secondary CPUs come out of reset on this SoC? From looking at the code it seems like the only path is internal rom jumps to sram (where rockchip_secondary_trampoline lives) which jumps to rockchip_secondary_startup() which then does an invalidate and jump to secondary_startup(). Linux controls everything besides the internal rom. Is something different in your case? > If there were a reasonable way to determine for sure that we are in > secure mode, then yes we could do what you're suggesting, and I'd be > happy to code that up. > > I think the problem is that there isn't a great way to determine > whether we're in secure mode or not, and this is maybe by design? I > don't particularly understand that design choice. It would be nice to > hear some rationale from ARM folks. > I'm thinking we would have a different boot-method for secure vs. non-secure and then we would know to configure cntvoff or not based on the boot method. Isn't that a reasonable way of knowing what should be done? It seems like we can at least modify the DT for this SoC. I still wonder if there is such a bootloader/hypervisor/rom that's putting this SoC into non-secure mode and not configuring cntvoff. Doug's comments seem to suggest that the whole world would be different if this were true. Maybe Heiko knows? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation --------------000003020603090500040908 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit
On 09/11/14 17:14, Sonny Rao wrote:
On Thu, Sep 11, 2014 at 4:56 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:

Where does this platform jump to when a CPU comes up? Is it
rockchip_secondary_startup()? I wonder if that path could have this
little bit of assembly to poke the cntvoff in monitor mode and then jump
to secondary_startup()? Before we boot any secondary CPUs we could also
read the cntvoff for CPU0 in the platform specific layer (where we know
we're running in secure mode) and then use that value as the "reset"
value for the secondaries. Or does this platform boot up in secure mode
some times and non-secure mode other times?

Yes, In our case, with our firmware, we will go through some internal Rom code and then jump to rockchip_secondary_startup, but I don't think it's correct to force all users of this SoC to do it that way.

What's being forced? The way internal rom jumps to sram? Is there any other way that secondary CPUs come out of reset on this SoC? From looking at the code it seems like the only path is internal rom jumps to sram (where rockchip_secondary_trampoline lives) which jumps to rockchip_secondary_startup() which then does an invalidate and jump to secondary_startup(). Linux controls everything besides the internal rom. Is something different in your case?

 If there were a reasonable way to determine for sure that we are in secure mode, then yes we could do what you're suggesting, and I'd be happy to code that up.

I think the problem is that there isn't a great way to determine whether we're in secure mode or not, and this is maybe by design?  I don't particularly understand that design choice.  It would be nice to hear some rationale from ARM folks.


I'm thinking we would have a different boot-method for secure vs. non-secure and then we would know to configure cntvoff or not based on the boot method. Isn't that a reasonable way of knowing what should be done? It seems like we can at least modify the DT for this SoC.

I still wonder if there is such a bootloader/hypervisor/rom that's putting this SoC into non-secure mode and not configuring cntvoff. Doug's comments seem to suggest that the whole world would be different if this were true. Maybe Heiko knows?
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
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