From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Figa Subject: Re: [PATCH v2 1/3] clk: samsung: exynos3250: Register DMC clk provider Date: Mon, 22 Sep 2014 10:29:39 +0200 Message-ID: <541FDDF3.6020609@gmail.com> References: <1409664077-27121-1-git-send-email-k.kozlowski@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1409664077-27121-1-git-send-email-k.kozlowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org To: Krzysztof Kozlowski , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Kukjin Kim , Ben Dooks , Russell King , Tomasz Figa , Mike Turquette , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Kyungmin Park , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Sylwester Nawrocki List-Id: devicetree@vger.kernel.org On 02.09.2014 15:21, Krzysztof Kozlowski wrote: > Add clock provider for clocks in DMC domain including EPLL and BPLL. The > DMC clocks are necessary for Exynos3 devfreq driver. > > The DMC clock domain uses different address space (0x105C0000) than > standard clock domain (0x10030000 - 0x10050000). The difference is huge > enough to add new DT node for the clock provider, rather than extending > existing address space. > > Signed-off-by: Krzysztof Kozlowski > > --- > > Changes since v1: > ================= > 1. Fix overwritteing main clock provider reg_base with DMC clock domain > reg_basr. This leads to OOPS in suspend. Applied the whole series for next. Best regards, Tomasz