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From: Christopher Covington <cov-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Lorenzo Pieralisi
	<lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>,
	Daniel Lezcano
	<daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	pawel.moll-5wv7dgnIgG8@public.gmane.org,
	ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
	Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Sudeep Holla <Sudeep.Holla-5wv7dgnIgG8@public.gmane.org>,
	Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	Catalin Marinas <Catalin.Marinas-5wv7dgnIgG8@public.gmane.org>,
	Nathan Lynch
	<Nathan_Lynch-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>,
	Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
	Sonny Rao <sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH v3] clocksource: arch_timer: Allow the device tree to specify the physical timer
Date: Mon, 29 Sep 2014 09:12:26 -0400	[thread overview]
Message-ID: <54295ABA.1010806@codeaurora.org> (raw)
In-Reply-To: <1410454801-14231-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>

Hi Doug,

On 09/11/2014 01:00 PM, Doug Anderson wrote:
> Some 32-bit (ARMv7) systems are architected like this:
> 
> * The firmware doesn't know and doesn't care about hypervisor mode and
>   we don't want to add the complexity of hypervisor there.
> 
> * The firmware isn't involved in SMP bringup or resume.
> 
> * The ARCH timer come up with an uninitialized offset between the
>   virtual and physical counters.  Each core gets a different random
>   offset.
> 
> * The device boots in "Secure SVC" mode.

I believe this can safely be detected by whether a write to CNTFRQ succeeds
(handling the UNDEF on failure). I've tested this approach in what I've
determined to be the 19 valid combinations of the following options.

* AArch64 EL3, AArch32 EL3, no EL3
* AArch64 EL2, AArch32 EL2, no EL2
* Start in SVC_N, SVC_S, HYP_N, MON_S

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
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      parent reply	other threads:[~2014-09-29 13:12 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-11 17:00 [PATCH v3] clocksource: arch_timer: Allow the device tree to specify the physical timer Doug Anderson
2014-09-26 10:00 ` Mark Rutland
2014-09-29 17:30   ` Sonny Rao
     [not found]     ` <CAPz6YkWZWgm--6EJxoV1s3zqTNpAF6+CBOrRc5qxdm5=hFzj1w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-01 15:21       ` Doug Anderson
     [not found] ` <1410454801-14231-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-09-29 13:12   ` Christopher Covington [this message]

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