From mboxrd@z Thu Jan  1 00:00:00 1970
From: Qais Yousef <qais.yousef-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH V3 2/4] of: Add binding document for MIPS GIC
Date: Wed, 29 Oct 2014 17:05:13 +0000
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To: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>, Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>, Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>, Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>, Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>, Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>, David Daney <ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Linux-MIPS <linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>, "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
List-Id: devicetree@vger.kernel.org

On 10/29/2014 04:56 PM, Andrew Bresticker wrote:
> On Wed, Oct 29, 2014 at 4:01 AM, Qais Yousef <qais.yousef-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
>> On 10/29/2014 12:12 AM, Andrew Bresticker wrote:
>>> +- mti,available-cpu-vectors : Specifies the list of CPU interrupt vectors
>>> +  to which the GIC may route interrupts.  May contain up to 6 entries,
>>> one
>>> +  for each of the CPU's hardware interrupt vectors.  Valid values are 2 -
>>> 7.
>>> +  This property is ignored if the CPU is started in EIC mode.
>>> +
>>
>> Wouldn't it be better to have this in the reversed sense ie:
>> mti,nonavailable-cpu-vectors? I think the assumption that by default they're
>> all available unless something else is connected to them which is unlikely
>> in most cases. It can be made optional property then.
>>
>> I don't have a strong opinion about it though.
> Actually, I think I like the reversed sense as well.  Perhaps
> "mti,reserved-cpu-vectors"?

Yep that's a better wording for sure :)
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