[PATCH v1 0/4] Enable PCI controller for Keystone SoCs

[PATCH v1 0/4] Enable PCI controller for Keystone SoCs

[Murali Karicheri]

Now that Keystone PCI driver is merged to v3.18, this patch series
add build options and DTS bindings to enable the driver for Keystone SoCs.

v1: resend with some minor fix up of the commit description and fixing
    the email ID for Santosh.

CC: Santosh Shilimkar <ssantosh@kernel.org>
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Russell King <linux@arm.linux.org.uk>
CC: devicetree@vger.kernel.org

Murali Karicheri (4):
  ARM: keystone: add pcie related options
  ARM: keystone: defconfig: add options to enable PCI controller
  ARM: dts: keystone: add DT bindings for PCI controller for port 0
  ARM: dts: keystone-k2e: add DT bindings for PCI controller for port 1

 arch/arm/boot/dts/k2e.dtsi          |   45 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/keystone.dtsi     |   45 +++++++++++++++++++++++++++++++++++
 arch/arm/configs/keystone_defconfig |    3 +++
 arch/arm/mach-keystone/Kconfig      |    2 ++
 4 files changed, 95 insertions(+)

-- 
1.7.9.5

[PATCH v1 3/4] ARM: dts: keystone: add DT bindings for PCI controller for port 0

[Murali Karicheri]

Add common DT bindings to support PCI controller driver for port 0 on all of
the K2 SoCs that has Synopsis Designware based pcie h/w.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
CC: Santosh Shilimkar <ssantosh@kernel.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Russell King <linux@arm.linux.org.uk>
CC: devicetree@vger.kernel.org
---
 v1 - fixed email ID for Santosh and reworded the commit description a bit to
      be consistent with the subject.
 arch/arm/boot/dts/keystone.dtsi |   45 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 5d3e83f..87b2daa 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -285,5 +285,50 @@
 			#interrupt-cells = <1>;
 			ti,syscon-dev = <&devctrl 0x2a0>;
 		};
+
+		pcie@21800000 {
+			compatible = "ti,keystone-pcie", "snps,dw-pcie";
+			clocks = <&clkpcie>;
+			clock-names = "pcie";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
+			ranges = <0x81000000 0 0 0x23250000 0 0x4000
+				0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
+
+			device_type = "pci";
+			num-lanes = <2>;
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>, // INT A
+					<0 0 0 2 &pcie_intc0 1>, // INT B
+					<0 0 0 3 &pcie_intc0 2>, // INT C
+					<0 0 0 4 &pcie_intc0 3>; // INT D
+
+			pcie_msi_intc0: msi-interrupt-controller {
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
+			};
+
+			pcie_intc0: legacy-interrupt-controller {
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
+			};
+		};
 	};
 };
-- 
1.7.9.5

[PATCH v1 4/4] ARM: dts: keystone-k2e: add DT bindings for PCI controller for port 1

[Murali Karicheri]

K2E SoC has a second PCI port based on Synopsis Designware PCIe h/w.
Add DT bindings to support PCI controller for port 1 for this SoC.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
CC: Santosh Shilimkar <ssantosh@kernel.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Russell King <linux@arm.linux.org.uk>
CC: devicetree@vger.kernel.org
---
 v1 - fixed email ID for Santosh and reworded commit description to be
      consistent with the subject.
 arch/arm/boot/dts/k2e.dtsi |   45 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
index c358b4b..e60d128 100644
--- a/arch/arm/boot/dts/k2e.dtsi
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -85,6 +85,51 @@
 			#gpio-cells = <2>;
 			gpio,syscon-dev = <&devctrl 0x240>;
 		};
+
+		pcie@21020000 {
+			compatible = "ti,keystone-pcie","snps,dw-pcie";
+			clocks = <&clkpcie1>;
+			clock-names = "pcie";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+			ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
+				0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
+
+			device_type = "pci";
+			num-lanes = <2>;
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>, // INT A
+					<0 0 0 2 &pcie_intc1 1>, // INT B
+					<0 0 0 3 &pcie_intc1 2>, // INT C
+					<0 0 0 4 &pcie_intc1 3>; // INT D
+
+			pcie_msi_intc1: msi-interrupt-controller {
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
+			};
+
+			pcie_intc1: legacy-interrupt-controller {
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
+			};
+		};
 	};
 };
 
-- 
1.7.9.5

Re: [PATCH v1 3/4] ARM: dts: keystone: add DT bindings for PCI controller for port 0

[Santosh Shilimkar]

On 10/29/2014 09:45 AM, Murali Karicheri wrote:
> Add common DT bindings to support PCI controller driver for port 0 on all of
> the K2 SoCs that has Synopsis Designware based pcie h/w.
>
> Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
> CC: Santosh Shilimkar <ssantosh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> CC: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> CC: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> CC: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> CC: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> CC: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> CC: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> CC: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>   v1 - fixed email ID for Santosh and reworded the commit description a bit to
>        be consistent with the subject.
>   arch/arm/boot/dts/keystone.dtsi |   45 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
> index 5d3e83f..87b2daa 100644
> --- a/arch/arm/boot/dts/keystone.dtsi
> +++ b/arch/arm/boot/dts/keystone.dtsi
> @@ -285,5 +285,50 @@
>   			#interrupt-cells = <1>;
>   			ti,syscon-dev = <&devctrl 0x2a0>;
>   		};
> +
> +		pcie@21800000 {
> +			compatible = "ti,keystone-pcie", "snps,dw-pcie";
> +			clocks = <&clkpcie>;
> +			clock-names = "pcie";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
> +			ranges = <0x81000000 0 0 0x23250000 0 0x4000
> +				0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
> +
> +			device_type = "pci";
> +			num-lanes = <2>;
> +
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>, // INT A
> +					<0 0 0 2 &pcie_intc0 1>, // INT B
> +					<0 0 0 3 &pcie_intc0 2>, // INT C
> +					<0 0 0 4 &pcie_intc0 3>; // INT D
> +
Can you just keep the comments under /* ... * / just to be consistent
across file. Rest of the patch looks fine by me.

Regards,
Santosh
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Re: [PATCH v1 4/4] ARM: dts: keystone-k2e: add DT bindings for PCI controller for port 1

[Santosh Shilimkar]

On 10/29/2014 09:45 AM, Murali Karicheri wrote:
> K2E SoC has a second PCI port based on Synopsis Designware PCIe h/w.
> Add DT bindings to support PCI controller for port 1 for this SoC.
>
> Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
> CC: Santosh Shilimkar <ssantosh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> CC: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> CC: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> CC: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> CC: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> CC: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> CC: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> CC: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>   v1 - fixed email ID for Santosh and reworded commit description to be
>        consistent with the subject.
>   arch/arm/boot/dts/k2e.dtsi |   45 ++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
> index c358b4b..e60d128 100644
> --- a/arch/arm/boot/dts/k2e.dtsi
> +++ b/arch/arm/boot/dts/k2e.dtsi
> @@ -85,6 +85,51 @@
>   			#gpio-cells = <2>;
>   			gpio,syscon-dev = <&devctrl 0x240>;
>   		};
> +
> +		pcie@21020000 {
> +			compatible = "ti,keystone-pcie","snps,dw-pcie";
> +			clocks = <&clkpcie1>;
> +			clock-names = "pcie";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
> +			ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
> +				0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
> +
> +			device_type = "pci";
> +			num-lanes = <2>;
> +
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc1 0>, // INT A
> +					<0 0 0 2 &pcie_intc1 1>, // INT B
> +					<0 0 0 3 &pcie_intc1 2>, // INT C
> +					<0 0 0 4 &pcie_intc1 3>; // INT D
Same comment as last patch. O.w looks fine.

Regards,
Santosh

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Re: [PATCH v1 0/4] Enable PCI controller for Keystone SoCs

[Santosh Shilimkar]

Murali,

On 10/29/2014 09:45 AM, Murali Karicheri wrote:
> Now that Keystone PCI driver is merged to v3.18, this patch series
> add build options and DTS bindings to enable the driver for Keystone SoCs.
>
> v1: resend with some minor fix up of the commit description and fixing
>      the email ID for Santosh.
>
> CC: Santosh Shilimkar <ssantosh@kernel.org>
> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Pawel Moll <pawel.moll@arm.com>
> CC: Mark Rutland <mark.rutland@arm.com>
> CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
> CC: Kumar Gala <galak@codeaurora.org>
> CC: Russell King <linux@arm.linux.org.uk>
> CC: devicetree@vger.kernel.org
>
> Murali Karicheri (4):
>    ARM: keystone: add pcie related options
>    ARM: keystone: defconfig: add options to enable PCI controller
>    ARM: dts: keystone: add DT bindings for PCI controller for port 0
>    ARM: dts: keystone-k2e: add DT bindings for PCI controller for port 1
>
Couple of minor comments o.w series looks fine by me. Once you
address the comment, please post updated version and I shall
queue that up for the next merge window.

Regards,
Santosh

Re: [PATCH v1 0/4] Enable PCI controller for Keystone SoCs

[Murali Karicheri]

On 10/29/2014 03:07 PM, Santosh Shilimkar wrote:
> Murali,
>
> On 10/29/2014 09:45 AM, Murali Karicheri wrote:
>> Now that Keystone PCI driver is merged to v3.18, this patch series
>> add build options and DTS bindings to enable the driver for Keystone
>> SoCs.
>>
>> v1: resend with some minor fix up of the commit description and fixing
>> the email ID for Santosh.
>>
>> CC: Santosh Shilimkar <ssantosh@kernel.org>
>> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> CC: Rob Herring <robh+dt@kernel.org>
>> CC: Pawel Moll <pawel.moll@arm.com>
>> CC: Mark Rutland <mark.rutland@arm.com>
>> CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
>> CC: Kumar Gala <galak@codeaurora.org>
>> CC: Russell King <linux@arm.linux.org.uk>
>> CC: devicetree@vger.kernel.org
>>
>> Murali Karicheri (4):
>> ARM: keystone: add pcie related options
>> ARM: keystone: defconfig: add options to enable PCI controller
>> ARM: dts: keystone: add DT bindings for PCI controller for port 0
>> ARM: dts: keystone-k2e: add DT bindings for PCI controller for port 1
>>
> Couple of minor comments o.w series looks fine by me. Once you
> address the comment, please post updated version and I shall
> queue that up for the next merge window.
>
> Regards,
> Santosh
Thanks. Will repost with comments addressed.

-- 
Murali Karicheri
Linux Kernel, Texas Instruments