From mboxrd@z Thu Jan 1 00:00:00 1970 From: Srinivas Kandagatla Subject: Re: [PATCH v3 2/6] pinctrl: Introduce pinctrl driver for Qualcomm SSBI PMIC's Date: Mon, 03 Nov 2014 08:48:55 +0000 Message-ID: <54574177.5030906@linaro.org> References: <1407771634-14946-1-git-send-email-iivanov@mm-sol.com> <1407771634-14946-3-git-send-email-iivanov@mm-sol.com> <53F456F3.3000309@linaro.org> <20140820212843.GB16274@sonymobile.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-arm-msm-owner@vger.kernel.org To: Bjorn Andersson , Bjorn Andersson Cc: "Ivan T. Ivanov" , Linus Walleij , Grant Likely , Rob Herring , "linux-arm-msm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" List-Id: devicetree@vger.kernel.org Hi Bjorn, On 20/08/14 23:13, Bjorn Andersson wrote: > On Wed, Aug 20, 2014 at 2:28 PM, Bjorn Andersson > wrote: >> On Wed 20 Aug 01:06 PDT 2014, Srinivas Kandagatla wrote: >>> 2> Looking back at v3.4 kernel, for gpio modes, BIT(0) of bank 0 is set >>> to enable gpio mode. without this bit driver does not work for output pins. >>> >> >> Thanks, I missed that. >> >> Unfortunately, setting that bit results in input not working - the interrupt >> bits are never set for gpios that have that bit set. I'm trying to figure out >> why this is the case before sending out the new version... > > With help from Andy Gross this is now corrected as well, turned out > that BIT(0) in bank0 controls if the "direction" is considered. As I > was tricked by the multiple levels of indirection in the codeaurora > version I got these wrong. > > Will send out an updated version shortly. Did you get a chance to spin a new version of this patcheset? --srini > > Regards, > Bjorn >