* [PATCH v3 00/13] Tegra124 EMC (external memory controller) support
@ 2014-10-29 16:22 Tomeu Vizoso
2014-10-29 16:22 ` [PATCH v3 02/13] of: Document long-ram-code property in nvidia,tegra20-apbmisc Tomeu Vizoso
` (6 more replies)
0 siblings, 7 replies; 23+ messages in thread
From: Tomeu Vizoso @ 2014-10-29 16:22 UTC (permalink / raw)
To: linux-tegra
Cc: Javier Martinez Canillas, Tomeu Vizoso, Alexandre Belloni,
Arnd Bergmann, Bharat Bhushan, devicetree, Greg Kroah-Hartman,
Ivan Khoronzhuk, linux-arm-kernel, linux-kernel, Mikko Perttunen,
Nicolas Ferre, Paul Gortmaker, Peter De Schrijver,
Prabhakar Kushwaha, Scott Wood, Stephen Warren, Thierry Reding
Hello,
in this v3 you can find these changes:
* Have the EMC clock use the emc_lock when writing to the register it shares with the MC clock
* Clarify the wording of the new property added to nvidia,tegra20-apbmisc, as suggested by Mikko
* On Tegra124, have the EMC clock be the parent of the MC clock
It depends on Thierry's MC patches at [0] and a branch can be found at [1]. So
far it has been tested only on a Jetson TK1.
Patch 1: Removes the old EMC clock, that was unused and not functional
Patch 2: Documents bindings for the new long-ram-code property
Patch 3: Adds API for reading the ram code
Patches 4 to 6: Document OF additions
Patch 7: Adds EMC node to Tegra124 DT
Patch 8: Adds timings for Jetson TK1 board
Patch 9: Adds functions to the MC driver so the EMC driver can stay within its
own registers
Patch 10: Adds the actual EMC driver, making use of the new MC API
Patch 11: Adds EMC clock driver, making use of API provided by the EMC driver
Patch 12: Adds debugfs entry for getting and setting the EMC rate
Patch 13: On Tegra124, have the EMC clock be the parent of the MC clock
Regards,
Tomeu
[0] https://github.com/thierryreding/linux/commits/staging/iommu
[1] http://cgit.collabora.com/git/user/tomeu/linux.git/log/?h=emc-v3
Mikko Perttunen (9):
clk: tegra124: Remove old emc clock
soc/tegra: Add ram code reader helper
of: Add Tegra124 EMC bindings
ARM: tegra: Add EMC to Tegra124 device tree
ARM: tegra: Add EMC timings to Jetson TK1 device tree
memory: tegra: Add API needed by the EMC driver
memory: tegra: Add EMC (external memory controller) driver
clk: tegra: Add EMC clock driver
memory: tegra: Add debugfs entry for getting and setting the EMC rate
Tomeu Vizoso (4):
of: Document long-ram-code property in nvidia,tegra20-apbmisc
of: document new emc-timings subnode in nvidia,tegra124-car
of: Document timings subnode of nvidia,tegra-mc
clk: tegra: Set the EMC clock as the parent of the MC clock
.../bindings/clock/nvidia,tegra124-car.txt | 46 +-
.../memory-controllers/nvidia,tegra-mc.txt | 46 +-
.../bindings/memory-controllers/tegra-emc.txt | 118 +
.../bindings/misc/nvidia,tegra20-apbmisc.txt | 2 +
arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2412 ++++++++++++++++++++
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +
arch/arm/boot/dts/tegra124.dtsi | 7 +
drivers/clk/tegra/Makefile | 2 +-
drivers/clk/tegra/clk-divider.c | 2 +-
drivers/clk/tegra/clk-emc.c | 470 ++++
drivers/clk/tegra/clk-tegra124.c | 18 +-
drivers/clk/tegra/clk.h | 2 +
drivers/memory/Kconfig | 10 +
drivers/memory/Makefile | 1 -
drivers/memory/tegra/Makefile | 1 +
drivers/memory/tegra/tegra-mc.c | 172 ++
drivers/memory/tegra/tegra124-emc.c | 1169 ++++++++++
drivers/soc/tegra/fuse/tegra-apbmisc.c | 19 +
include/soc/tegra/fuse.h | 1 +
include/soc/tegra/memory.h | 19 +
20 files changed, 4498 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt
create mode 100644 arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
create mode 100644 drivers/clk/tegra/clk-emc.c
create mode 100644 drivers/memory/tegra/tegra124-emc.c
create mode 100644 include/soc/tegra/memory.h
--
1.9.3
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v3 02/13] of: Document long-ram-code property in nvidia,tegra20-apbmisc 2014-10-29 16:22 [PATCH v3 00/13] Tegra124 EMC (external memory controller) support Tomeu Vizoso @ 2014-10-29 16:22 ` Tomeu Vizoso 2014-10-29 16:22 ` [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car Tomeu Vizoso ` (5 subsequent siblings) 6 siblings, 0 replies; 23+ messages in thread From: Tomeu Vizoso @ 2014-10-29 16:22 UTC (permalink / raw) To: linux-tegra Cc: Javier Martinez Canillas, Tomeu Vizoso, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree, linux-kernel Needed to properly decode the ram code register. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- v3: * Clarify wording as suggested by Mikko --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index b97b8be..d034ff8 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -11,3 +11,5 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). -- 1.9.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car 2014-10-29 16:22 [PATCH v3 00/13] Tegra124 EMC (external memory controller) support Tomeu Vizoso 2014-10-29 16:22 ` [PATCH v3 02/13] of: Document long-ram-code property in nvidia,tegra20-apbmisc Tomeu Vizoso @ 2014-10-29 16:22 ` Tomeu Vizoso 2014-11-06 6:37 ` Alexandre Courbot 2014-10-29 16:22 ` [PATCH v3 05/13] of: Document timings subnode of nvidia,tegra-mc Tomeu Vizoso ` (4 subsequent siblings) 6 siblings, 1 reply; 23+ messages in thread From: Tomeu Vizoso @ 2014-10-29 16:22 UTC (permalink / raw) To: linux-tegra Cc: Javier Martinez Canillas, Tomeu Vizoso, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree, linux-kernel The EMC clock needs some extra information for changing its rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- .../bindings/clock/nvidia,tegra124-car.txt | 46 +++++++++++++++++++++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt index ded5d62..42e0588 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt @@ -19,12 +19,35 @@ Required properties : In clock consumers, this cell represents the bit number in the CAR's array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. +The node should contain a "emc-timings" subnode for each supported RAM type (see +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address being its +RAM_CODE. + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set + is used for. + +Each "emc-timings" node should contain a "timing" subnode for every supported +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as their +unit address. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate to which this timing +relates. +- nvidia,parent-clock-frequency : Should contain the rate at which the current +parent of the EMC clock should be running at this timing. +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names : Must include the following entries: + - emc-parent : the clock that should be the parent of the EMC clock at this +timing. + Example SoC include file: / { - tegra_car: clock { + tegra_car: clock@0,60006000 { compatible = "nvidia,tegra124-car"; - reg = <0x60006000 0x1000>; + reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -60,4 +83,23 @@ Example board file: &tegra_car { clocks = <&clk_32k> <&osc>; }; + + clock@0,60006000 { + emc-timings@3 { + nvidia,ram-code = <3>; + + timing@12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing@20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + }; + }; }; -- 1.9.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car 2014-10-29 16:22 ` [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car Tomeu Vizoso @ 2014-11-06 6:37 ` Alexandre Courbot [not found] ` <545B172C.4060105-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-11-06 15:12 ` Rob Herring 0 siblings, 2 replies; 23+ messages in thread From: Alexandre Courbot @ 2014-11-06 6:37 UTC (permalink / raw) To: Tomeu Vizoso, linux-tegra Cc: Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree, linux-kernel On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: > The EMC clock needs some extra information for changing its rate. > > Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> > --- > .../bindings/clock/nvidia,tegra124-car.txt | 46 +++++++++++++++++++++- > 1 file changed, 44 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt > index ded5d62..42e0588 100644 > --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt > +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt > @@ -19,12 +19,35 @@ Required properties : > In clock consumers, this cell represents the bit number in the CAR's > array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. > > +The node should contain a "emc-timings" subnode for each supported RAM type (see > +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address being its > +RAM_CODE. > + > +Required properties for "emc-timings" nodes : > +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set > + is used for. > + > +Each "emc-timings" node should contain a "timing" subnode for every supported > +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as their > +unit address. This seems to be a quite liberal use of unit addresses (same in the next patch) - is this allowed by DT? > + > +Required properties for "timing" nodes : > +- clock-frequency : Should contain the memory clock rate to which this timing > +relates. > +- nvidia,parent-clock-frequency : Should contain the rate at which the current > +parent of the EMC clock should be running at this timing. > +- clocks : Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names : Must include the following entries: > + - emc-parent : the clock that should be the parent of the EMC clock at this > +timing. > + > Example SoC include file: > > / { > - tegra_car: clock { > + tegra_car: clock@0,60006000 { > compatible = "nvidia,tegra124-car"; > - reg = <0x60006000 0x1000>; > + reg = <0x0 0x60006000 0x0 0x1000>; > #clock-cells = <1>; > #reset-cells = <1>; > }; > @@ -60,4 +83,23 @@ Example board file: > &tegra_car { > clocks = <&clk_32k> <&osc>; > }; > + > + clock@0,60006000 { > + emc-timings@3 { > + nvidia,ram-code = <3>; > + > + timing@12750000 { > + clock-frequency = <12750000>; > + nvidia,parent-clock-frequency = <408000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; > + clock-names = "emc-parent"; > + }; > + timing@20400000 { > + clock-frequency = <20400000>; > + nvidia,parent-clock-frequency = <408000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; > + clock-names = "emc-parent"; > + }; > + }; > + }; At first it seems confusing to see a top-level node without a compatible property, until you realize it has already been defined before. In patch 05, you put "Example board file:" above a similar node, which is enough to lift that ambiguity - could you do the same here? ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <545B172C.4060105-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car [not found] ` <545B172C.4060105-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-11-06 9:11 ` Tomeu Vizoso [not found] ` <CAAObsKBe8kigKfEs_ER+1X5fqLw3dZD69XHicEn4cVuQTyoFAw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Tomeu Vizoso @ 2014-11-06 9:11 UTC (permalink / raw) To: Alexandre Courbot Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On 6 November 2014 07:37, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: > On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >> >> The EMC clock needs some extra information for changing its rate. >> >> Signed-off-by: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> >> --- >> .../bindings/clock/nvidia,tegra124-car.txt | 46 >> +++++++++++++++++++++- >> 1 file changed, 44 insertions(+), 2 deletions(-) >> >> diff --git >> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >> index ded5d62..42e0588 100644 >> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >> @@ -19,12 +19,35 @@ Required properties : >> In clock consumers, this cell represents the bit number in the CAR's >> array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. >> >> +The node should contain a "emc-timings" subnode for each supported RAM >> type (see >> +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address >> being its >> +RAM_CODE. >> + >> +Required properties for "emc-timings" nodes : >> +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set >> + is used for. >> + >> +Each "emc-timings" node should contain a "timing" subnode for every >> supported >> +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as >> their >> +unit address. > > > This seems to be a quite liberal use of unit addresses (same in the next > patch) - is this allowed by DT? Well, it's not that different from using the register address. I think it helps with readability more than an arbitrary index. >> + >> +Required properties for "timing" nodes : >> +- clock-frequency : Should contain the memory clock rate to which this >> timing >> +relates. >> +- nvidia,parent-clock-frequency : Should contain the rate at which the >> current >> +parent of the EMC clock should be running at this timing. >> +- clocks : Must contain an entry for each entry in clock-names. >> + See ../clocks/clock-bindings.txt for details. >> +- clock-names : Must include the following entries: >> + - emc-parent : the clock that should be the parent of the EMC clock at >> this >> +timing. >> + >> Example SoC include file: >> >> / { >> - tegra_car: clock { >> + tegra_car: clock@0,60006000 { >> compatible = "nvidia,tegra124-car"; >> - reg = <0x60006000 0x1000>; >> + reg = <0x0 0x60006000 0x0 0x1000>; >> #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> @@ -60,4 +83,23 @@ Example board file: >> &tegra_car { >> clocks = <&clk_32k> <&osc>; >> }; >> + >> + clock@0,60006000 { >> + emc-timings@3 { >> + nvidia,ram-code = <3>; >> + >> + timing@12750000 { >> + clock-frequency = <12750000>; >> + nvidia,parent-clock-frequency = >> <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; >> + }; >> + timing@20400000 { >> + clock-frequency = <20400000>; >> + nvidia,parent-clock-frequency = >> <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; >> + }; >> + }; >> + }; > > > At first it seems confusing to see a top-level node without a compatible > property, until you realize it has already been defined before. > > In patch 05, you put "Example board file:" above a similar node, which is > enough to lift that ambiguity - could you do the same here? Oh, actually it was already in the file. I took this idea from here for patch 05. Thanks, Tomeu > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <CAAObsKBe8kigKfEs_ER+1X5fqLw3dZD69XHicEn4cVuQTyoFAw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car [not found] ` <CAAObsKBe8kigKfEs_ER+1X5fqLw3dZD69XHicEn4cVuQTyoFAw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-11-06 9:15 ` Alexandre Courbot 0 siblings, 0 replies; 23+ messages in thread From: Alexandre Courbot @ 2014-11-06 9:15 UTC (permalink / raw) To: Tomeu Vizoso Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On 11/06/2014 06:11 PM, Tomeu Vizoso wrote: > On 6 November 2014 07:37, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: >> On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >>> >>> The EMC clock needs some extra information for changing its rate. >>> >>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> >>> --- >>> .../bindings/clock/nvidia,tegra124-car.txt | 46 >>> +++++++++++++++++++++- >>> 1 file changed, 44 insertions(+), 2 deletions(-) >>> >>> diff --git >>> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>> index ded5d62..42e0588 100644 >>> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>> @@ -19,12 +19,35 @@ Required properties : >>> In clock consumers, this cell represents the bit number in the CAR's >>> array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. >>> >>> +The node should contain a "emc-timings" subnode for each supported RAM >>> type (see >>> +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address >>> being its >>> +RAM_CODE. >>> + >>> +Required properties for "emc-timings" nodes : >>> +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set >>> + is used for. >>> + >>> +Each "emc-timings" node should contain a "timing" subnode for every >>> supported >>> +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as >>> their >>> +unit address. >> >> >> This seems to be a quite liberal use of unit addresses (same in the next >> patch) - is this allowed by DT? > > Well, it's not that different from using the register address. I think > it helps with readability more than an arbitrary index. > >>> + >>> +Required properties for "timing" nodes : >>> +- clock-frequency : Should contain the memory clock rate to which this >>> timing >>> +relates. >>> +- nvidia,parent-clock-frequency : Should contain the rate at which the >>> current >>> +parent of the EMC clock should be running at this timing. >>> +- clocks : Must contain an entry for each entry in clock-names. >>> + See ../clocks/clock-bindings.txt for details. >>> +- clock-names : Must include the following entries: >>> + - emc-parent : the clock that should be the parent of the EMC clock at >>> this >>> +timing. >>> + >>> Example SoC include file: >>> >>> / { >>> - tegra_car: clock { >>> + tegra_car: clock@0,60006000 { >>> compatible = "nvidia,tegra124-car"; >>> - reg = <0x60006000 0x1000>; >>> + reg = <0x0 0x60006000 0x0 0x1000>; >>> #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> @@ -60,4 +83,23 @@ Example board file: >>> &tegra_car { >>> clocks = <&clk_32k> <&osc>; >>> }; >>> + >>> + clock@0,60006000 { >>> + emc-timings@3 { >>> + nvidia,ram-code = <3>; >>> + >>> + timing@12750000 { >>> + clock-frequency = <12750000>; >>> + nvidia,parent-clock-frequency = >>> <408000000>; >>> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >>> + clock-names = "emc-parent"; >>> + }; >>> + timing@20400000 { >>> + clock-frequency = <20400000>; >>> + nvidia,parent-clock-frequency = >>> <408000000>; >>> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >>> + clock-names = "emc-parent"; >>> + }; >>> + }; >>> + }; >> >> >> At first it seems confusing to see a top-level node without a compatible >> property, until you realize it has already been defined before. >> >> In patch 05, you put "Example board file:" above a similar node, which is >> enough to lift that ambiguity - could you do the same here? > > Oh, actually it was already in the file. I took this idea from here > for patch 05. My bad, missed it! -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car 2014-11-06 6:37 ` Alexandre Courbot [not found] ` <545B172C.4060105-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-11-06 15:12 ` Rob Herring 2014-11-07 5:31 ` Alexandre Courbot [not found] ` <CAL_JsqKYSF3JVrXH_dkqRXQrgUU3igzvoK1C2k1Caz-4UuHX6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 1 sibling, 2 replies; 23+ messages in thread From: Rob Herring @ 2014-11-06 15:12 UTC (permalink / raw) To: Alexandre Courbot Cc: Tomeu Vizoso, linux-tegra@vger.kernel.org, Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org On Thu, Nov 6, 2014 at 12:37 AM, Alexandre Courbot <acourbot@nvidia.com> wrote: > On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >> >> The EMC clock needs some extra information for changing its rate. >> >> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> >> --- >> .../bindings/clock/nvidia,tegra124-car.txt | 46 >> +++++++++++++++++++++- >> 1 file changed, 44 insertions(+), 2 deletions(-) >> >> diff --git >> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >> index ded5d62..42e0588 100644 >> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >> @@ -19,12 +19,35 @@ Required properties : >> In clock consumers, this cell represents the bit number in the CAR's >> array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. >> >> +The node should contain a "emc-timings" subnode for each supported RAM >> type (see >> +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address >> being its >> +RAM_CODE. >> + >> +Required properties for "emc-timings" nodes : >> +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set >> + is used for. >> + >> +Each "emc-timings" node should contain a "timing" subnode for every >> supported >> +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as >> their >> +unit address. > > > This seems to be a quite liberal use of unit addresses (same in the next > patch) - is this allowed by DT? No, unit address should match a reg property. >> + >> +Required properties for "timing" nodes : >> +- clock-frequency : Should contain the memory clock rate to which this >> timing >> +relates. >> +- nvidia,parent-clock-frequency : Should contain the rate at which the >> current >> +parent of the EMC clock should be running at this timing. >> +- clocks : Must contain an entry for each entry in clock-names. >> + See ../clocks/clock-bindings.txt for details. >> +- clock-names : Must include the following entries: >> + - emc-parent : the clock that should be the parent of the EMC clock at >> this >> +timing. >> + >> Example SoC include file: >> >> / { >> - tegra_car: clock { >> + tegra_car: clock@0,60006000 { The comma here is wrong. Commas should be used when you have something like PCI bus:dev:func for addressing. >> compatible = "nvidia,tegra124-car"; >> - reg = <0x60006000 0x1000>; >> + reg = <0x0 0x60006000 0x0 0x1000>; The number of cell's is really irrelevant to the example. >> #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> @@ -60,4 +83,23 @@ Example board file: >> &tegra_car { >> clocks = <&clk_32k> <&osc>; >> }; >> + >> + clock@0,60006000 { >> + emc-timings@3 { >> + nvidia,ram-code = <3>; >> + >> + timing@12750000 { >> + clock-frequency = <12750000>; >> + nvidia,parent-clock-frequency = >> <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; Why do you need both clocks and hardcoded values? clock-frequency is the desired freq you want to set TEGRA124_CLK_PLL_P to? The clocks property really belongs as part of the memory controller node or a memory device node. Rob ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car 2014-11-06 15:12 ` Rob Herring @ 2014-11-07 5:31 ` Alexandre Courbot 2014-11-07 11:35 ` Mikko Perttunen [not found] ` <545C5927.3010001-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> [not found] ` <CAL_JsqKYSF3JVrXH_dkqRXQrgUU3igzvoK1C2k1Caz-4UuHX6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 1 sibling, 2 replies; 23+ messages in thread From: Alexandre Courbot @ 2014-11-07 5:31 UTC (permalink / raw) To: Rob Herring Cc: Tomeu Vizoso, linux-tegra@vger.kernel.org, Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org On 11/07/2014 12:12 AM, Rob Herring wrote: > On Thu, Nov 6, 2014 at 12:37 AM, Alexandre Courbot <acourbot@nvidia.com> wrote: >> On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >>> >>> The EMC clock needs some extra information for changing its rate. >>> >>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> >>> --- >>> .../bindings/clock/nvidia,tegra124-car.txt | 46 >>> +++++++++++++++++++++- >>> 1 file changed, 44 insertions(+), 2 deletions(-) >>> >>> diff --git >>> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>> index ded5d62..42e0588 100644 >>> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>> @@ -19,12 +19,35 @@ Required properties : >>> In clock consumers, this cell represents the bit number in the CAR's >>> array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. >>> >>> +The node should contain a "emc-timings" subnode for each supported RAM >>> type (see >>> +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address >>> being its >>> +RAM_CODE. >>> + >>> +Required properties for "emc-timings" nodes : >>> +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set >>> + is used for. >>> + >>> +Each "emc-timings" node should contain a "timing" subnode for every >>> supported >>> +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as >>> their >>> +unit address. >> >> >> This seems to be a quite liberal use of unit addresses (same in the next >> patch) - is this allowed by DT? > > No, unit address should match a reg property. Mmm, would you have any suggestion as to how this can be fixed? Right now what I can think of is either to replace the "clock-frequency" property by "reg" (which would be confusing), or to use a different naming scheme, e.g. timing-12750000. IIUC the naming is not essential for properly parsing these nodes, so maybe the second solution is the way to go? > >>> + >>> +Required properties for "timing" nodes : >>> +- clock-frequency : Should contain the memory clock rate to which this >>> timing >>> +relates. >>> +- nvidia,parent-clock-frequency : Should contain the rate at which the >>> current >>> +parent of the EMC clock should be running at this timing. >>> +- clocks : Must contain an entry for each entry in clock-names. >>> + See ../clocks/clock-bindings.txt for details. >>> +- clock-names : Must include the following entries: >>> + - emc-parent : the clock that should be the parent of the EMC clock at >>> this >>> +timing. >>> + >>> Example SoC include file: >>> >>> / { >>> - tegra_car: clock { >>> + tegra_car: clock@0,60006000 { > > The comma here is wrong. Commas should be used when you have something > like PCI bus:dev:func for addressing. > >>> compatible = "nvidia,tegra124-car"; >>> - reg = <0x60006000 0x1000>; >>> + reg = <0x0 0x60006000 0x0 0x1000>; > > The number of cell's is really irrelevant to the example. > >>> #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> @@ -60,4 +83,23 @@ Example board file: >>> &tegra_car { >>> clocks = <&clk_32k> <&osc>; >>> }; >>> + >>> + clock@0,60006000 { >>> + emc-timings@3 { >>> + nvidia,ram-code = <3>; >>> + >>> + timing@12750000 { >>> + clock-frequency = <12750000>; >>> + nvidia,parent-clock-frequency = >>> <408000000>; >>> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >>> + clock-names = "emc-parent"; > > Why do you need both clocks and hardcoded values? clock-frequency is > the desired freq you want to set TEGRA124_CLK_PLL_P to? That would be nvidia,parent-clock-frequency IIUC, while clock-frequency is the resulting EMC clock. > > The clocks property really belongs as part of the memory controller > node or a memory device node. I would tend to agree here. Tomeu, does it make sense to move these properties to the EMC driver instead? ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car 2014-11-07 5:31 ` Alexandre Courbot @ 2014-11-07 11:35 ` Mikko Perttunen [not found] ` <545C5927.3010001-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 1 sibling, 0 replies; 23+ messages in thread From: Mikko Perttunen @ 2014-11-07 11:35 UTC (permalink / raw) To: Alexandre Courbot, Rob Herring Cc: Tomeu Vizoso, linux-tegra@vger.kernel.org, Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org To better facilitate discussion, here's an outline of how the driver works: emc_set_rate (CAR) gets called The current timing (= rate,parent pair) is checked along with the target timing. If the target timing has the same clock source (~parent, see emc_parent_clk_sources in the clk driver), find a timing with a different clock source. This is to prevent a situation where we have switched to a new parent rate but the EMC has not yet been reprogrammed. This new timing is called a backup timing. If a backup timing was required, switch to it (using this same procedure). Set the rate of the new parent to the required rate and enable it. It is important to use the correct parent for each timing, since in addition to the rate requirements, there are jitter requirements. The specified timings have been verified by a hardware team. Call tegra_emc_prepare_timing_change. This does assorted things to prepare the EMC block for a timing change and also tells the MC driver to prepare for it. Prepare the value that will be written to CLK_SOURCE_EMC in the CAR block. This value contains the divisor to get from the parent rate to the EMC rate and specifies the parent clock to use. Write the value. This must be done in a single write, as it starts a state machine that uses the written value. Call tegra_emc_complete_timing_change. This will lead the state machine to completion. Tell CCF that our parent is now the specified one. Disable the old parent. Note that information about the parent is only needed within the CAR driver and not in EMC or MC. Those drivers only need to map the EMC rate to a set of configuration values. If the parent clock information is moved under the EMC node, we have some options: a) Add API to EMC that the CAR driver can use to query the parent information. b) Add API to CAR that the EMC driver can use to write the rate and parent information. c) Other? Cheers, Mikko. On 11/07/2014 07:31 AM, Alexandre Courbot wrote: > On 11/07/2014 12:12 AM, Rob Herring wrote: >> On Thu, Nov 6, 2014 at 12:37 AM, Alexandre Courbot >> <acourbot@nvidia.com> wrote: >>> On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >>>> >>>> The EMC clock needs some extra information for changing its rate. >>>> >>>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> >>>> --- >>>> .../bindings/clock/nvidia,tegra124-car.txt | 46 >>>> +++++++++++++++++++++- >>>> 1 file changed, 44 insertions(+), 2 deletions(-) >>>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>>> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>>> index ded5d62..42e0588 100644 >>>> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>>> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>>> @@ -19,12 +19,35 @@ Required properties : >>>> In clock consumers, this cell represents the bit number in the >>>> CAR's >>>> array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. >>>> >>>> +The node should contain a "emc-timings" subnode for each supported RAM >>>> type (see >>>> +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address >>>> being its >>>> +RAM_CODE. >>>> + >>>> +Required properties for "emc-timings" nodes : >>>> +- nvidia,ram-code : Should contain the value of RAM_CODE this >>>> timing set >>>> + is used for. >>>> + >>>> +Each "emc-timings" node should contain a "timing" subnode for every >>>> supported >>>> +EMC clock rate. The "timing" subnodes should have the clock rate in >>>> Hz as >>>> their >>>> +unit address. >>> >>> >>> This seems to be a quite liberal use of unit addresses (same in the next >>> patch) - is this allowed by DT? >> >> No, unit address should match a reg property. > > Mmm, would you have any suggestion as to how this can be fixed? Right > now what I can think of is either to replace the "clock-frequency" > property by "reg" (which would be confusing), or to use a different > naming scheme, e.g. timing-12750000. IIUC the naming is not essential > for properly parsing these nodes, so maybe the second solution is the > way to go? > >> >>>> + >>>> +Required properties for "timing" nodes : >>>> +- clock-frequency : Should contain the memory clock rate to which this >>>> timing >>>> +relates. >>>> +- nvidia,parent-clock-frequency : Should contain the rate at which the >>>> current >>>> +parent of the EMC clock should be running at this timing. >>>> +- clocks : Must contain an entry for each entry in clock-names. >>>> + See ../clocks/clock-bindings.txt for details. >>>> +- clock-names : Must include the following entries: >>>> + - emc-parent : the clock that should be the parent of the EMC >>>> clock at >>>> this >>>> +timing. >>>> + >>>> Example SoC include file: >>>> >>>> / { >>>> - tegra_car: clock { >>>> + tegra_car: clock@0,60006000 { >> >> The comma here is wrong. Commas should be used when you have something >> like PCI bus:dev:func for addressing. >> >>>> compatible = "nvidia,tegra124-car"; >>>> - reg = <0x60006000 0x1000>; >>>> + reg = <0x0 0x60006000 0x0 0x1000>; >> >> The number of cell's is really irrelevant to the example. >> >>>> #clock-cells = <1>; >>>> #reset-cells = <1>; >>>> }; >>>> @@ -60,4 +83,23 @@ Example board file: >>>> &tegra_car { >>>> clocks = <&clk_32k> <&osc>; >>>> }; >>>> + >>>> + clock@0,60006000 { >>>> + emc-timings@3 { >>>> + nvidia,ram-code = <3>; >>>> + >>>> + timing@12750000 { >>>> + clock-frequency = <12750000>; >>>> + nvidia,parent-clock-frequency = >>>> <408000000>; >>>> + clocks = <&tegra_car >>>> TEGRA124_CLK_PLL_P>; >>>> + clock-names = "emc-parent"; >> >> Why do you need both clocks and hardcoded values? clock-frequency is >> the desired freq you want to set TEGRA124_CLK_PLL_P to? > > That would be nvidia,parent-clock-frequency IIUC, while clock-frequency > is the resulting EMC clock. > >> >> The clocks property really belongs as part of the memory controller >> node or a memory device node. > > I would tend to agree here. Tomeu, does it make sense to move these > properties to the EMC driver instead? > -- > To unsubscribe from this list: send the line "unsubscribe linux-tegra" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <545C5927.3010001-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car [not found] ` <545C5927.3010001-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-11-07 13:03 ` Tomeu Vizoso 0 siblings, 0 replies; 23+ messages in thread From: Tomeu Vizoso @ 2014-11-07 13:03 UTC (permalink / raw) To: Alexandre Courbot, Rob Herring Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On 11/07/2014 06:31 AM, Alexandre Courbot wrote: > On 11/07/2014 12:12 AM, Rob Herring wrote: >> On Thu, Nov 6, 2014 at 12:37 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: >>> On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >>>> >>>> The EMC clock needs some extra information for changing its rate. >>>> >>>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> >>>> --- >>>> .../bindings/clock/nvidia,tegra124-car.txt | 46 >>>> +++++++++++++++++++++- >>>> 1 file changed, 44 insertions(+), 2 deletions(-) >>>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>>> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>>> index ded5d62..42e0588 100644 >>>> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>>> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt >>>> @@ -19,12 +19,35 @@ Required properties : >>>> In clock consumers, this cell represents the bit number in the CAR's >>>> array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. >>>> >>>> +The node should contain a "emc-timings" subnode for each supported RAM >>>> type (see >>>> +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address >>>> being its >>>> +RAM_CODE. >>>> + >>>> +Required properties for "emc-timings" nodes : >>>> +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set >>>> + is used for. >>>> + >>>> +Each "emc-timings" node should contain a "timing" subnode for every >>>> supported >>>> +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as >>>> their >>>> +unit address. >>> >>> >>> This seems to be a quite liberal use of unit addresses (same in the next >>> patch) - is this allowed by DT? >> >> No, unit address should match a reg property. > > Mmm, would you have any suggestion as to how this can be fixed? Right > now what I can think of is either to replace the "clock-frequency" > property by "reg" (which would be confusing), or to use a different > naming scheme, e.g. timing-12750000. IIUC the naming is not essential > for properly parsing these nodes, so maybe the second solution is the > way to go? Yeah, there seems to be a precedent for embedding the frequency in the node name in the TI DTs, e.g.: virt_12000000_ck. Thanks, Tomeu ^ permalink raw reply [flat|nested] 23+ messages in thread
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* Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car [not found] ` <CAL_JsqKYSF3JVrXH_dkqRXQrgUU3igzvoK1C2k1Caz-4UuHX6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-11-07 13:10 ` Tomeu Vizoso 0 siblings, 0 replies; 23+ messages in thread From: Tomeu Vizoso @ 2014-11-07 13:10 UTC (permalink / raw) To: Rob Herring, Alexandre Courbot Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, Peter De Schrijver, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On 11/06/2014 04:12 PM, Rob Herring wrote: > On Thu, Nov 6, 2014 at 12:37 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: >> On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >>> #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> @@ -60,4 +83,23 @@ Example board file: >>> &tegra_car { >>> clocks = <&clk_32k> <&osc>; >>> }; >>> + >>> + clock@0,60006000 { >>> + emc-timings@3 { >>> + nvidia,ram-code = <3>; >>> + >>> + timing@12750000 { >>> + clock-frequency = <12750000>; >>> + nvidia,parent-clock-frequency = >>> <408000000>; >>> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >>> + clock-names = "emc-parent"; > > Why do you need both clocks and hardcoded values? clock-frequency is > the desired freq you want to set TEGRA124_CLK_PLL_P to? For the EMC clock to run at 12.75 MHz, its parent should become TEGRA124_CLK_PLL_P and it has to be running at 408 MHz. > The clocks property really belongs as part of the memory controller > node or a memory device node. What would be the rationale for that? The clock provider needs to know what clock should become the parent of the EMC clock when changing rates. Thanks, Tomeu ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 05/13] of: Document timings subnode of nvidia,tegra-mc 2014-10-29 16:22 [PATCH v3 00/13] Tegra124 EMC (external memory controller) support Tomeu Vizoso 2014-10-29 16:22 ` [PATCH v3 02/13] of: Document long-ram-code property in nvidia,tegra20-apbmisc Tomeu Vizoso 2014-10-29 16:22 ` [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car Tomeu Vizoso @ 2014-10-29 16:22 ` Tomeu Vizoso [not found] ` <1414599796-30597-6-git-send-email-tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> 2014-10-29 16:22 ` [PATCH v3 06/13] of: Add Tegra124 EMC bindings Tomeu Vizoso ` (3 subsequent siblings) 6 siblings, 1 reply; 23+ messages in thread From: Tomeu Vizoso @ 2014-10-29 16:22 UTC (permalink / raw) To: linux-tegra Cc: Javier Martinez Canillas, Tomeu Vizoso, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree, linux-kernel The MC driver needs some timing-specific information to program the EMEM during a rate change of the EMC clock. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- .../memory-controllers/nvidia,tegra-mc.txt | 46 +++++++++++++++++++++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt index f3db93c..8467b8c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt @@ -15,9 +15,26 @@ Required properties: This device implements an IOMMU that complies with the generic IOMMU binding. See ../iommu/iommu.txt for details. -Example: --------- +The node should contain a "timings" subnode for each supported RAM type (see +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address being its +RAM_CODE. +Required properties for "timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used +for. + +Each "timings" node should contain a "timing" subnode for every supported EMC +clock rate. The "timing" subnodes should have the clock rate in Hz as their unit +address. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- nvidia,emem-configuration : Values to be written to the EMEM register block, +as specified by the board documentation. + +Example SoC include file: + +/ { mc: memory-controller@0,70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; @@ -34,3 +51,28 @@ Example: ... iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; }; +}; + +Example board file: + +/ { + memory-controller@0,70019000 { + timings@3 { + nvidia,ram-code = <3>; + + timing@12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + >; + }; + }; + }; +}; -- 1.9.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
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* Re: [PATCH v3 05/13] of: Document timings subnode of nvidia,tegra-mc [not found] ` <1414599796-30597-6-git-send-email-tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> @ 2014-11-06 8:12 ` Alexandre Courbot [not found] ` <545B2D6B.9030001-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Alexandre Courbot @ 2014-11-06 8:12 UTC (permalink / raw) To: Tomeu Vizoso, linux-tegra-u79uwXL29TY76Z2rM5mHXA Cc: Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: > The MC driver needs some timing-specific information to program the EMEM during > a rate change of the EMC clock. > > Signed-off-by: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> > --- > .../memory-controllers/nvidia,tegra-mc.txt | 46 +++++++++++++++++++++- > 1 file changed, 44 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt > index f3db93c..8467b8c 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt > @@ -15,9 +15,26 @@ Required properties: > This device implements an IOMMU that complies with the generic IOMMU binding. > See ../iommu/iommu.txt for details. > > -Example: > --------- > +The node should contain a "timings" subnode for each supported RAM type (see > +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address being its > +RAM_CODE. > > +Required properties for "timings" nodes : > +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used > +for. > + > +Each "timings" node should contain a "timing" subnode for every supported EMC > +clock rate. The "timing" subnodes should have the clock rate in Hz as their unit > +address. In patch 04, a similar sub-node is named "emc-timings". Shouldn't the same name be used here for consistency? Also, it seems like there is a need for timing nodes in the MC to have match timing nodes in the CAR. It would be nice to add that information in all related bindings files. > + > +Required properties for "timing" nodes : > +- clock-frequency : Should contain the memory clock rate in Hz. > +- nvidia,emem-configuration : Values to be written to the EMEM register block, > +as specified by the board documentation. Could you add some more information about which range of registers we are talking about, and whether they must all be specified or only part of them? > + > +Example SoC include file: > + > +/ { > mc: memory-controller@0,70019000 { > compatible = "nvidia,tegra124-mc"; > reg = <0x0 0x70019000 0x0 0x1000>; > @@ -34,3 +51,28 @@ Example: > ... > iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; > }; > +}; > + > +Example board file: > + > +/ { > + memory-controller@0,70019000 { > + timings@3 { > + nvidia,ram-code = <3>; > + > + timing@12750000 { > + clock-frequency = <12750000>; > + > + nvidia,emem-configuration = < > + 0x40040001 /* MC_EMEM_ARB_CFG */ > + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ > + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ > + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ > + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ > + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ > + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ > + >; Looking at the actual board files I suppose this example here is incomplete. It would be nice to make this explicit, maybe by adding "..." on a new line to indicate more registers are expected. ^ permalink raw reply [flat|nested] 23+ messages in thread
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* Re: [PATCH v3 05/13] of: Document timings subnode of nvidia,tegra-mc [not found] ` <545B2D6B.9030001-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-11-06 10:32 ` Tomeu Vizoso 0 siblings, 0 replies; 23+ messages in thread From: Tomeu Vizoso @ 2014-11-06 10:32 UTC (permalink / raw) To: Alexandre Courbot Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Javier Martinez Canillas, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On 6 November 2014 09:12, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: > On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >> >> The MC driver needs some timing-specific information to program the EMEM >> during >> a rate change of the EMC clock. >> >> Signed-off-by: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> >> --- >> .../memory-controllers/nvidia,tegra-mc.txt | 46 >> +++++++++++++++++++++- >> 1 file changed, 44 insertions(+), 2 deletions(-) >> >> diff --git >> a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt >> b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt >> index f3db93c..8467b8c 100644 >> --- >> a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt >> +++ >> b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt >> @@ -15,9 +15,26 @@ Required properties: >> This device implements an IOMMU that complies with the generic IOMMU >> binding. >> See ../iommu/iommu.txt for details. >> >> -Example: >> --------- >> +The node should contain a "timings" subnode for each supported RAM type >> (see >> +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address >> being its >> +RAM_CODE. >> >> +Required properties for "timings" nodes : >> +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set >> is used >> +for. >> + >> +Each "timings" node should contain a "timing" subnode for every supported >> EMC >> +clock rate. The "timing" subnodes should have the clock rate in Hz as >> their unit >> +address. > > > In patch 04, a similar sub-node is named "emc-timings". Shouldn't the same > name be used here for consistency? Yeah, agreed. > Also, it seems like there is a need for timing nodes in the MC to have match > timing nodes in the CAR. It would be nice to add that information in all > related bindings files. Well, rather than the timing subnodes in a node having to match the ones in another nodes, I think that all of them should match the frequencies at which the EMC can run, which I think is clear enough like this (already in each of the three bindings): +Each "timings" node should contain a "timing" subnode for every supported EMC clock rate. >> + >> +Required properties for "timing" nodes : >> +- clock-frequency : Should contain the memory clock rate in Hz. >> +- nvidia,emem-configuration : Values to be written to the EMEM register >> block, >> +as specified by the board documentation. > > > Could you add some more information about which range of registers we are > talking about, and whether they must all be specified or only part of them? > > >> + >> +Example SoC include file: >> + >> +/ { >> mc: memory-controller@0,70019000 { >> compatible = "nvidia,tegra124-mc"; >> reg = <0x0 0x70019000 0x0 0x1000>; >> @@ -34,3 +51,28 @@ Example: >> ... >> iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; >> }; >> +}; >> + >> +Example board file: >> + >> +/ { >> + memory-controller@0,70019000 { >> + timings@3 { >> + nvidia,ram-code = <3>; >> + >> + timing@12750000 { >> + clock-frequency = <12750000>; >> + >> + nvidia,emem-configuration = < >> + 0x40040001 /* MC_EMEM_ARB_CFG */ >> + 0x8000000a /* >> MC_EMEM_ARB_OUTSTANDING_REQ */ >> + 0x00000001 /* >> MC_EMEM_ARB_TIMING_RCD */ >> + 0x00000001 /* >> MC_EMEM_ARB_TIMING_RP */ >> + 0x00000002 /* >> MC_EMEM_ARB_TIMING_RC */ >> + 0x00000000 /* >> MC_EMEM_ARB_TIMING_RAS */ >> + 0x00000002 /* >> MC_EMEM_ARB_TIMING_FAW */ >> + >; > > > Looking at the actual board files I suppose this example here is incomplete. > It would be nice to make this explicit, maybe by adding "..." on a new line > to indicate more registers are expected. Sounds good. Thanks! Tomeu > -- > To unsubscribe from this list: send the line "unsubscribe linux-tegra" in > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 06/13] of: Add Tegra124 EMC bindings 2014-10-29 16:22 [PATCH v3 00/13] Tegra124 EMC (external memory controller) support Tomeu Vizoso ` (2 preceding siblings ...) 2014-10-29 16:22 ` [PATCH v3 05/13] of: Document timings subnode of nvidia,tegra-mc Tomeu Vizoso @ 2014-10-29 16:22 ` Tomeu Vizoso 2014-10-29 16:22 ` [PATCH v3 07/13] ARM: tegra: Add EMC to Tegra124 device tree Tomeu Vizoso ` (2 subsequent siblings) 6 siblings, 0 replies; 23+ messages in thread From: Tomeu Vizoso @ 2014-10-29 16:22 UTC (permalink / raw) To: linux-tegra Cc: Javier Martinez Canillas, Mikko Perttunen, Tomeu Vizoso, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree, linux-kernel From: Mikko Perttunen <mperttunen@nvidia.com> Add binding documentation for the nvidia,tegra124-emc device tree node. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- v2: * Specify the unit addresses for the timings and timing nodes --- .../bindings/memory-controllers/tegra-emc.txt | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt new file mode 100644 index 0000000..fe64d57 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt @@ -0,0 +1,118 @@ +NVIDIA Tegra124 SoC EMC (external memory controller) +==================================================== + +Required properties : +- compatible : Should be "nvidia,tegra124-emc". +- reg : physical base address and length of the controller's registers. +- nvidia,memory-controller : phandle of the MC driver. + +The node should contain a "timings" subnode for each supported RAM type (see +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address being its +RAM_CODE. + +Required properties for "timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used +for. + +Each "timings" node should contain a "timing" subnode for every supported EMC +clock rate. The "timing" subnodes should have the clock rate in Hz as their unit +address. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- The following properties contain EMC timing characterization values (specified +in the board documentation) : + - nvidia,emc-zcal-cnt-long + - nvidia,emc-auto-cal-interval + - nvidia,emc-ctt-term-ctrl + - nvidia,emc-cfg + - nvidia,emc-cfg-2 + - nvidia,emc-sel-dpd-ctrl + - nvidia,emc-cfg-dig-dll + - nvidia,emc-bgbias-ctl0 + - nvidia,emc-auto-cal-config + - nvidia,emc-auto-cal-config2 + - nvidia,emc-auto-cal-config3 + - nvidia,emc-mode-reset + - nvidia,emc-mode-1 + - nvidia,emc-mode-2 + - nvidia,emc-mode-4 +- nvidia,emc-configuration : EMC timing characterization data to be written to +the EMC registers, as specified by the board documentation. + +Example SoC include file: + +/ { + emc@0,7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + + nvidia,memory-controller = <&mc>; + }; +}; + +Example board file: + +/ { + emc@0,7001b000 { + timings@3 { + nvidia,ram-code = <3>; + + timing@12750000 { + clock-frequency = <12750000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + >; + }; + + timing@20400000 { + clock-frequency = <20400000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + >; + }; + }; + }; +}; -- 1.9.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 07/13] ARM: tegra: Add EMC to Tegra124 device tree 2014-10-29 16:22 [PATCH v3 00/13] Tegra124 EMC (external memory controller) support Tomeu Vizoso ` (3 preceding siblings ...) 2014-10-29 16:22 ` [PATCH v3 06/13] of: Add Tegra124 EMC bindings Tomeu Vizoso @ 2014-10-29 16:22 ` Tomeu Vizoso 2014-10-29 16:22 ` [PATCH v3 08/13] ARM: tegra: Add EMC timings to Jetson TK1 " Tomeu Vizoso 2014-10-29 16:22 ` [PATCH v3 10/13] memory: tegra: Add EMC (external memory controller) driver Tomeu Vizoso 6 siblings, 0 replies; 23+ messages in thread From: Tomeu Vizoso @ 2014-10-29 16:22 UTC (permalink / raw) To: linux-tegra Cc: Javier Martinez Canillas, Mikko Perttunen, Tomeu Vizoso, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree, linux-arm-kernel, linux-kernel From: Mikko Perttunen <mperttunen@nvidia.com> This adds a node for the EMC memory controller. It is always enabled, but only provides read-only functionality without board-specific timing tables. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- arch/arm/boot/dts/tegra124.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 0ee30f6..97c9f8b 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -567,6 +567,13 @@ #iommu-cells = <1>; }; + emc@0,7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + + nvidia,memory-controller = <&mc>; + }; + sata@0,70020000 { compatible = "nvidia,tegra124-ahci"; -- 1.9.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 08/13] ARM: tegra: Add EMC timings to Jetson TK1 device tree 2014-10-29 16:22 [PATCH v3 00/13] Tegra124 EMC (external memory controller) support Tomeu Vizoso ` (4 preceding siblings ...) 2014-10-29 16:22 ` [PATCH v3 07/13] ARM: tegra: Add EMC to Tegra124 device tree Tomeu Vizoso @ 2014-10-29 16:22 ` Tomeu Vizoso [not found] ` <1414599796-30597-9-git-send-email-tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> 2014-10-29 16:22 ` [PATCH v3 10/13] memory: tegra: Add EMC (external memory controller) driver Tomeu Vizoso 6 siblings, 1 reply; 23+ messages in thread From: Tomeu Vizoso @ 2014-10-29 16:22 UTC (permalink / raw) To: linux-tegra Cc: Mark Rutland, Alexandre Courbot, Russell King, Tomeu Vizoso, Pawel Moll, Ian Campbell, Stephen Warren, linux-kernel, Mikko Perttunen, devicetree, Rob Herring, Thierry Reding, Kumar Gala, Javier Martinez Canillas, linux-arm-kernel From: Mikko Perttunen <mperttunen@nvidia.com> This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains valid timings for the EMC memory clock. The file is included to the main Jetson TK1 device tree. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- v2: * Fix the unit addresses of the timings and timing nodes --- arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2412 ++++++++++++++++++++++++ arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 + 2 files changed, 2414 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi new file mode 100644 index 0000000..f1f391a --- /dev/null +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -0,0 +1,2412 @@ +/ { + clock@0,60006000 { + emc-timings@3 { + nvidia,ram-code = <3>; + + timing@12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing@20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing@40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing@68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing@102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing@204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing@300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing@396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + timing@528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing@600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing@792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing@924000000 { + clock-frequency = <924000000>; + nvidia,parent-clock-frequency = <924000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + emc@0,7001b000 { + timings@3 { + nvidia,ram-code = <3>; + + timing@12750000 { + clock-frequency = <12750000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x0130b118 /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing@20400000 { + clock-frequency = <20400000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x0130b118 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000042 + 0x000e000e + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + timing@2 { + clock-frequency = <40800000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x0130b118 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000000 + 0x00000042 + 0x000e000e + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + timing@3 { + clock-frequency = <68000000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x0130b118 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000000 + 0x00000042 + 0x000e000e + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + timing@4 { + clock-frequency = <102000000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x0130b118 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000000 + 0x00000042 + 0x000e000e + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + timing@204000000 { + clock-frequency = <204000000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000006 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000007 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00008000 + 0x00000000 + 0x00000000 + 0x00008000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x0130b118 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000707 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00020000 + 0x00000100 + 0x000e000e + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + timing@300000000 { + clock-frequency = <300000000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004d + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004b + 0x0000000e + 0x00000052 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000009 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x01231339 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00020000 + 0x00000100 + 0x0173000e + 0x0173000e + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + timing@396000000 { + clock-frequency = <396000000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-cfg-dig-dll = <0x002c0068>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000011 + 0x00000066 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006c + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000d + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00003800 + 0x00003800 + 0x00003800 + 0x00003800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x01231339 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00020000 + 0x00000100 + 0x015b000e + 0x015b000e + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + timing@528000000 { + clock-frequency = <528000000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-cfg-dig-dll = <0xe0120069>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000018 + 0x00000088 + 0x00000000 + 0x00000010 + 0x00000006 + 0x00000006 + 0x00000009 + 0x00000002 + 0x0000000d + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000009 + 0x00030000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000010 + 0x00000012 + 0x00000014 + 0x00000fd6 + 0x00000000 + 0x000003f5 + 0x00000002 + 0x0000000b + 0x00000001 + 0x00000000 + 0x00000085 + 0x00000012 + 0x00000090 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000013 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001017 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe01200b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00054000 + 0x00054000 + 0x00000000 + 0x00054000 + 0x00054000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x0123133d + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00020000 + 0x00000100 + 0x0139000e + 0x0139000e + 0x00000000 + 0x00000003 + 0x000042a0 + 0x80002062 + 0x0000000a + >; + }; + timing@600000000 { + clock-frequency = <600000000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-cfg-dig-dll = <0xe00e0069>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x0000001b + 0x0000009b + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000097 + 0x00000015 + 0x000000a3 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000015 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x100002a0 + 0x00000000 + 0x00111111 + 0x0121113d + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00020000 + 0x00000100 + 0x0127000e + 0x0127000e + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024a9 + 0x0000000e + >; + }; + timing@792000000 { + clock-frequency = <792000000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-cfg-dig-dll = <0xe0070069>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000024 + 0x000000cd + 0x00000000 + 0x00000019 + 0x0000000a + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x0000000a + 0x0000000a + 0x00000003 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c7 + 0x00000018 + 0x000000d7 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x0000001d + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x100002a0 + 0x00000000 + 0x00111111 + 0x0120113d + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00514514 + 0x00514514 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00020000 + 0x00000100 + 0x00f7000e + 0x00f7000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + timing@924000000 { + clock-frequency = <924000000>; + + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-cfg-dig-dll = <0xe0040069>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-auto-cal-config = <0x00000000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0xa1430303>; + nvidia,emc-mode-reset = <0x80000f15>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x0000002b + 0x000000f0 + 0x00000000 + 0x0000001e + 0x0000000b + 0x00000009 + 0x0000000f + 0x00000005 + 0x00000016 + 0x0000000b + 0x0000000b + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000007 + 0x00000007 + 0x0000000d + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000f + 0x000a0000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000016 + 0x0000001a + 0x0000001c + 0x00001be7 + 0x00000000 + 0x000006f9 + 0x00000004 + 0x00000015 + 0x00000001 + 0x00000000 + 0x000000e7 + 0x0000001b + 0x000000fb + 0x00000200 + 0x00000006 + 0x00000007 + 0x00000006 + 0x00000022 + 0x00000000 + 0x0000000a + 0x0000000a + 0x00001c28 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab898 + 0xe00400b1 + 0x00008000 + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x100002a0 + 0x00000000 + 0x00111111 + 0x0120113d + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x5d75d720 + 0x00514514 + 0x00514514 + 0x5d75d700 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00020000 + 0x00000128 + 0x00cd000e + 0x00cd000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x800037ea + 0x00000011 + >; + }; + }; + }; + + memory-controller@0,70019000 { + timings@3 { + nvidia,ram-code = <3>; + + timing@12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing@20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + timing@40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + timing@68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + timing@102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + timing@204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000004 + 0x00000002 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0404 + 0x73840a05 + 0x70000f03 + 0x001f0000 + >; + }; + timing@300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + timing@396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + timing@528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000007 + 0x0000000a + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090c + 0x7428180d + 0x70000f03 + 0x001f0000 + >; + }; + timing@600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + timing@792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00170e13 + 0x736c2414 + 0x70000f02 + 0x001f0000 + >; + }; + timing@924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d + 0x80000040 + 0x00000005 + 0x00000006 + 0x00000016 + 0x0000000e + 0x00000011 + 0x00000002 + 0x00000004 + 0x0000000e + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000009 + 0x09060202 + 0x001a1016 + 0x734e2a17 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 029c9a02..96de17e 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -3,6 +3,8 @@ #include <dt-bindings/input/input.h> #include "tegra124.dtsi" +#include "tegra124-jetson-tk1-emc.dtsi" + / { model = "NVIDIA Tegra124 Jetson TK1"; compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; -- 1.9.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
[parent not found: <1414599796-30597-9-git-send-email-tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>]
* Re: [PATCH v3 08/13] ARM: tegra: Add EMC timings to Jetson TK1 device tree [not found] ` <1414599796-30597-9-git-send-email-tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> @ 2014-11-06 12:21 ` Nikolaus Schulz [not found] ` <20141106122149.GC3863-GNrqntRiisjPWV3K8zbkiAH8Oo8bv1DvZkel5v8DVj8@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Nikolaus Schulz @ 2014-11-06 12:21 UTC (permalink / raw) To: Tomeu Vizoso Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, Javier Martinez Canillas, Mikko Perttunen, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, Oct 29, 2014 at 05:22:26PM +0100, Tomeu Vizoso wrote: > From: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains > valid timings for the EMC memory clock. The file is included to the > main Jetson TK1 device tree. > > Signed-off-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > Signed-off-by: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> > > --- > > v2: * Fix the unit addresses of the timings and timing nodes This is not completely fixed yet, see FIXMEs below. > --- > arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2412 ++++++++++++++++++++++++ > arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 + > 2 files changed, 2414 insertions(+) > create mode 100644 arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi > > diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi > new file mode 100644 > index 0000000..f1f391a > --- /dev/null > +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi > @@ -0,0 +1,2412 @@ > +/ { > + clock@0,60006000 { > + emc-timings@3 { > + nvidia,ram-code = <3>; > + > + timing@12750000 { > + clock-frequency = <12750000>; > + nvidia,parent-clock-frequency = <408000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; > + clock-names = "emc-parent"; > + }; > + timing@20400000 { > + clock-frequency = <20400000>; > + nvidia,parent-clock-frequency = <408000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; > + clock-names = "emc-parent"; > + }; > + timing@40800000 { > + clock-frequency = <40800000>; > + nvidia,parent-clock-frequency = <408000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; > + clock-names = "emc-parent"; > + }; > + timing@68000000 { > + clock-frequency = <68000000>; > + nvidia,parent-clock-frequency = <408000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; > + clock-names = "emc-parent"; > + }; > + timing@102000000 { > + clock-frequency = <102000000>; > + nvidia,parent-clock-frequency = <408000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; > + clock-names = "emc-parent"; > + }; > + timing@204000000 { > + clock-frequency = <204000000>; > + nvidia,parent-clock-frequency = <408000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; > + clock-names = "emc-parent"; > + }; > + timing@300000000 { > + clock-frequency = <300000000>; > + nvidia,parent-clock-frequency = <600000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; > + clock-names = "emc-parent"; > + }; > + timing@396000000 { > + clock-frequency = <396000000>; > + nvidia,parent-clock-frequency = <792000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; > + clock-names = "emc-parent"; > + }; > + timing@528000000 { > + clock-frequency = <528000000>; > + nvidia,parent-clock-frequency = <528000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; > + clock-names = "emc-parent"; > + }; > + timing@600000000 { > + clock-frequency = <600000000>; > + nvidia,parent-clock-frequency = <600000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; > + clock-names = "emc-parent"; > + }; > + timing@792000000 { > + clock-frequency = <792000000>; > + nvidia,parent-clock-frequency = <792000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; > + clock-names = "emc-parent"; > + }; > + timing@924000000 { > + clock-frequency = <924000000>; > + nvidia,parent-clock-frequency = <924000000>; > + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; > + clock-names = "emc-parent"; > + }; > + }; > + }; > + > + emc@0,7001b000 { > + timings@3 { > + nvidia,ram-code = <3>; > + > + timing@12750000 { > + clock-frequency = <12750000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73240000>; > + nvidia,emc-cfg-2 = <0x000008c5>; > + nvidia,emc-sel-dpd-ctrl = <0x00040128>; > + nvidia,emc-cfg-dig-dll = <0x002c0068>; > + nvidia,emc-bgbias-ctl0 = <0x00000008>; > + nvidia,emc-auto-cal-config = <0xa1430000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0x00000000>; > + nvidia,emc-mode-reset = <0x80001221>; > + nvidia,emc-mode-1 = <0x80100003>; > + nvidia,emc-mode-2 = <0x80200008>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000000 /* EMC_RC */ > + 0x00000003 /* EMC_RFC */ > + 0x00000000 /* EMC_RFC_SLR */ > + 0x00000000 /* EMC_RAS */ > + 0x00000000 /* EMC_RP */ > + 0x00000004 /* EMC_R2W */ > + 0x0000000a /* EMC_W2R */ > + 0x00000003 /* EMC_R2P */ > + 0x0000000b /* EMC_W2P */ > + 0x00000000 /* EMC_RD_RCD */ > + 0x00000000 /* EMC_WR_RCD */ > + 0x00000003 /* EMC_RRD */ > + 0x00000003 /* EMC_REXT */ > + 0x00000000 /* EMC_WEXT */ > + 0x00000006 /* EMC_WDV */ > + 0x00000006 /* EMC_WDV_MASK */ > + 0x00000006 /* EMC_QUSE */ > + 0x00000002 /* EMC_QUSE_WIDTH */ > + 0x00000000 /* EMC_IBDLY */ > + 0x00000005 /* EMC_EINPUT */ > + 0x00000005 /* EMC_EINPUT_DURATION */ > + 0x00010000 /* EMC_PUTERM_EXTRA */ > + 0x00000003 /* EMC_PUTERM_WIDTH */ > + 0x00000000 /* EMC_PUTERM_ADJ */ > + 0x00000000 /* EMC_CDB_CNTL_1 */ > + 0x00000000 /* EMC_CDB_CNTL_2 */ > + 0x00000000 /* EMC_CDB_CNTL_3 */ > + 0x00000004 /* EMC_QRST */ > + 0x0000000c /* EMC_QSAFE */ > + 0x0000000d /* EMC_RDV */ > + 0x0000000f /* EMC_RDV_MASK */ > + 0x00000060 /* EMC_REFRESH */ > + 0x00000000 /* EMC_BURST_REFRESH_NUM */ > + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ > + 0x00000002 /* EMC_PDEX2WR */ > + 0x00000002 /* EMC_PDEX2RD */ > + 0x00000001 /* EMC_PCHG2PDEN */ > + 0x00000000 /* EMC_ACT2PDEN */ > + 0x00000007 /* EMC_AR2PDEN */ > + 0x0000000f /* EMC_RW2PDEN */ > + 0x00000005 /* EMC_TXSR */ > + 0x00000005 /* EMC_TXSRDLL */ > + 0x00000004 /* EMC_TCKE */ > + 0x00000005 /* EMC_TCKESR */ > + 0x00000004 /* EMC_TPD */ > + 0x00000000 /* EMC_TFAW */ > + 0x00000000 /* EMC_TRPAB */ > + 0x00000005 /* EMC_TCLKSTABLE */ > + 0x00000005 /* EMC_TCLKSTOP */ > + 0x00000064 /* EMC_TREFBW */ > + 0x00000000 /* EMC_FBIO_CFG6 */ > + 0x00000000 /* EMC_ODT_WRITE */ > + 0x00000000 /* EMC_ODT_READ */ > + 0x106aa298 /* EMC_FBIO_CFG5 */ > + 0x002c00a0 /* EMC_CFG_DIG_DLL */ > + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ > + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ > + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ > + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ > + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ > + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ > + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ > + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ > + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ > + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ > + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ > + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ > + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ > + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ > + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ > + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ > + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ > + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ > + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ > + 0x10000280 /* EMC_XM2CMDPADCTRL */ > + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ > + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ > + 0x0130b118 /* EMC_XM2DQSPADCTRL2 */ > + 0x00000000 /* EMC_XM2DQPADCTRL2 */ > + 0x00000000 /* EMC_XM2DQPADCTRL3 */ > + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ > + 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ > + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ > + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ > + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ > + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ > + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ > + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ > + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ > + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ > + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ > + 0x00000007 /* EMC_TXDSRVTTGEN */ > + 0x00000000 /* EMC_FBIO_SPARE */ > + 0x00000000 /* EMC_ZCAL_INTERVAL */ > + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ > + 0x000e000e /* EMC_MRS_WAIT_CNT */ > + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ > + 0x00000000 /* EMC_CTT */ > + 0x00000003 /* EMC_CTT_DURATION */ > + 0x0000f2f3 /* EMC_CFG_PIPE */ > + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ > + 0x0000000a /* EMC_QPOP */ > + >; > + }; > + > + timing@20400000 { > + clock-frequency = <20400000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73240000>; > + nvidia,emc-cfg-2 = <0x000008c5>; > + nvidia,emc-sel-dpd-ctrl = <0x00040128>; > + nvidia,emc-cfg-dig-dll = <0x002c0068>; > + nvidia,emc-bgbias-ctl0 = <0x00000008>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80001221>; > + nvidia,emc-mode-1 = <0x80100003>; > + nvidia,emc-mode-2 = <0x80200008>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000000 > + 0x00000005 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000004 > + 0x0000000a > + 0x00000003 > + 0x0000000b > + 0x00000000 > + 0x00000000 > + 0x00000003 > + 0x00000003 > + 0x00000000 > + 0x00000006 > + 0x00000006 > + 0x00000006 > + 0x00000002 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00010000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000004 > + 0x0000000c > + 0x0000000d > + 0x0000000f > + 0x0000009a > + 0x00000000 > + 0x00000026 > + 0x00000002 > + 0x00000002 > + 0x00000001 > + 0x00000000 > + 0x00000007 > + 0x0000000f > + 0x00000006 > + 0x00000006 > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x00000000 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x000000a0 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x106aa298 > + 0x002c00a0 > + 0x00008000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x000fc000 > + 0x000fc000 > + 0x000fc000 > + 0x000fc000 > + 0x0000fc00 > + 0x0000fc00 > + 0x0000fc00 > + 0x0000fc00 > + 0x10000280 > + 0x00000000 > + 0x00111111 > + 0x0130b118 > + 0x00000000 > + 0x00000000 > + 0x77ffc081 > + 0x00000e0e > + 0x81f1f108 > + 0x07070004 > + 0x0000003f > + 0x016eeeee > + 0x51451400 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0000003f > + 0x0000000b > + 0x00000000 > + 0x00000000 > + 0x00000042 > + 0x000e000e > + 0x000e000e > + 0x00000000 > + 0x00000003 > + 0x0000f2f3 > + 0x8000023a > + 0x0000000a > + >; > + }; > + timing@2 { FIXME: this should be timing@40800000 > + clock-frequency = <40800000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73240000>; > + nvidia,emc-cfg-2 = <0x000008c5>; > + nvidia,emc-sel-dpd-ctrl = <0x00040128>; > + nvidia,emc-cfg-dig-dll = <0x002c0068>; > + nvidia,emc-bgbias-ctl0 = <0x00000008>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80001221>; > + nvidia,emc-mode-1 = <0x80100003>; > + nvidia,emc-mode-2 = <0x80200008>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000001 > + 0x0000000a > + 0x00000000 > + 0x00000001 > + 0x00000000 > + 0x00000004 > + 0x0000000a > + 0x00000003 > + 0x0000000b > + 0x00000000 > + 0x00000000 > + 0x00000003 > + 0x00000003 > + 0x00000000 > + 0x00000006 > + 0x00000006 > + 0x00000006 > + 0x00000002 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00010000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000004 > + 0x0000000c > + 0x0000000d > + 0x0000000f > + 0x00000134 > + 0x00000000 > + 0x0000004d > + 0x00000002 > + 0x00000002 > + 0x00000001 > + 0x00000000 > + 0x00000008 > + 0x0000000f > + 0x0000000c > + 0x0000000c > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x00000000 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x0000013f > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x106aa298 > + 0x002c00a0 > + 0x00008000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x000fc000 > + 0x000fc000 > + 0x000fc000 > + 0x000fc000 > + 0x0000fc00 > + 0x0000fc00 > + 0x0000fc00 > + 0x0000fc00 > + 0x10000280 > + 0x00000000 > + 0x00111111 > + 0x0130b118 > + 0x00000000 > + 0x00000000 > + 0x77ffc081 > + 0x00000e0e > + 0x81f1f108 > + 0x07070004 > + 0x0000003f > + 0x016eeeee > + 0x51451400 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0000003f > + 0x00000015 > + 0x00000000 > + 0x00000000 > + 0x00000042 > + 0x000e000e > + 0x000e000e > + 0x00000000 > + 0x00000003 > + 0x0000f2f3 > + 0x80000370 > + 0x0000000a > + >; > + }; > + timing@3 { FIXME: should be timing@68000000 > + clock-frequency = <68000000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73240000>; > + nvidia,emc-cfg-2 = <0x000008c5>; > + nvidia,emc-sel-dpd-ctrl = <0x00040128>; > + nvidia,emc-cfg-dig-dll = <0x002c0068>; > + nvidia,emc-bgbias-ctl0 = <0x00000008>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80001221>; > + nvidia,emc-mode-1 = <0x80100003>; > + nvidia,emc-mode-2 = <0x80200008>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000003 > + 0x00000011 > + 0x00000000 > + 0x00000002 > + 0x00000000 > + 0x00000004 > + 0x0000000a > + 0x00000003 > + 0x0000000b > + 0x00000000 > + 0x00000000 > + 0x00000003 > + 0x00000003 > + 0x00000000 > + 0x00000006 > + 0x00000006 > + 0x00000006 > + 0x00000002 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00010000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000004 > + 0x0000000c > + 0x0000000d > + 0x0000000f > + 0x00000202 > + 0x00000000 > + 0x00000080 > + 0x00000002 > + 0x00000002 > + 0x00000001 > + 0x00000000 > + 0x0000000f > + 0x0000000f > + 0x00000013 > + 0x00000013 > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x00000001 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00000213 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x106aa298 > + 0x002c00a0 > + 0x00008000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x000fc000 > + 0x000fc000 > + 0x000fc000 > + 0x000fc000 > + 0x0000fc00 > + 0x0000fc00 > + 0x0000fc00 > + 0x0000fc00 > + 0x10000280 > + 0x00000000 > + 0x00111111 > + 0x0130b118 > + 0x00000000 > + 0x00000000 > + 0x77ffc081 > + 0x00000e0e > + 0x81f1f108 > + 0x07070004 > + 0x0000003f > + 0x016eeeee > + 0x51451400 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0000003f > + 0x00000022 > + 0x00000000 > + 0x00000000 > + 0x00000042 > + 0x000e000e > + 0x000e000e > + 0x00000000 > + 0x00000003 > + 0x0000f2f3 > + 0x8000050e > + 0x0000000a > + >; > + }; > + timing@4 { FIXME: timing@102000000 > + clock-frequency = <102000000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73240000>; > + nvidia,emc-cfg-2 = <0x000008c5>; > + nvidia,emc-sel-dpd-ctrl = <0x00040128>; > + nvidia,emc-cfg-dig-dll = <0x002c0068>; > + nvidia,emc-bgbias-ctl0 = <0x00000008>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80001221>; > + nvidia,emc-mode-1 = <0x80100003>; > + nvidia,emc-mode-2 = <0x80200008>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000004 > + 0x0000001a > + 0x00000000 > + 0x00000003 > + 0x00000001 > + 0x00000004 > + 0x0000000a > + 0x00000003 > + 0x0000000b > + 0x00000001 > + 0x00000001 > + 0x00000003 > + 0x00000003 > + 0x00000000 > + 0x00000006 > + 0x00000006 > + 0x00000006 > + 0x00000002 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00010000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000004 > + 0x0000000c > + 0x0000000d > + 0x0000000f > + 0x00000304 > + 0x00000000 > + 0x000000c1 > + 0x00000002 > + 0x00000002 > + 0x00000001 > + 0x00000000 > + 0x00000018 > + 0x0000000f > + 0x0000001c > + 0x0000001c > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x00000003 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x0000031c > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x106aa298 > + 0x002c00a0 > + 0x00008000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x000fc000 > + 0x000fc000 > + 0x000fc000 > + 0x000fc000 > + 0x0000fc00 > + 0x0000fc00 > + 0x0000fc00 > + 0x0000fc00 > + 0x10000280 > + 0x00000000 > + 0x00111111 > + 0x0130b118 > + 0x00000000 > + 0x00000000 > + 0x77ffc081 > + 0x00000e0e > + 0x81f1f108 > + 0x07070004 > + 0x0000003f > + 0x016eeeee > + 0x51451400 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0000003f > + 0x00000033 > + 0x00000000 > + 0x00000000 > + 0x00000042 > + 0x000e000e > + 0x000e000e > + 0x00000000 > + 0x00000003 > + 0x0000f2f3 > + 0x80000713 > + 0x0000000a > + >; > + }; > + timing@204000000 { > + clock-frequency = <204000000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73240000>; > + nvidia,emc-cfg-2 = <0x0000088d>; > + nvidia,emc-sel-dpd-ctrl = <0x00040008>; > + nvidia,emc-cfg-dig-dll = <0x002c0068>; > + nvidia,emc-bgbias-ctl0 = <0x00000008>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80001221>; > + nvidia,emc-mode-1 = <0x80100003>; > + nvidia,emc-mode-2 = <0x80200008>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000009 > + 0x00000035 > + 0x00000000 > + 0x00000006 > + 0x00000002 > + 0x00000005 > + 0x0000000a > + 0x00000003 > + 0x0000000b > + 0x00000002 > + 0x00000002 > + 0x00000003 > + 0x00000003 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00000006 > + 0x00000002 > + 0x00000000 > + 0x00000004 > + 0x00000006 > + 0x00010000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000003 > + 0x0000000d > + 0x0000000f > + 0x00000011 > + 0x00000607 > + 0x00000000 > + 0x00000181 > + 0x00000002 > + 0x00000002 > + 0x00000001 > + 0x00000000 > + 0x00000032 > + 0x0000000f > + 0x00000038 > + 0x00000038 > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x00000007 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00000638 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x106aa298 > + 0x002c00a0 > + 0x00008000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00064000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00008000 > + 0x00000000 > + 0x00000000 > + 0x00008000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00090000 > + 0x00090000 > + 0x00090000 > + 0x00090000 > + 0x00009000 > + 0x00009000 > + 0x00009000 > + 0x00009000 > + 0x10000280 > + 0x00000000 > + 0x00111111 > + 0x0130b118 > + 0x00000000 > + 0x00000000 > + 0x77ffc081 > + 0x00000707 > + 0x81f1f108 > + 0x07070004 > + 0x0000003f > + 0x016eeeee > + 0x51451400 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0000003f > + 0x00000066 > + 0x00000000 > + 0x00020000 > + 0x00000100 > + 0x000e000e > + 0x000e000e > + 0x00000000 > + 0x00000003 > + 0x0000d2b3 > + 0x80000d22 > + 0x0000000a > + >; > + }; > + timing@300000000 { > + clock-frequency = <300000000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73340000>; > + nvidia,emc-cfg-2 = <0x000008d5>; > + nvidia,emc-sel-dpd-ctrl = <0x00040128>; > + nvidia,emc-cfg-dig-dll = <0x002c0068>; > + nvidia,emc-bgbias-ctl0 = <0x00000000>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80000321>; > + nvidia,emc-mode-1 = <0x80100002>; > + nvidia,emc-mode-2 = <0x80200000>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x0000000d > + 0x0000004d > + 0x00000000 > + 0x00000009 > + 0x00000003 > + 0x00000004 > + 0x00000008 > + 0x00000002 > + 0x00000009 > + 0x00000003 > + 0x00000003 > + 0x00000002 > + 0x00000002 > + 0x00000000 > + 0x00000003 > + 0x00000003 > + 0x00000005 > + 0x00000002 > + 0x00000000 > + 0x00000002 > + 0x00000007 > + 0x00020000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000001 > + 0x0000000e > + 0x00000010 > + 0x00000012 > + 0x000008e4 > + 0x00000000 > + 0x00000239 > + 0x00000001 > + 0x00000008 > + 0x00000001 > + 0x00000000 > + 0x0000004b > + 0x0000000e > + 0x00000052 > + 0x00000200 > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x00000009 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00000924 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x104ab098 > + 0x002c00a0 > + 0x00008000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00098000 > + 0x00098000 > + 0x00000000 > + 0x00098000 > + 0x00098000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00060000 > + 0x00060000 > + 0x00060000 > + 0x00060000 > + 0x00006000 > + 0x00006000 > + 0x00006000 > + 0x00006000 > + 0x10000280 > + 0x00000000 > + 0x00111111 > + 0x01231339 > + 0x00000000 > + 0x00000000 > + 0x77ffc081 > + 0x00000505 > + 0x81f1f108 > + 0x07070004 > + 0x00000000 > + 0x016eeeee > + 0x51451420 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0000003f > + 0x00000096 > + 0x00000000 > + 0x00020000 > + 0x00000100 > + 0x0173000e > + 0x0173000e > + 0x00000000 > + 0x00000003 > + 0x000052a3 > + 0x800012d7 > + 0x00000009 > + >; > + }; > + timing@396000000 { > + clock-frequency = <396000000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73340000>; > + nvidia,emc-cfg-2 = <0x00000895>; > + nvidia,emc-sel-dpd-ctrl = <0x00040008>; > + nvidia,emc-cfg-dig-dll = <0x002c0068>; > + nvidia,emc-bgbias-ctl0 = <0x00000000>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80000521>; > + nvidia,emc-mode-1 = <0x80100002>; > + nvidia,emc-mode-2 = <0x80200000>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000011 > + 0x00000066 > + 0x00000000 > + 0x0000000c > + 0x00000004 > + 0x00000004 > + 0x00000008 > + 0x00000002 > + 0x0000000a > + 0x00000004 > + 0x00000004 > + 0x00000002 > + 0x00000002 > + 0x00000000 > + 0x00000003 > + 0x00000003 > + 0x00000005 > + 0x00000002 > + 0x00000000 > + 0x00000001 > + 0x00000008 > + 0x00020000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x0000000f > + 0x00000010 > + 0x00000012 > + 0x00000bd1 > + 0x00000000 > + 0x000002f4 > + 0x00000001 > + 0x00000008 > + 0x00000001 > + 0x00000000 > + 0x00000063 > + 0x0000000f > + 0x0000006c > + 0x00000200 > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x0000000d > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00000c11 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x104ab098 > + 0x002c00a0 > + 0x00008000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00030000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00070000 > + 0x00070000 > + 0x00000000 > + 0x00070000 > + 0x00070000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00038000 > + 0x00038000 > + 0x00038000 > + 0x00038000 > + 0x00003800 > + 0x00003800 > + 0x00003800 > + 0x00003800 > + 0x10000280 > + 0x00000000 > + 0x00111111 > + 0x01231339 > + 0x00000000 > + 0x00000000 > + 0x77ffc081 > + 0x00000505 > + 0x81f1f108 > + 0x07070004 > + 0x00000000 > + 0x016eeeee > + 0x51451420 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0000003f > + 0x000000c6 > + 0x00000000 > + 0x00020000 > + 0x00000100 > + 0x015b000e > + 0x015b000e > + 0x00000000 > + 0x00000003 > + 0x000052a3 > + 0x8000188b > + 0x00000009 > + >; > + }; > + timing@528000000 { > + clock-frequency = <528000000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73300000>; > + nvidia,emc-cfg-2 = <0x0000089d>; > + nvidia,emc-sel-dpd-ctrl = <0x00040008>; > + nvidia,emc-cfg-dig-dll = <0xe0120069>; > + nvidia,emc-bgbias-ctl0 = <0x00000000>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80000941>; > + nvidia,emc-mode-1 = <0x80100002>; > + nvidia,emc-mode-2 = <0x80200008>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000018 > + 0x00000088 > + 0x00000000 > + 0x00000010 > + 0x00000006 > + 0x00000006 > + 0x00000009 > + 0x00000002 > + 0x0000000d > + 0x00000006 > + 0x00000006 > + 0x00000002 > + 0x00000002 > + 0x00000000 > + 0x00000003 > + 0x00000003 > + 0x00000006 > + 0x00000002 > + 0x00000000 > + 0x00000001 > + 0x00000009 > + 0x00030000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000010 > + 0x00000012 > + 0x00000014 > + 0x00000fd6 > + 0x00000000 > + 0x000003f5 > + 0x00000002 > + 0x0000000b > + 0x00000001 > + 0x00000000 > + 0x00000085 > + 0x00000012 > + 0x00000090 > + 0x00000200 > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x00000013 > + 0x00000000 > + 0x00000006 > + 0x00000006 > + 0x00001017 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x104ab098 > + 0xe01200b1 > + 0x00008000 > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00054000 > + 0x00054000 > + 0x00000000 > + 0x00054000 > + 0x00054000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x0000000e > + 0x0000000e > + 0x0000000e > + 0x0000000e > + 0x0000000e > + 0x0000000e > + 0x0000000e > + 0x0000000e > + 0x100002a0 > + 0x00000000 > + 0x00111111 > + 0x0123133d > + 0x00000000 > + 0x00000000 > + 0x77ffc085 > + 0x00000505 > + 0x81f1f108 > + 0x07070004 > + 0x00000000 > + 0x016eeeee > + 0x51451420 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0606003f > + 0x00000000 > + 0x00000000 > + 0x00020000 > + 0x00000100 > + 0x0139000e > + 0x0139000e > + 0x00000000 > + 0x00000003 > + 0x000042a0 > + 0x80002062 > + 0x0000000a > + >; > + }; > + timing@600000000 { > + clock-frequency = <600000000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73300000>; > + nvidia,emc-cfg-2 = <0x0000089d>; > + nvidia,emc-sel-dpd-ctrl = <0x00040008>; > + nvidia,emc-cfg-dig-dll = <0xe00e0069>; > + nvidia,emc-bgbias-ctl0 = <0x00000000>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80000b61>; > + nvidia,emc-mode-1 = <0x80100002>; > + nvidia,emc-mode-2 = <0x80200010>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x0000001b > + 0x0000009b > + 0x00000000 > + 0x00000013 > + 0x00000007 > + 0x00000007 > + 0x0000000b > + 0x00000003 > + 0x00000010 > + 0x00000007 > + 0x00000007 > + 0x00000002 > + 0x00000002 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x0000000a > + 0x00000002 > + 0x00000000 > + 0x00000003 > + 0x0000000b > + 0x00070000 > + 0x00000003 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000002 > + 0x00000012 > + 0x00000016 > + 0x00000018 > + 0x00001208 > + 0x00000000 > + 0x00000482 > + 0x00000002 > + 0x0000000d > + 0x00000001 > + 0x00000000 > + 0x00000097 > + 0x00000015 > + 0x000000a3 > + 0x00000200 > + 0x00000004 > + 0x00000005 > + 0x00000004 > + 0x00000015 > + 0x00000000 > + 0x00000006 > + 0x00000006 > + 0x00001248 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x104ab098 > + 0xe00e00b1 > + 0x00008000 > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00048000 > + 0x00048000 > + 0x00000000 > + 0x00048000 > + 0x00048000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x0000000d > + 0x0000000d > + 0x0000000d > + 0x0000000d > + 0x0000000d > + 0x0000000d > + 0x0000000d > + 0x0000000d > + 0x100002a0 > + 0x00000000 > + 0x00111111 > + 0x0121113d > + 0x00000000 > + 0x00000000 > + 0x77ffc085 > + 0x00000505 > + 0x81f1f108 > + 0x07070004 > + 0x00000000 > + 0x016eeeee > + 0x51451420 > + 0x00514514 > + 0x00514514 > + 0x51451400 > + 0x0606003f > + 0x00000000 > + 0x00000000 > + 0x00020000 > + 0x00000100 > + 0x0127000e > + 0x0127000e > + 0x00000000 > + 0x00000003 > + 0x000040a0 > + 0x800024a9 > + 0x0000000e > + >; > + }; > + timing@792000000 { > + clock-frequency = <792000000>; > + > + nvidia,emc-zcal-cnt-long = <0x00000042>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73300000>; > + nvidia,emc-cfg-2 = <0x0000089d>; > + nvidia,emc-sel-dpd-ctrl = <0x00040000>; > + nvidia,emc-cfg-dig-dll = <0xe0070069>; > + nvidia,emc-bgbias-ctl0 = <0x00000000>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430000>; > + nvidia,emc-mode-reset = <0x80000d71>; > + nvidia,emc-mode-1 = <0x80100002>; > + nvidia,emc-mode-2 = <0x80200018>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x00000024 > + 0x000000cd > + 0x00000000 > + 0x00000019 > + 0x0000000a > + 0x00000008 > + 0x0000000d > + 0x00000004 > + 0x00000013 > + 0x0000000a > + 0x0000000a > + 0x00000003 > + 0x00000002 > + 0x00000000 > + 0x00000006 > + 0x00000006 > + 0x0000000b > + 0x00000002 > + 0x00000000 > + 0x00000002 > + 0x0000000d > + 0x00080000 > + 0x00000004 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000001 > + 0x00000014 > + 0x00000018 > + 0x0000001a > + 0x000017e2 > + 0x00000000 > + 0x000005f8 > + 0x00000003 > + 0x00000011 > + 0x00000001 > + 0x00000000 > + 0x000000c7 > + 0x00000018 > + 0x000000d7 > + 0x00000200 > + 0x00000005 > + 0x00000006 > + 0x00000005 > + 0x0000001d > + 0x00000000 > + 0x00000008 > + 0x00000008 > + 0x00001822 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x104ab098 > + 0xe00700b1 > + 0x00008000 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00034000 > + 0x00034000 > + 0x00000000 > + 0x00034000 > + 0x00034000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x0000000a > + 0x100002a0 > + 0x00000000 > + 0x00111111 > + 0x0120113d > + 0x00000000 > + 0x00000000 > + 0x77ffc085 > + 0x00000000 > + 0x81f1f108 > + 0x07070004 > + 0x00000000 > + 0x016eeeee > + 0x61861820 > + 0x00514514 > + 0x00514514 > + 0x61861800 > + 0x0606003f > + 0x00000000 > + 0x00000000 > + 0x00020000 > + 0x00000100 > + 0x00f7000e > + 0x00f7000e > + 0x00000000 > + 0x00000004 > + 0x00004080 > + 0x80003012 > + 0x0000000f > + >; > + }; > + timing@924000000 { > + clock-frequency = <924000000>; > + > + nvidia,emc-zcal-cnt-long = <0x0000004c>; > + nvidia,emc-auto-cal-interval = <0x001fffff>; > + nvidia,emc-ctt-term-ctrl = <0x00000802>; > + nvidia,emc-cfg = <0x73300000>; > + nvidia,emc-cfg-2 = <0x0000089d>; > + nvidia,emc-sel-dpd-ctrl = <0x00040000>; > + nvidia,emc-cfg-dig-dll = <0xe0040069>; > + nvidia,emc-bgbias-ctl0 = <0x00000000>; > + nvidia,emc-auto-cal-config = <0x00000000>; > + nvidia,emc-auto-cal-config2 = <0x00000000>; > + nvidia,emc-auto-cal-config3 = <0xa1430303>; > + nvidia,emc-mode-reset = <0x80000f15>; > + nvidia,emc-mode-1 = <0x80100002>; > + nvidia,emc-mode-2 = <0x80200020>; > + nvidia,emc-mode-4 = <0x00000000>; > + > + nvidia,emc-configuration = < > + 0x0000002b > + 0x000000f0 > + 0x00000000 > + 0x0000001e > + 0x0000000b > + 0x00000009 > + 0x0000000f > + 0x00000005 > + 0x00000016 > + 0x0000000b > + 0x0000000b > + 0x00000004 > + 0x00000002 > + 0x00000000 > + 0x00000007 > + 0x00000007 > + 0x0000000d > + 0x00000002 > + 0x00000000 > + 0x00000002 > + 0x0000000f > + 0x000a0000 > + 0x00000004 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000001 > + 0x00000016 > + 0x0000001a > + 0x0000001c > + 0x00001be7 > + 0x00000000 > + 0x000006f9 > + 0x00000004 > + 0x00000015 > + 0x00000001 > + 0x00000000 > + 0x000000e7 > + 0x0000001b > + 0x000000fb > + 0x00000200 > + 0x00000006 > + 0x00000007 > + 0x00000006 > + 0x00000022 > + 0x00000000 > + 0x0000000a > + 0x0000000a > + 0x00001c28 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x104ab898 > + 0xe00400b1 > + 0x00008000 > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x007f800a > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x0002c000 > + 0x0002c000 > + 0x00000000 > + 0x0002c000 > + 0x0002c000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000000 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000005 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x00000008 > + 0x100002a0 > + 0x00000000 > + 0x00111111 > + 0x0120113d > + 0x00000000 > + 0x00000000 > + 0x77ffc085 > + 0x00000000 > + 0x81f1f108 > + 0x07070004 > + 0x00000000 > + 0x016eeeee > + 0x5d75d720 > + 0x00514514 > + 0x00514514 > + 0x5d75d700 > + 0x0606003f > + 0x00000000 > + 0x00000000 > + 0x00020000 > + 0x00000128 > + 0x00cd000e > + 0x00cd000e > + 0x00000000 > + 0x00000004 > + 0x00004080 > + 0x800037ea > + 0x00000011 > + >; > + }; > + }; > + }; > + > + memory-controller@0,70019000 { > + timings@3 { > + nvidia,ram-code = <3>; > + > + timing@12750000 { > + clock-frequency = <12750000>; > + > + nvidia,emem-configuration = < > + 0x40040001 /* MC_EMEM_ARB_CFG */ > + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ > + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ > + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ > + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ > + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ > + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ > + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ > + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ > + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ > + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ > + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ > + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ > + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ > + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ > + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ > + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ > + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ > + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ > + >; > + }; > + > + timing@20400000 { > + clock-frequency = <20400000>; > + > + nvidia,emem-configuration = < > + 0x40020001 > + 0x80000012 > + 0x00000001 > + 0x00000001 > + 0x00000002 > + 0x00000000 > + 0x00000002 > + 0x00000001 > + 0x00000002 > + 0x00000008 > + 0x00000003 > + 0x00000002 > + 0x00000003 > + 0x00000006 > + 0x06030203 > + 0x000a0402 > + 0x76230303 > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@40800000 { > + clock-frequency = <40800000>; > + > + nvidia,emem-configuration = < > + 0xa0000001 > + 0x80000017 > + 0x00000001 > + 0x00000001 > + 0x00000002 > + 0x00000000 > + 0x00000002 > + 0x00000001 > + 0x00000002 > + 0x00000008 > + 0x00000003 > + 0x00000002 > + 0x00000003 > + 0x00000006 > + 0x06030203 > + 0x000a0402 > + 0x74a30303 > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@68000000 { > + clock-frequency = <68000000>; > + > + nvidia,emem-configuration = < > + 0x00000001 > + 0x8000001e > + 0x00000001 > + 0x00000001 > + 0x00000002 > + 0x00000000 > + 0x00000002 > + 0x00000001 > + 0x00000002 > + 0x00000008 > + 0x00000003 > + 0x00000002 > + 0x00000003 > + 0x00000006 > + 0x06030203 > + 0x000a0402 > + 0x74230403 > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@102000000 { > + clock-frequency = <102000000>; > + > + nvidia,emem-configuration = < > + 0x08000001 > + 0x80000026 > + 0x00000001 > + 0x00000001 > + 0x00000003 > + 0x00000000 > + 0x00000002 > + 0x00000001 > + 0x00000002 > + 0x00000008 > + 0x00000003 > + 0x00000002 > + 0x00000003 > + 0x00000006 > + 0x06030203 > + 0x000a0403 > + 0x73c30504 > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@204000000 { > + clock-frequency = <204000000>; > + > + nvidia,emem-configuration = < > + 0x01000003 > + 0x80000040 > + 0x00000001 > + 0x00000001 > + 0x00000004 > + 0x00000002 > + 0x00000004 > + 0x00000001 > + 0x00000002 > + 0x00000008 > + 0x00000003 > + 0x00000002 > + 0x00000004 > + 0x00000006 > + 0x06040203 > + 0x000a0404 > + 0x73840a05 > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@300000000 { > + clock-frequency = <300000000>; > + > + nvidia,emem-configuration = < > + 0x08000004 > + 0x80000040 > + 0x00000001 > + 0x00000002 > + 0x00000007 > + 0x00000004 > + 0x00000005 > + 0x00000001 > + 0x00000002 > + 0x00000007 > + 0x00000002 > + 0x00000002 > + 0x00000004 > + 0x00000006 > + 0x06040202 > + 0x000b0607 > + 0x77450e08 > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@396000000 { > + clock-frequency = <396000000>; > + > + nvidia,emem-configuration = < > + 0x0f000005 > + 0x80000040 > + 0x00000001 > + 0x00000002 > + 0x00000009 > + 0x00000005 > + 0x00000007 > + 0x00000001 > + 0x00000002 > + 0x00000008 > + 0x00000002 > + 0x00000002 > + 0x00000004 > + 0x00000006 > + 0x06040202 > + 0x000d0709 > + 0x7586120a > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@528000000 { > + clock-frequency = <528000000>; > + > + nvidia,emem-configuration = < > + 0x0f000007 > + 0x80000040 > + 0x00000002 > + 0x00000003 > + 0x0000000c > + 0x00000007 > + 0x0000000a > + 0x00000001 > + 0x00000002 > + 0x00000009 > + 0x00000002 > + 0x00000002 > + 0x00000005 > + 0x00000006 > + 0x06050202 > + 0x0010090c > + 0x7428180d > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@600000000 { > + clock-frequency = <600000000>; > + > + nvidia,emem-configuration = < > + 0x00000009 > + 0x80000040 > + 0x00000003 > + 0x00000004 > + 0x0000000e > + 0x00000009 > + 0x0000000b > + 0x00000001 > + 0x00000003 > + 0x0000000b > + 0x00000002 > + 0x00000002 > + 0x00000005 > + 0x00000007 > + 0x07050202 > + 0x00130b0e > + 0x73a91b0f > + 0x70000f03 > + 0x001f0000 > + >; > + }; > + timing@792000000 { > + clock-frequency = <792000000>; > + > + nvidia,emem-configuration = < > + 0x0e00000b > + 0x80000040 > + 0x00000004 > + 0x00000005 > + 0x00000013 > + 0x0000000c > + 0x0000000f > + 0x00000002 > + 0x00000003 > + 0x0000000c > + 0x00000002 > + 0x00000002 > + 0x00000006 > + 0x00000008 > + 0x08060202 > + 0x00170e13 > + 0x736c2414 > + 0x70000f02 > + 0x001f0000 > + >; > + }; > + timing@924000000 { > + clock-frequency = <924000000>; > + > + nvidia,emem-configuration = < > + 0x0e00000d > + 0x80000040 > + 0x00000005 > + 0x00000006 > + 0x00000016 > + 0x0000000e > + 0x00000011 > + 0x00000002 > + 0x00000004 > + 0x0000000e > + 0x00000002 > + 0x00000002 > + 0x00000006 > + 0x00000009 > + 0x09060202 > + 0x001a1016 > + 0x734e2a17 > + 0x70000f02 > + 0x001f0000 > + >; > + }; > + }; > + }; > +}; > diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts > index 029c9a02..96de17e 100644 > --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts > +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts > @@ -3,6 +3,8 @@ > #include <dt-bindings/input/input.h> > #include "tegra124.dtsi" > > +#include "tegra124-jetson-tk1-emc.dtsi" > + > / { > model = "NVIDIA Tegra124 Jetson TK1"; > compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; > -- > 1.9.3 ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <20141106122149.GC3863-GNrqntRiisjPWV3K8zbkiAH8Oo8bv1DvZkel5v8DVj8@public.gmane.org>]
* Re: [PATCH v3 08/13] ARM: tegra: Add EMC timings to Jetson TK1 device tree [not found] ` <20141106122149.GC3863-GNrqntRiisjPWV3K8zbkiAH8Oo8bv1DvZkel5v8DVj8@public.gmane.org> @ 2014-11-07 16:12 ` Tomeu Vizoso 0 siblings, 0 replies; 23+ messages in thread From: Tomeu Vizoso @ 2014-11-07 16:12 UTC (permalink / raw) To: Nikolaus Schulz Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Javier Martinez Canillas, Mikko Perttunen, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On 6 November 2014 13:21, Nikolaus Schulz <nikolaus.schulz-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> wrote: > On Wed, Oct 29, 2014 at 05:22:26PM +0100, Tomeu Vizoso wrote: >> From: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >> >> This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains >> valid timings for the EMC memory clock. The file is included to the >> main Jetson TK1 device tree. >> >> Signed-off-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >> Signed-off-by: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> >> >> --- >> >> v2: * Fix the unit addresses of the timings and timing nodes > > This is not completely fixed yet, see FIXMEs below. Thanks a lot for checking. Tomeu > >> --- >> arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2412 ++++++++++++++++++++++++ >> arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 + >> 2 files changed, 2414 insertions(+) >> create mode 100644 arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi >> >> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi >> new file mode 100644 >> index 0000000..f1f391a >> --- /dev/null >> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi >> @@ -0,0 +1,2412 @@ >> +/ { >> + clock@0,60006000 { >> + emc-timings@3 { >> + nvidia,ram-code = <3>; >> + >> + timing@12750000 { >> + clock-frequency = <12750000>; >> + nvidia,parent-clock-frequency = <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; >> + }; >> + timing@20400000 { >> + clock-frequency = <20400000>; >> + nvidia,parent-clock-frequency = <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; >> + }; >> + timing@40800000 { >> + clock-frequency = <40800000>; >> + nvidia,parent-clock-frequency = <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; >> + }; >> + timing@68000000 { >> + clock-frequency = <68000000>; >> + nvidia,parent-clock-frequency = <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; >> + }; >> + timing@102000000 { >> + clock-frequency = <102000000>; >> + nvidia,parent-clock-frequency = <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; >> + }; >> + timing@204000000 { >> + clock-frequency = <204000000>; >> + nvidia,parent-clock-frequency = <408000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; >> + clock-names = "emc-parent"; >> + }; >> + timing@300000000 { >> + clock-frequency = <300000000>; >> + nvidia,parent-clock-frequency = <600000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; >> + clock-names = "emc-parent"; >> + }; >> + timing@396000000 { >> + clock-frequency = <396000000>; >> + nvidia,parent-clock-frequency = <792000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; >> + clock-names = "emc-parent"; >> + }; >> + timing@528000000 { >> + clock-frequency = <528000000>; >> + nvidia,parent-clock-frequency = <528000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; >> + clock-names = "emc-parent"; >> + }; >> + timing@600000000 { >> + clock-frequency = <600000000>; >> + nvidia,parent-clock-frequency = <600000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; >> + clock-names = "emc-parent"; >> + }; >> + timing@792000000 { >> + clock-frequency = <792000000>; >> + nvidia,parent-clock-frequency = <792000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; >> + clock-names = "emc-parent"; >> + }; >> + timing@924000000 { >> + clock-frequency = <924000000>; >> + nvidia,parent-clock-frequency = <924000000>; >> + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; >> + clock-names = "emc-parent"; >> + }; >> + }; >> + }; >> + >> + emc@0,7001b000 { >> + timings@3 { >> + nvidia,ram-code = <3>; >> + >> + timing@12750000 { >> + clock-frequency = <12750000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73240000>; >> + nvidia,emc-cfg-2 = <0x000008c5>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040128>; >> + nvidia,emc-cfg-dig-dll = <0x002c0068>; >> + nvidia,emc-bgbias-ctl0 = <0x00000008>; >> + nvidia,emc-auto-cal-config = <0xa1430000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0x00000000>; >> + nvidia,emc-mode-reset = <0x80001221>; >> + nvidia,emc-mode-1 = <0x80100003>; >> + nvidia,emc-mode-2 = <0x80200008>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000000 /* EMC_RC */ >> + 0x00000003 /* EMC_RFC */ >> + 0x00000000 /* EMC_RFC_SLR */ >> + 0x00000000 /* EMC_RAS */ >> + 0x00000000 /* EMC_RP */ >> + 0x00000004 /* EMC_R2W */ >> + 0x0000000a /* EMC_W2R */ >> + 0x00000003 /* EMC_R2P */ >> + 0x0000000b /* EMC_W2P */ >> + 0x00000000 /* EMC_RD_RCD */ >> + 0x00000000 /* EMC_WR_RCD */ >> + 0x00000003 /* EMC_RRD */ >> + 0x00000003 /* EMC_REXT */ >> + 0x00000000 /* EMC_WEXT */ >> + 0x00000006 /* EMC_WDV */ >> + 0x00000006 /* EMC_WDV_MASK */ >> + 0x00000006 /* EMC_QUSE */ >> + 0x00000002 /* EMC_QUSE_WIDTH */ >> + 0x00000000 /* EMC_IBDLY */ >> + 0x00000005 /* EMC_EINPUT */ >> + 0x00000005 /* EMC_EINPUT_DURATION */ >> + 0x00010000 /* EMC_PUTERM_EXTRA */ >> + 0x00000003 /* EMC_PUTERM_WIDTH */ >> + 0x00000000 /* EMC_PUTERM_ADJ */ >> + 0x00000000 /* EMC_CDB_CNTL_1 */ >> + 0x00000000 /* EMC_CDB_CNTL_2 */ >> + 0x00000000 /* EMC_CDB_CNTL_3 */ >> + 0x00000004 /* EMC_QRST */ >> + 0x0000000c /* EMC_QSAFE */ >> + 0x0000000d /* EMC_RDV */ >> + 0x0000000f /* EMC_RDV_MASK */ >> + 0x00000060 /* EMC_REFRESH */ >> + 0x00000000 /* EMC_BURST_REFRESH_NUM */ >> + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ >> + 0x00000002 /* EMC_PDEX2WR */ >> + 0x00000002 /* EMC_PDEX2RD */ >> + 0x00000001 /* EMC_PCHG2PDEN */ >> + 0x00000000 /* EMC_ACT2PDEN */ >> + 0x00000007 /* EMC_AR2PDEN */ >> + 0x0000000f /* EMC_RW2PDEN */ >> + 0x00000005 /* EMC_TXSR */ >> + 0x00000005 /* EMC_TXSRDLL */ >> + 0x00000004 /* EMC_TCKE */ >> + 0x00000005 /* EMC_TCKESR */ >> + 0x00000004 /* EMC_TPD */ >> + 0x00000000 /* EMC_TFAW */ >> + 0x00000000 /* EMC_TRPAB */ >> + 0x00000005 /* EMC_TCLKSTABLE */ >> + 0x00000005 /* EMC_TCLKSTOP */ >> + 0x00000064 /* EMC_TREFBW */ >> + 0x00000000 /* EMC_FBIO_CFG6 */ >> + 0x00000000 /* EMC_ODT_WRITE */ >> + 0x00000000 /* EMC_ODT_READ */ >> + 0x106aa298 /* EMC_FBIO_CFG5 */ >> + 0x002c00a0 /* EMC_CFG_DIG_DLL */ >> + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ >> + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ >> + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ >> + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ >> + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ >> + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ >> + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ >> + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ >> + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ >> + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ >> + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ >> + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ >> + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ >> + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ >> + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ >> + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ >> + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ >> + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ >> + 0x10000280 /* EMC_XM2CMDPADCTRL */ >> + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ >> + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ >> + 0x0130b118 /* EMC_XM2DQSPADCTRL2 */ >> + 0x00000000 /* EMC_XM2DQPADCTRL2 */ >> + 0x00000000 /* EMC_XM2DQPADCTRL3 */ >> + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ >> + 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ >> + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ >> + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ >> + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ >> + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ >> + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ >> + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ >> + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ >> + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ >> + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ >> + 0x00000007 /* EMC_TXDSRVTTGEN */ >> + 0x00000000 /* EMC_FBIO_SPARE */ >> + 0x00000000 /* EMC_ZCAL_INTERVAL */ >> + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ >> + 0x000e000e /* EMC_MRS_WAIT_CNT */ >> + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ >> + 0x00000000 /* EMC_CTT */ >> + 0x00000003 /* EMC_CTT_DURATION */ >> + 0x0000f2f3 /* EMC_CFG_PIPE */ >> + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ >> + 0x0000000a /* EMC_QPOP */ >> + >; >> + }; >> + >> + timing@20400000 { >> + clock-frequency = <20400000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73240000>; >> + nvidia,emc-cfg-2 = <0x000008c5>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040128>; >> + nvidia,emc-cfg-dig-dll = <0x002c0068>; >> + nvidia,emc-bgbias-ctl0 = <0x00000008>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80001221>; >> + nvidia,emc-mode-1 = <0x80100003>; >> + nvidia,emc-mode-2 = <0x80200008>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000000 >> + 0x00000005 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000004 >> + 0x0000000a >> + 0x00000003 >> + 0x0000000b >> + 0x00000000 >> + 0x00000000 >> + 0x00000003 >> + 0x00000003 >> + 0x00000000 >> + 0x00000006 >> + 0x00000006 >> + 0x00000006 >> + 0x00000002 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00010000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000004 >> + 0x0000000c >> + 0x0000000d >> + 0x0000000f >> + 0x0000009a >> + 0x00000000 >> + 0x00000026 >> + 0x00000002 >> + 0x00000002 >> + 0x00000001 >> + 0x00000000 >> + 0x00000007 >> + 0x0000000f >> + 0x00000006 >> + 0x00000006 >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x00000000 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x000000a0 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x106aa298 >> + 0x002c00a0 >> + 0x00008000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x10000280 >> + 0x00000000 >> + 0x00111111 >> + 0x0130b118 >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc081 >> + 0x00000e0e >> + 0x81f1f108 >> + 0x07070004 >> + 0x0000003f >> + 0x016eeeee >> + 0x51451400 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0000003f >> + 0x0000000b >> + 0x00000000 >> + 0x00000000 >> + 0x00000042 >> + 0x000e000e >> + 0x000e000e >> + 0x00000000 >> + 0x00000003 >> + 0x0000f2f3 >> + 0x8000023a >> + 0x0000000a >> + >; >> + }; >> + timing@2 { > > FIXME: this should be timing@40800000 > >> + clock-frequency = <40800000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73240000>; >> + nvidia,emc-cfg-2 = <0x000008c5>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040128>; >> + nvidia,emc-cfg-dig-dll = <0x002c0068>; >> + nvidia,emc-bgbias-ctl0 = <0x00000008>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80001221>; >> + nvidia,emc-mode-1 = <0x80100003>; >> + nvidia,emc-mode-2 = <0x80200008>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000001 >> + 0x0000000a >> + 0x00000000 >> + 0x00000001 >> + 0x00000000 >> + 0x00000004 >> + 0x0000000a >> + 0x00000003 >> + 0x0000000b >> + 0x00000000 >> + 0x00000000 >> + 0x00000003 >> + 0x00000003 >> + 0x00000000 >> + 0x00000006 >> + 0x00000006 >> + 0x00000006 >> + 0x00000002 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00010000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000004 >> + 0x0000000c >> + 0x0000000d >> + 0x0000000f >> + 0x00000134 >> + 0x00000000 >> + 0x0000004d >> + 0x00000002 >> + 0x00000002 >> + 0x00000001 >> + 0x00000000 >> + 0x00000008 >> + 0x0000000f >> + 0x0000000c >> + 0x0000000c >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x00000000 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x0000013f >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x106aa298 >> + 0x002c00a0 >> + 0x00008000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x10000280 >> + 0x00000000 >> + 0x00111111 >> + 0x0130b118 >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc081 >> + 0x00000e0e >> + 0x81f1f108 >> + 0x07070004 >> + 0x0000003f >> + 0x016eeeee >> + 0x51451400 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0000003f >> + 0x00000015 >> + 0x00000000 >> + 0x00000000 >> + 0x00000042 >> + 0x000e000e >> + 0x000e000e >> + 0x00000000 >> + 0x00000003 >> + 0x0000f2f3 >> + 0x80000370 >> + 0x0000000a >> + >; >> + }; >> + timing@3 { > > FIXME: should be timing@68000000 > >> + clock-frequency = <68000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73240000>; >> + nvidia,emc-cfg-2 = <0x000008c5>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040128>; >> + nvidia,emc-cfg-dig-dll = <0x002c0068>; >> + nvidia,emc-bgbias-ctl0 = <0x00000008>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80001221>; >> + nvidia,emc-mode-1 = <0x80100003>; >> + nvidia,emc-mode-2 = <0x80200008>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000003 >> + 0x00000011 >> + 0x00000000 >> + 0x00000002 >> + 0x00000000 >> + 0x00000004 >> + 0x0000000a >> + 0x00000003 >> + 0x0000000b >> + 0x00000000 >> + 0x00000000 >> + 0x00000003 >> + 0x00000003 >> + 0x00000000 >> + 0x00000006 >> + 0x00000006 >> + 0x00000006 >> + 0x00000002 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00010000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000004 >> + 0x0000000c >> + 0x0000000d >> + 0x0000000f >> + 0x00000202 >> + 0x00000000 >> + 0x00000080 >> + 0x00000002 >> + 0x00000002 >> + 0x00000001 >> + 0x00000000 >> + 0x0000000f >> + 0x0000000f >> + 0x00000013 >> + 0x00000013 >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x00000001 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00000213 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x106aa298 >> + 0x002c00a0 >> + 0x00008000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x10000280 >> + 0x00000000 >> + 0x00111111 >> + 0x0130b118 >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc081 >> + 0x00000e0e >> + 0x81f1f108 >> + 0x07070004 >> + 0x0000003f >> + 0x016eeeee >> + 0x51451400 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0000003f >> + 0x00000022 >> + 0x00000000 >> + 0x00000000 >> + 0x00000042 >> + 0x000e000e >> + 0x000e000e >> + 0x00000000 >> + 0x00000003 >> + 0x0000f2f3 >> + 0x8000050e >> + 0x0000000a >> + >; >> + }; >> + timing@4 { > > FIXME: timing@102000000 > >> + clock-frequency = <102000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73240000>; >> + nvidia,emc-cfg-2 = <0x000008c5>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040128>; >> + nvidia,emc-cfg-dig-dll = <0x002c0068>; >> + nvidia,emc-bgbias-ctl0 = <0x00000008>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80001221>; >> + nvidia,emc-mode-1 = <0x80100003>; >> + nvidia,emc-mode-2 = <0x80200008>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000004 >> + 0x0000001a >> + 0x00000000 >> + 0x00000003 >> + 0x00000001 >> + 0x00000004 >> + 0x0000000a >> + 0x00000003 >> + 0x0000000b >> + 0x00000001 >> + 0x00000001 >> + 0x00000003 >> + 0x00000003 >> + 0x00000000 >> + 0x00000006 >> + 0x00000006 >> + 0x00000006 >> + 0x00000002 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00010000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000004 >> + 0x0000000c >> + 0x0000000d >> + 0x0000000f >> + 0x00000304 >> + 0x00000000 >> + 0x000000c1 >> + 0x00000002 >> + 0x00000002 >> + 0x00000001 >> + 0x00000000 >> + 0x00000018 >> + 0x0000000f >> + 0x0000001c >> + 0x0000001c >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x00000003 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x0000031c >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x106aa298 >> + 0x002c00a0 >> + 0x00008000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x000fc000 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x0000fc00 >> + 0x10000280 >> + 0x00000000 >> + 0x00111111 >> + 0x0130b118 >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc081 >> + 0x00000e0e >> + 0x81f1f108 >> + 0x07070004 >> + 0x0000003f >> + 0x016eeeee >> + 0x51451400 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0000003f >> + 0x00000033 >> + 0x00000000 >> + 0x00000000 >> + 0x00000042 >> + 0x000e000e >> + 0x000e000e >> + 0x00000000 >> + 0x00000003 >> + 0x0000f2f3 >> + 0x80000713 >> + 0x0000000a >> + >; >> + }; >> + timing@204000000 { >> + clock-frequency = <204000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73240000>; >> + nvidia,emc-cfg-2 = <0x0000088d>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040008>; >> + nvidia,emc-cfg-dig-dll = <0x002c0068>; >> + nvidia,emc-bgbias-ctl0 = <0x00000008>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80001221>; >> + nvidia,emc-mode-1 = <0x80100003>; >> + nvidia,emc-mode-2 = <0x80200008>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000009 >> + 0x00000035 >> + 0x00000000 >> + 0x00000006 >> + 0x00000002 >> + 0x00000005 >> + 0x0000000a >> + 0x00000003 >> + 0x0000000b >> + 0x00000002 >> + 0x00000002 >> + 0x00000003 >> + 0x00000003 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00000006 >> + 0x00000002 >> + 0x00000000 >> + 0x00000004 >> + 0x00000006 >> + 0x00010000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000003 >> + 0x0000000d >> + 0x0000000f >> + 0x00000011 >> + 0x00000607 >> + 0x00000000 >> + 0x00000181 >> + 0x00000002 >> + 0x00000002 >> + 0x00000001 >> + 0x00000000 >> + 0x00000032 >> + 0x0000000f >> + 0x00000038 >> + 0x00000038 >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x00000007 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00000638 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x106aa298 >> + 0x002c00a0 >> + 0x00008000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00064000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00008000 >> + 0x00000000 >> + 0x00000000 >> + 0x00008000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00090000 >> + 0x00090000 >> + 0x00090000 >> + 0x00090000 >> + 0x00009000 >> + 0x00009000 >> + 0x00009000 >> + 0x00009000 >> + 0x10000280 >> + 0x00000000 >> + 0x00111111 >> + 0x0130b118 >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc081 >> + 0x00000707 >> + 0x81f1f108 >> + 0x07070004 >> + 0x0000003f >> + 0x016eeeee >> + 0x51451400 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0000003f >> + 0x00000066 >> + 0x00000000 >> + 0x00020000 >> + 0x00000100 >> + 0x000e000e >> + 0x000e000e >> + 0x00000000 >> + 0x00000003 >> + 0x0000d2b3 >> + 0x80000d22 >> + 0x0000000a >> + >; >> + }; >> + timing@300000000 { >> + clock-frequency = <300000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73340000>; >> + nvidia,emc-cfg-2 = <0x000008d5>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040128>; >> + nvidia,emc-cfg-dig-dll = <0x002c0068>; >> + nvidia,emc-bgbias-ctl0 = <0x00000000>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80000321>; >> + nvidia,emc-mode-1 = <0x80100002>; >> + nvidia,emc-mode-2 = <0x80200000>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x0000000d >> + 0x0000004d >> + 0x00000000 >> + 0x00000009 >> + 0x00000003 >> + 0x00000004 >> + 0x00000008 >> + 0x00000002 >> + 0x00000009 >> + 0x00000003 >> + 0x00000003 >> + 0x00000002 >> + 0x00000002 >> + 0x00000000 >> + 0x00000003 >> + 0x00000003 >> + 0x00000005 >> + 0x00000002 >> + 0x00000000 >> + 0x00000002 >> + 0x00000007 >> + 0x00020000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000001 >> + 0x0000000e >> + 0x00000010 >> + 0x00000012 >> + 0x000008e4 >> + 0x00000000 >> + 0x00000239 >> + 0x00000001 >> + 0x00000008 >> + 0x00000001 >> + 0x00000000 >> + 0x0000004b >> + 0x0000000e >> + 0x00000052 >> + 0x00000200 >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x00000009 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00000924 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x104ab098 >> + 0x002c00a0 >> + 0x00008000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00098000 >> + 0x00098000 >> + 0x00000000 >> + 0x00098000 >> + 0x00098000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00060000 >> + 0x00060000 >> + 0x00060000 >> + 0x00060000 >> + 0x00006000 >> + 0x00006000 >> + 0x00006000 >> + 0x00006000 >> + 0x10000280 >> + 0x00000000 >> + 0x00111111 >> + 0x01231339 >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc081 >> + 0x00000505 >> + 0x81f1f108 >> + 0x07070004 >> + 0x00000000 >> + 0x016eeeee >> + 0x51451420 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0000003f >> + 0x00000096 >> + 0x00000000 >> + 0x00020000 >> + 0x00000100 >> + 0x0173000e >> + 0x0173000e >> + 0x00000000 >> + 0x00000003 >> + 0x000052a3 >> + 0x800012d7 >> + 0x00000009 >> + >; >> + }; >> + timing@396000000 { >> + clock-frequency = <396000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73340000>; >> + nvidia,emc-cfg-2 = <0x00000895>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040008>; >> + nvidia,emc-cfg-dig-dll = <0x002c0068>; >> + nvidia,emc-bgbias-ctl0 = <0x00000000>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80000521>; >> + nvidia,emc-mode-1 = <0x80100002>; >> + nvidia,emc-mode-2 = <0x80200000>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000011 >> + 0x00000066 >> + 0x00000000 >> + 0x0000000c >> + 0x00000004 >> + 0x00000004 >> + 0x00000008 >> + 0x00000002 >> + 0x0000000a >> + 0x00000004 >> + 0x00000004 >> + 0x00000002 >> + 0x00000002 >> + 0x00000000 >> + 0x00000003 >> + 0x00000003 >> + 0x00000005 >> + 0x00000002 >> + 0x00000000 >> + 0x00000001 >> + 0x00000008 >> + 0x00020000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x0000000f >> + 0x00000010 >> + 0x00000012 >> + 0x00000bd1 >> + 0x00000000 >> + 0x000002f4 >> + 0x00000001 >> + 0x00000008 >> + 0x00000001 >> + 0x00000000 >> + 0x00000063 >> + 0x0000000f >> + 0x0000006c >> + 0x00000200 >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x0000000d >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00000c11 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x104ab098 >> + 0x002c00a0 >> + 0x00008000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00030000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00070000 >> + 0x00070000 >> + 0x00000000 >> + 0x00070000 >> + 0x00070000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00038000 >> + 0x00038000 >> + 0x00038000 >> + 0x00038000 >> + 0x00003800 >> + 0x00003800 >> + 0x00003800 >> + 0x00003800 >> + 0x10000280 >> + 0x00000000 >> + 0x00111111 >> + 0x01231339 >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc081 >> + 0x00000505 >> + 0x81f1f108 >> + 0x07070004 >> + 0x00000000 >> + 0x016eeeee >> + 0x51451420 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0000003f >> + 0x000000c6 >> + 0x00000000 >> + 0x00020000 >> + 0x00000100 >> + 0x015b000e >> + 0x015b000e >> + 0x00000000 >> + 0x00000003 >> + 0x000052a3 >> + 0x8000188b >> + 0x00000009 >> + >; >> + }; >> + timing@528000000 { >> + clock-frequency = <528000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73300000>; >> + nvidia,emc-cfg-2 = <0x0000089d>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040008>; >> + nvidia,emc-cfg-dig-dll = <0xe0120069>; >> + nvidia,emc-bgbias-ctl0 = <0x00000000>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80000941>; >> + nvidia,emc-mode-1 = <0x80100002>; >> + nvidia,emc-mode-2 = <0x80200008>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000018 >> + 0x00000088 >> + 0x00000000 >> + 0x00000010 >> + 0x00000006 >> + 0x00000006 >> + 0x00000009 >> + 0x00000002 >> + 0x0000000d >> + 0x00000006 >> + 0x00000006 >> + 0x00000002 >> + 0x00000002 >> + 0x00000000 >> + 0x00000003 >> + 0x00000003 >> + 0x00000006 >> + 0x00000002 >> + 0x00000000 >> + 0x00000001 >> + 0x00000009 >> + 0x00030000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000010 >> + 0x00000012 >> + 0x00000014 >> + 0x00000fd6 >> + 0x00000000 >> + 0x000003f5 >> + 0x00000002 >> + 0x0000000b >> + 0x00000001 >> + 0x00000000 >> + 0x00000085 >> + 0x00000012 >> + 0x00000090 >> + 0x00000200 >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x00000013 >> + 0x00000000 >> + 0x00000006 >> + 0x00000006 >> + 0x00001017 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x104ab098 >> + 0xe01200b1 >> + 0x00008000 >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00054000 >> + 0x00054000 >> + 0x00000000 >> + 0x00054000 >> + 0x00054000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x0000000e >> + 0x0000000e >> + 0x0000000e >> + 0x0000000e >> + 0x0000000e >> + 0x0000000e >> + 0x0000000e >> + 0x0000000e >> + 0x100002a0 >> + 0x00000000 >> + 0x00111111 >> + 0x0123133d >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc085 >> + 0x00000505 >> + 0x81f1f108 >> + 0x07070004 >> + 0x00000000 >> + 0x016eeeee >> + 0x51451420 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0606003f >> + 0x00000000 >> + 0x00000000 >> + 0x00020000 >> + 0x00000100 >> + 0x0139000e >> + 0x0139000e >> + 0x00000000 >> + 0x00000003 >> + 0x000042a0 >> + 0x80002062 >> + 0x0000000a >> + >; >> + }; >> + timing@600000000 { >> + clock-frequency = <600000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73300000>; >> + nvidia,emc-cfg-2 = <0x0000089d>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040008>; >> + nvidia,emc-cfg-dig-dll = <0xe00e0069>; >> + nvidia,emc-bgbias-ctl0 = <0x00000000>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80000b61>; >> + nvidia,emc-mode-1 = <0x80100002>; >> + nvidia,emc-mode-2 = <0x80200010>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x0000001b >> + 0x0000009b >> + 0x00000000 >> + 0x00000013 >> + 0x00000007 >> + 0x00000007 >> + 0x0000000b >> + 0x00000003 >> + 0x00000010 >> + 0x00000007 >> + 0x00000007 >> + 0x00000002 >> + 0x00000002 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x0000000a >> + 0x00000002 >> + 0x00000000 >> + 0x00000003 >> + 0x0000000b >> + 0x00070000 >> + 0x00000003 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000002 >> + 0x00000012 >> + 0x00000016 >> + 0x00000018 >> + 0x00001208 >> + 0x00000000 >> + 0x00000482 >> + 0x00000002 >> + 0x0000000d >> + 0x00000001 >> + 0x00000000 >> + 0x00000097 >> + 0x00000015 >> + 0x000000a3 >> + 0x00000200 >> + 0x00000004 >> + 0x00000005 >> + 0x00000004 >> + 0x00000015 >> + 0x00000000 >> + 0x00000006 >> + 0x00000006 >> + 0x00001248 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x104ab098 >> + 0xe00e00b1 >> + 0x00008000 >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00048000 >> + 0x00048000 >> + 0x00000000 >> + 0x00048000 >> + 0x00048000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x0000000d >> + 0x0000000d >> + 0x0000000d >> + 0x0000000d >> + 0x0000000d >> + 0x0000000d >> + 0x0000000d >> + 0x0000000d >> + 0x100002a0 >> + 0x00000000 >> + 0x00111111 >> + 0x0121113d >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc085 >> + 0x00000505 >> + 0x81f1f108 >> + 0x07070004 >> + 0x00000000 >> + 0x016eeeee >> + 0x51451420 >> + 0x00514514 >> + 0x00514514 >> + 0x51451400 >> + 0x0606003f >> + 0x00000000 >> + 0x00000000 >> + 0x00020000 >> + 0x00000100 >> + 0x0127000e >> + 0x0127000e >> + 0x00000000 >> + 0x00000003 >> + 0x000040a0 >> + 0x800024a9 >> + 0x0000000e >> + >; >> + }; >> + timing@792000000 { >> + clock-frequency = <792000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x00000042>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73300000>; >> + nvidia,emc-cfg-2 = <0x0000089d>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040000>; >> + nvidia,emc-cfg-dig-dll = <0xe0070069>; >> + nvidia,emc-bgbias-ctl0 = <0x00000000>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430000>; >> + nvidia,emc-mode-reset = <0x80000d71>; >> + nvidia,emc-mode-1 = <0x80100002>; >> + nvidia,emc-mode-2 = <0x80200018>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x00000024 >> + 0x000000cd >> + 0x00000000 >> + 0x00000019 >> + 0x0000000a >> + 0x00000008 >> + 0x0000000d >> + 0x00000004 >> + 0x00000013 >> + 0x0000000a >> + 0x0000000a >> + 0x00000003 >> + 0x00000002 >> + 0x00000000 >> + 0x00000006 >> + 0x00000006 >> + 0x0000000b >> + 0x00000002 >> + 0x00000000 >> + 0x00000002 >> + 0x0000000d >> + 0x00080000 >> + 0x00000004 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000001 >> + 0x00000014 >> + 0x00000018 >> + 0x0000001a >> + 0x000017e2 >> + 0x00000000 >> + 0x000005f8 >> + 0x00000003 >> + 0x00000011 >> + 0x00000001 >> + 0x00000000 >> + 0x000000c7 >> + 0x00000018 >> + 0x000000d7 >> + 0x00000200 >> + 0x00000005 >> + 0x00000006 >> + 0x00000005 >> + 0x0000001d >> + 0x00000000 >> + 0x00000008 >> + 0x00000008 >> + 0x00001822 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x104ab098 >> + 0xe00700b1 >> + 0x00008000 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00034000 >> + 0x00034000 >> + 0x00000000 >> + 0x00034000 >> + 0x00034000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x0000000a >> + 0x100002a0 >> + 0x00000000 >> + 0x00111111 >> + 0x0120113d >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc085 >> + 0x00000000 >> + 0x81f1f108 >> + 0x07070004 >> + 0x00000000 >> + 0x016eeeee >> + 0x61861820 >> + 0x00514514 >> + 0x00514514 >> + 0x61861800 >> + 0x0606003f >> + 0x00000000 >> + 0x00000000 >> + 0x00020000 >> + 0x00000100 >> + 0x00f7000e >> + 0x00f7000e >> + 0x00000000 >> + 0x00000004 >> + 0x00004080 >> + 0x80003012 >> + 0x0000000f >> + >; >> + }; >> + timing@924000000 { >> + clock-frequency = <924000000>; >> + >> + nvidia,emc-zcal-cnt-long = <0x0000004c>; >> + nvidia,emc-auto-cal-interval = <0x001fffff>; >> + nvidia,emc-ctt-term-ctrl = <0x00000802>; >> + nvidia,emc-cfg = <0x73300000>; >> + nvidia,emc-cfg-2 = <0x0000089d>; >> + nvidia,emc-sel-dpd-ctrl = <0x00040000>; >> + nvidia,emc-cfg-dig-dll = <0xe0040069>; >> + nvidia,emc-bgbias-ctl0 = <0x00000000>; >> + nvidia,emc-auto-cal-config = <0x00000000>; >> + nvidia,emc-auto-cal-config2 = <0x00000000>; >> + nvidia,emc-auto-cal-config3 = <0xa1430303>; >> + nvidia,emc-mode-reset = <0x80000f15>; >> + nvidia,emc-mode-1 = <0x80100002>; >> + nvidia,emc-mode-2 = <0x80200020>; >> + nvidia,emc-mode-4 = <0x00000000>; >> + >> + nvidia,emc-configuration = < >> + 0x0000002b >> + 0x000000f0 >> + 0x00000000 >> + 0x0000001e >> + 0x0000000b >> + 0x00000009 >> + 0x0000000f >> + 0x00000005 >> + 0x00000016 >> + 0x0000000b >> + 0x0000000b >> + 0x00000004 >> + 0x00000002 >> + 0x00000000 >> + 0x00000007 >> + 0x00000007 >> + 0x0000000d >> + 0x00000002 >> + 0x00000000 >> + 0x00000002 >> + 0x0000000f >> + 0x000a0000 >> + 0x00000004 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000001 >> + 0x00000016 >> + 0x0000001a >> + 0x0000001c >> + 0x00001be7 >> + 0x00000000 >> + 0x000006f9 >> + 0x00000004 >> + 0x00000015 >> + 0x00000001 >> + 0x00000000 >> + 0x000000e7 >> + 0x0000001b >> + 0x000000fb >> + 0x00000200 >> + 0x00000006 >> + 0x00000007 >> + 0x00000006 >> + 0x00000022 >> + 0x00000000 >> + 0x0000000a >> + 0x0000000a >> + 0x00001c28 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x104ab898 >> + 0xe00400b1 >> + 0x00008000 >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x007f800a >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x0002c000 >> + 0x0002c000 >> + 0x00000000 >> + 0x0002c000 >> + 0x0002c000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000000 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000005 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x00000008 >> + 0x100002a0 >> + 0x00000000 >> + 0x00111111 >> + 0x0120113d >> + 0x00000000 >> + 0x00000000 >> + 0x77ffc085 >> + 0x00000000 >> + 0x81f1f108 >> + 0x07070004 >> + 0x00000000 >> + 0x016eeeee >> + 0x5d75d720 >> + 0x00514514 >> + 0x00514514 >> + 0x5d75d700 >> + 0x0606003f >> + 0x00000000 >> + 0x00000000 >> + 0x00020000 >> + 0x00000128 >> + 0x00cd000e >> + 0x00cd000e >> + 0x00000000 >> + 0x00000004 >> + 0x00004080 >> + 0x800037ea >> + 0x00000011 >> + >; >> + }; >> + }; >> + }; >> + >> + memory-controller@0,70019000 { >> + timings@3 { >> + nvidia,ram-code = <3>; >> + >> + timing@12750000 { >> + clock-frequency = <12750000>; >> + >> + nvidia,emem-configuration = < >> + 0x40040001 /* MC_EMEM_ARB_CFG */ >> + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ >> + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ >> + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ >> + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ >> + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ >> + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ >> + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ >> + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ >> + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ >> + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ >> + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ >> + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ >> + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ >> + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ >> + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ >> + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ >> + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ >> + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >> + >; >> + }; >> + >> + timing@20400000 { >> + clock-frequency = <20400000>; >> + >> + nvidia,emem-configuration = < >> + 0x40020001 >> + 0x80000012 >> + 0x00000001 >> + 0x00000001 >> + 0x00000002 >> + 0x00000000 >> + 0x00000002 >> + 0x00000001 >> + 0x00000002 >> + 0x00000008 >> + 0x00000003 >> + 0x00000002 >> + 0x00000003 >> + 0x00000006 >> + 0x06030203 >> + 0x000a0402 >> + 0x76230303 >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@40800000 { >> + clock-frequency = <40800000>; >> + >> + nvidia,emem-configuration = < >> + 0xa0000001 >> + 0x80000017 >> + 0x00000001 >> + 0x00000001 >> + 0x00000002 >> + 0x00000000 >> + 0x00000002 >> + 0x00000001 >> + 0x00000002 >> + 0x00000008 >> + 0x00000003 >> + 0x00000002 >> + 0x00000003 >> + 0x00000006 >> + 0x06030203 >> + 0x000a0402 >> + 0x74a30303 >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@68000000 { >> + clock-frequency = <68000000>; >> + >> + nvidia,emem-configuration = < >> + 0x00000001 >> + 0x8000001e >> + 0x00000001 >> + 0x00000001 >> + 0x00000002 >> + 0x00000000 >> + 0x00000002 >> + 0x00000001 >> + 0x00000002 >> + 0x00000008 >> + 0x00000003 >> + 0x00000002 >> + 0x00000003 >> + 0x00000006 >> + 0x06030203 >> + 0x000a0402 >> + 0x74230403 >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@102000000 { >> + clock-frequency = <102000000>; >> + >> + nvidia,emem-configuration = < >> + 0x08000001 >> + 0x80000026 >> + 0x00000001 >> + 0x00000001 >> + 0x00000003 >> + 0x00000000 >> + 0x00000002 >> + 0x00000001 >> + 0x00000002 >> + 0x00000008 >> + 0x00000003 >> + 0x00000002 >> + 0x00000003 >> + 0x00000006 >> + 0x06030203 >> + 0x000a0403 >> + 0x73c30504 >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@204000000 { >> + clock-frequency = <204000000>; >> + >> + nvidia,emem-configuration = < >> + 0x01000003 >> + 0x80000040 >> + 0x00000001 >> + 0x00000001 >> + 0x00000004 >> + 0x00000002 >> + 0x00000004 >> + 0x00000001 >> + 0x00000002 >> + 0x00000008 >> + 0x00000003 >> + 0x00000002 >> + 0x00000004 >> + 0x00000006 >> + 0x06040203 >> + 0x000a0404 >> + 0x73840a05 >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@300000000 { >> + clock-frequency = <300000000>; >> + >> + nvidia,emem-configuration = < >> + 0x08000004 >> + 0x80000040 >> + 0x00000001 >> + 0x00000002 >> + 0x00000007 >> + 0x00000004 >> + 0x00000005 >> + 0x00000001 >> + 0x00000002 >> + 0x00000007 >> + 0x00000002 >> + 0x00000002 >> + 0x00000004 >> + 0x00000006 >> + 0x06040202 >> + 0x000b0607 >> + 0x77450e08 >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@396000000 { >> + clock-frequency = <396000000>; >> + >> + nvidia,emem-configuration = < >> + 0x0f000005 >> + 0x80000040 >> + 0x00000001 >> + 0x00000002 >> + 0x00000009 >> + 0x00000005 >> + 0x00000007 >> + 0x00000001 >> + 0x00000002 >> + 0x00000008 >> + 0x00000002 >> + 0x00000002 >> + 0x00000004 >> + 0x00000006 >> + 0x06040202 >> + 0x000d0709 >> + 0x7586120a >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@528000000 { >> + clock-frequency = <528000000>; >> + >> + nvidia,emem-configuration = < >> + 0x0f000007 >> + 0x80000040 >> + 0x00000002 >> + 0x00000003 >> + 0x0000000c >> + 0x00000007 >> + 0x0000000a >> + 0x00000001 >> + 0x00000002 >> + 0x00000009 >> + 0x00000002 >> + 0x00000002 >> + 0x00000005 >> + 0x00000006 >> + 0x06050202 >> + 0x0010090c >> + 0x7428180d >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@600000000 { >> + clock-frequency = <600000000>; >> + >> + nvidia,emem-configuration = < >> + 0x00000009 >> + 0x80000040 >> + 0x00000003 >> + 0x00000004 >> + 0x0000000e >> + 0x00000009 >> + 0x0000000b >> + 0x00000001 >> + 0x00000003 >> + 0x0000000b >> + 0x00000002 >> + 0x00000002 >> + 0x00000005 >> + 0x00000007 >> + 0x07050202 >> + 0x00130b0e >> + 0x73a91b0f >> + 0x70000f03 >> + 0x001f0000 >> + >; >> + }; >> + timing@792000000 { >> + clock-frequency = <792000000>; >> + >> + nvidia,emem-configuration = < >> + 0x0e00000b >> + 0x80000040 >> + 0x00000004 >> + 0x00000005 >> + 0x00000013 >> + 0x0000000c >> + 0x0000000f >> + 0x00000002 >> + 0x00000003 >> + 0x0000000c >> + 0x00000002 >> + 0x00000002 >> + 0x00000006 >> + 0x00000008 >> + 0x08060202 >> + 0x00170e13 >> + 0x736c2414 >> + 0x70000f02 >> + 0x001f0000 >> + >; >> + }; >> + timing@924000000 { >> + clock-frequency = <924000000>; >> + >> + nvidia,emem-configuration = < >> + 0x0e00000d >> + 0x80000040 >> + 0x00000005 >> + 0x00000006 >> + 0x00000016 >> + 0x0000000e >> + 0x00000011 >> + 0x00000002 >> + 0x00000004 >> + 0x0000000e >> + 0x00000002 >> + 0x00000002 >> + 0x00000006 >> + 0x00000009 >> + 0x09060202 >> + 0x001a1016 >> + 0x734e2a17 >> + 0x70000f02 >> + 0x001f0000 >> + >; >> + }; >> + }; >> + }; >> +}; >> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts >> index 029c9a02..96de17e 100644 >> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts >> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts >> @@ -3,6 +3,8 @@ >> #include <dt-bindings/input/input.h> >> #include "tegra124.dtsi" >> >> +#include "tegra124-jetson-tk1-emc.dtsi" >> + >> / { >> model = "NVIDIA Tegra124 Jetson TK1"; >> compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; >> -- >> 1.9.3 > -- > To unsubscribe from this list: send the line "unsubscribe linux-tegra" in > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 10/13] memory: tegra: Add EMC (external memory controller) driver 2014-10-29 16:22 [PATCH v3 00/13] Tegra124 EMC (external memory controller) support Tomeu Vizoso ` (5 preceding siblings ...) 2014-10-29 16:22 ` [PATCH v3 08/13] ARM: tegra: Add EMC timings to Jetson TK1 " Tomeu Vizoso @ 2014-10-29 16:22 ` Tomeu Vizoso 2014-11-06 7:56 ` Alexandre Courbot 6 siblings, 1 reply; 23+ messages in thread From: Tomeu Vizoso @ 2014-10-29 16:22 UTC (permalink / raw) To: linux-tegra Cc: Javier Martinez Canillas, Mikko Perttunen, Tomeu Vizoso, Stephen Warren, Thierry Reding, Alexandre Courbot, Grant Likely, Rob Herring, Greg Kroah-Hartman, Paul Gortmaker, Maxime Ripard, Nicolas Ferre, Ivan Khoronzhuk, Alexandre Belloni, Scott Wood, Bharat Bhushan, Santosh Shilimkar, Prabhakar Kushwaha, linux-kernel, devicetree From: Mikko Perttunen <mperttunen@nvidia.com> Implements functionality needed to change the rate of the memory bus clock. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- v2: * Use subsys_initcall(), so it gets probed after the MC driver and before the CAR driver --- drivers/memory/Kconfig | 10 + drivers/memory/Makefile | 1 - drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/tegra124-emc.c | 1133 +++++++++++++++++++++++++++++++++++ include/soc/tegra/memory.h | 2 + 5 files changed, 1146 insertions(+), 1 deletion(-) create mode 100644 drivers/memory/tegra/tegra124-emc.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 6d91c27..3ba3aef 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -51,6 +51,16 @@ config MVEBU_DEVBUS Armada 370 and Armada XP. This controller allows to handle flash devices such as NOR, NAND, SRAM, and FPGA. +config TEGRA124_EMC + bool "Tegra124 External Memory Controller driver" + default y + depends on ARCH_TEGRA_124_SOC + help + This driver is for the External Memory Controller (EMC) found on + Tegra124 chips. The EMC controls the external DRAM on the board. + This driver is required to change memory timings / clock rate for + external memory. + config TEGRA20_MC bool "Tegra20 Memory Controller(MC) driver" default y diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 1c932e7..8e5ec8d 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -12,5 +12,4 @@ obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o - obj-$(CONFIG_ARCH_TEGRA) += tegra/ diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 51b9e8f..4e84bef 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-mc.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114-mc.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-mc.o obj-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124-mc.o +obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c new file mode 100644 index 0000000..8438de2 --- /dev/null +++ b/drivers/memory/tegra/tegra124-emc.c @@ -0,0 +1,1133 @@ +/* + * drivers/memory/tegra124-emc.c + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Author: + * Mikko Perttunen <mperttunen@nvidia.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/clk-provider.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/delay.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/sort.h> +#include <linux/string.h> + +#include <soc/tegra/fuse.h> +#include <soc/tegra/memory.h> + +#define EMC_FBIO_CFG5 0x104 +#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3 +#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 + +#define EMC_INTSTATUS 0x0 +#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) + +#define EMC_CFG 0xc +#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31) +#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30) +#define EMC_CFG_DRAM_ACPD BIT(29) +#define EMC_CFG_DYN_SREF BIT(28) +#define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18)) +#define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18) + +#define EMC_REFCTRL 0x20 +#define EMC_REFCTRL_DEV_SEL_SHIFT 0 +#define EMC_REFCTRL_ENABLE BIT(31) + +#define EMC_TIMING_CONTROL 0x28 +#define EMC_RC 0x2c +#define EMC_RFC 0x30 +#define EMC_RAS 0x34 +#define EMC_RP 0x38 +#define EMC_R2W 0x3c +#define EMC_W2R 0x40 +#define EMC_R2P 0x44 +#define EMC_W2P 0x48 +#define EMC_RD_RCD 0x4c +#define EMC_WR_RCD 0x50 +#define EMC_RRD 0x54 +#define EMC_REXT 0x58 +#define EMC_WDV 0x5c +#define EMC_QUSE 0x60 +#define EMC_QRST 0x64 +#define EMC_QSAFE 0x68 +#define EMC_RDV 0x6c +#define EMC_REFRESH 0x70 +#define EMC_BURST_REFRESH_NUM 0x74 +#define EMC_PDEX2WR 0x78 +#define EMC_PDEX2RD 0x7c +#define EMC_PCHG2PDEN 0x80 +#define EMC_ACT2PDEN 0x84 +#define EMC_AR2PDEN 0x88 +#define EMC_RW2PDEN 0x8c +#define EMC_TXSR 0x90 +#define EMC_TCKE 0x94 +#define EMC_TFAW 0x98 +#define EMC_TRPAB 0x9c +#define EMC_TCLKSTABLE 0xa0 +#define EMC_TCLKSTOP 0xa4 +#define EMC_TREFBW 0xa8 +#define EMC_ODT_WRITE 0xb0 +#define EMC_ODT_READ 0xb4 +#define EMC_WEXT 0xb8 +#define EMC_CTT 0xbc +#define EMC_RFC_SLR 0xc0 +#define EMC_MRS_WAIT_CNT2 0xc4 + +#define EMC_MRS_WAIT_CNT 0xc8 +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ + (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) +#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 +#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ + (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) + +#define EMC_MRS 0xcc +#define EMC_MODE_SET_DLL_RESET BIT(8) +#define EMC_MODE_SET_LONG_CNT BIT(26) +#define EMC_EMRS 0xd0 +#define EMC_REF 0xd4 +#define EMC_PRE 0xd8 + +#define EMC_SELF_REF 0xe0 +#define EMC_SELF_REF_CMD_ENABLED BIT(0) +#define EMC_SELF_REF_DEV_SEL_SHIFT 30 + +#define EMC_MRW 0xe8 + +#define EMC_MRR 0xec +#define EMC_MRR_MA_SHIFT 16 +#define LPDDR2_MR4_TEMP_SHIFT 0 + +#define EMC_XM2DQSPADCTRL3 0xf8 +#define EMC_FBIO_SPARE 0x100 + +#define EMC_FBIO_CFG6 0x114 +#define EMC_EMRS2 0x12c +#define EMC_MRW2 0x134 +#define EMC_MRW4 0x13c +#define EMC_EINPUT 0x14c +#define EMC_EINPUT_DURATION 0x150 +#define EMC_PUTERM_EXTRA 0x154 +#define EMC_TCKESR 0x158 +#define EMC_TPD 0x15c + +#define EMC_AUTO_CAL_CONFIG 0x2a4 +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31) +#define EMC_AUTO_CAL_INTERVAL 0x2a8 +#define EMC_AUTO_CAL_STATUS 0x2ac +#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31) +#define EMC_STATUS 0x2b4 +#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) + +#define EMC_CFG_2 0x2b8 +#define EMC_CFG_2_MODE_SHIFT 0 +#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6) + +#define EMC_CFG_DIG_DLL 0x2bc +#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 +#define EMC_RDV_MASK 0x2cc +#define EMC_WDV_MASK 0x2d0 +#define EMC_CTT_DURATION 0x2d8 +#define EMC_CTT_TERM_CTRL 0x2dc +#define EMC_ZCAL_INTERVAL 0x2e0 +#define EMC_ZCAL_WAIT_CNT 0x2e4 + +#define EMC_ZQ_CAL 0x2ec +#define EMC_ZQ_CAL_CMD BIT(0) +#define EMC_ZQ_CAL_LONG BIT(4) +#define EMC_ZQ_CAL_LONG_CMD_DEV0 \ + (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) +#define EMC_ZQ_CAL_LONG_CMD_DEV1 \ + (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) + +#define EMC_XM2CMDPADCTRL 0x2f0 +#define EMC_XM2DQSPADCTRL 0x2f8 +#define EMC_XM2DQSPADCTRL2 0x2fc +#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0) +#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5) +#define EMC_XM2DQPADCTRL 0x300 +#define EMC_XM2DQPADCTRL2 0x304 +#define EMC_XM2CLKPADCTRL 0x308 +#define EMC_XM2COMPPADCTRL 0x30c +#define EMC_XM2VTTGENPADCTRL 0x310 +#define EMC_XM2VTTGENPADCTRL2 0x314 +#define EMC_XM2VTTGENPADCTRL3 0x318 +#define EMC_XM2DQSPADCTRL4 0x320 +#define EMC_DLL_XFORM_DQS0 0x328 +#define EMC_DLL_XFORM_DQS1 0x32c +#define EMC_DLL_XFORM_DQS2 0x330 +#define EMC_DLL_XFORM_DQS3 0x334 +#define EMC_DLL_XFORM_DQS4 0x338 +#define EMC_DLL_XFORM_DQS5 0x33c +#define EMC_DLL_XFORM_DQS6 0x340 +#define EMC_DLL_XFORM_DQS7 0x344 +#define EMC_DLL_XFORM_QUSE0 0x348 +#define EMC_DLL_XFORM_QUSE1 0x34c +#define EMC_DLL_XFORM_QUSE2 0x350 +#define EMC_DLL_XFORM_QUSE3 0x354 +#define EMC_DLL_XFORM_QUSE4 0x358 +#define EMC_DLL_XFORM_QUSE5 0x35c +#define EMC_DLL_XFORM_QUSE6 0x360 +#define EMC_DLL_XFORM_QUSE7 0x364 +#define EMC_DLL_XFORM_DQ0 0x368 +#define EMC_DLL_XFORM_DQ1 0x36c +#define EMC_DLL_XFORM_DQ2 0x370 +#define EMC_DLL_XFORM_DQ3 0x374 +#define EMC_DLI_TRIM_TXDQS0 0x3a8 +#define EMC_DLI_TRIM_TXDQS1 0x3ac +#define EMC_DLI_TRIM_TXDQS2 0x3b0 +#define EMC_DLI_TRIM_TXDQS3 0x3b4 +#define EMC_DLI_TRIM_TXDQS4 0x3b8 +#define EMC_DLI_TRIM_TXDQS5 0x3bc +#define EMC_DLI_TRIM_TXDQS6 0x3c0 +#define EMC_DLI_TRIM_TXDQS7 0x3c4 +#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc +#define EMC_SEL_DPD_CTRL 0x3d8 +#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8) +#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5) +#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4) +#define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3) +#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2) +#define EMC_SEL_DPD_CTRL_DDR3_MASK \ + ((0xf << 2) | BIT(8)) +#define EMC_SEL_DPD_CTRL_MASK \ + ((0x3 << 2) | BIT(5) | BIT(8)) +#define EMC_PRE_REFRESH_REQ_CNT 0x3dc +#define EMC_DYN_SELF_REF_CONTROL 0x3e0 +#define EMC_TXSRDLL 0x3e4 +#define EMC_CCFIFO_ADDR 0x3e8 +#define EMC_CCFIFO_DATA 0x3ec +#define EMC_CCFIFO_STATUS 0x3f0 +#define EMC_CDB_CNTL_1 0x3f4 +#define EMC_CDB_CNTL_2 0x3f8 +#define EMC_XM2CLKPADCTRL2 0x3fc +#define EMC_AUTO_CAL_CONFIG2 0x458 +#define EMC_AUTO_CAL_CONFIG3 0x45c +#define EMC_IBDLY 0x468 +#define EMC_DLL_XFORM_ADDR0 0x46c +#define EMC_DLL_XFORM_ADDR1 0x470 +#define EMC_DLL_XFORM_ADDR2 0x474 +#define EMC_DSR_VTTGEN_DRV 0x47c +#define EMC_TXDSRVTTGEN 0x480 +#define EMC_XM2CMDPADCTRL4 0x484 +#define EMC_XM2CMDPADCTRL5 0x488 +#define EMC_DLL_XFORM_DQS8 0x4a0 +#define EMC_DLL_XFORM_DQS9 0x4a4 +#define EMC_DLL_XFORM_DQS10 0x4a8 +#define EMC_DLL_XFORM_DQS11 0x4ac +#define EMC_DLL_XFORM_DQS12 0x4b0 +#define EMC_DLL_XFORM_DQS13 0x4b4 +#define EMC_DLL_XFORM_DQS14 0x4b8 +#define EMC_DLL_XFORM_DQS15 0x4bc +#define EMC_DLL_XFORM_QUSE8 0x4c0 +#define EMC_DLL_XFORM_QUSE9 0x4c4 +#define EMC_DLL_XFORM_QUSE10 0x4c8 +#define EMC_DLL_XFORM_QUSE11 0x4cc +#define EMC_DLL_XFORM_QUSE12 0x4d0 +#define EMC_DLL_XFORM_QUSE13 0x4d4 +#define EMC_DLL_XFORM_QUSE14 0x4d8 +#define EMC_DLL_XFORM_QUSE15 0x4dc +#define EMC_DLL_XFORM_DQ4 0x4e0 +#define EMC_DLL_XFORM_DQ5 0x4e4 +#define EMC_DLL_XFORM_DQ6 0x4e8 +#define EMC_DLL_XFORM_DQ7 0x4ec +#define EMC_DLI_TRIM_TXDQS8 0x520 +#define EMC_DLI_TRIM_TXDQS9 0x524 +#define EMC_DLI_TRIM_TXDQS10 0x528 +#define EMC_DLI_TRIM_TXDQS11 0x52c +#define EMC_DLI_TRIM_TXDQS12 0x530 +#define EMC_DLI_TRIM_TXDQS13 0x534 +#define EMC_DLI_TRIM_TXDQS14 0x538 +#define EMC_DLI_TRIM_TXDQS15 0x53c +#define EMC_CDB_CNTL_3 0x540 +#define EMC_XM2DQSPADCTRL5 0x544 +#define EMC_XM2DQSPADCTRL6 0x548 +#define EMC_XM2DQPADCTRL3 0x54c +#define EMC_DLL_XFORM_ADDR3 0x550 +#define EMC_DLL_XFORM_ADDR4 0x554 +#define EMC_DLL_XFORM_ADDR5 0x558 +#define EMC_CFG_PIPE 0x560 +#define EMC_QPOP 0x564 +#define EMC_QUSE_WIDTH 0x568 +#define EMC_PUTERM_WIDTH 0x56c +#define EMC_BGBIAS_CTL0 0x570 +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3) +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2) +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1) +#define EMC_PUTERM_ADJ 0x574 + +#define DRAM_DEV_SEL_ALL 0 +#define DRAM_DEV_SEL_0 (2 << 30) +#define DRAM_DEV_SEL_1 (1 << 30) + +#define EMC_CFG_POWER_FEATURES_MASK \ + (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \ + EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN) +#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) +#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0) + +#define EMC_STATUS_UPDATE_TIMEOUT 1000 + +enum emc_dram_type { + DRAM_TYPE_DDR3 = 0, + DRAM_TYPE_DDR1 = 1, + DRAM_TYPE_LPDDR3 = 2, + DRAM_TYPE_DDR2 = 3 +}; + +enum emc_dll_change { + DLL_CHANGE_NONE, + DLL_CHANGE_ON, + DLL_CHANGE_OFF +}; + +static int t124_emc_burst_regs[] = { + EMC_RC, + EMC_RFC, + EMC_RFC_SLR, + EMC_RAS, + EMC_RP, + EMC_R2W, + EMC_W2R, + EMC_R2P, + EMC_W2P, + EMC_RD_RCD, + EMC_WR_RCD, + EMC_RRD, + EMC_REXT, + EMC_WEXT, + EMC_WDV, + EMC_WDV_MASK, + EMC_QUSE, + EMC_QUSE_WIDTH, + EMC_IBDLY, + EMC_EINPUT, + EMC_EINPUT_DURATION, + EMC_PUTERM_EXTRA, + EMC_PUTERM_WIDTH, + EMC_PUTERM_ADJ, + EMC_CDB_CNTL_1, + EMC_CDB_CNTL_2, + EMC_CDB_CNTL_3, + EMC_QRST, + EMC_QSAFE, + EMC_RDV, + EMC_RDV_MASK, + EMC_REFRESH, + EMC_BURST_REFRESH_NUM, + EMC_PRE_REFRESH_REQ_CNT, + EMC_PDEX2WR, + EMC_PDEX2RD, + EMC_PCHG2PDEN, + EMC_ACT2PDEN, + EMC_AR2PDEN, + EMC_RW2PDEN, + EMC_TXSR, + EMC_TXSRDLL, + EMC_TCKE, + EMC_TCKESR, + EMC_TPD, + EMC_TFAW, + EMC_TRPAB, + EMC_TCLKSTABLE, + EMC_TCLKSTOP, + EMC_TREFBW, + EMC_FBIO_CFG6, + EMC_ODT_WRITE, + EMC_ODT_READ, + EMC_FBIO_CFG5, + EMC_CFG_DIG_DLL, + EMC_CFG_DIG_DLL_PERIOD, + EMC_DLL_XFORM_DQS0, + EMC_DLL_XFORM_DQS1, + EMC_DLL_XFORM_DQS2, + EMC_DLL_XFORM_DQS3, + EMC_DLL_XFORM_DQS4, + EMC_DLL_XFORM_DQS5, + EMC_DLL_XFORM_DQS6, + EMC_DLL_XFORM_DQS7, + EMC_DLL_XFORM_DQS8, + EMC_DLL_XFORM_DQS9, + EMC_DLL_XFORM_DQS10, + EMC_DLL_XFORM_DQS11, + EMC_DLL_XFORM_DQS12, + EMC_DLL_XFORM_DQS13, + EMC_DLL_XFORM_DQS14, + EMC_DLL_XFORM_DQS15, + EMC_DLL_XFORM_QUSE0, + EMC_DLL_XFORM_QUSE1, + EMC_DLL_XFORM_QUSE2, + EMC_DLL_XFORM_QUSE3, + EMC_DLL_XFORM_QUSE4, + EMC_DLL_XFORM_QUSE5, + EMC_DLL_XFORM_QUSE6, + EMC_DLL_XFORM_QUSE7, + EMC_DLL_XFORM_ADDR0, + EMC_DLL_XFORM_ADDR1, + EMC_DLL_XFORM_ADDR2, + EMC_DLL_XFORM_ADDR3, + EMC_DLL_XFORM_ADDR4, + EMC_DLL_XFORM_ADDR5, + EMC_DLL_XFORM_QUSE8, + EMC_DLL_XFORM_QUSE9, + EMC_DLL_XFORM_QUSE10, + EMC_DLL_XFORM_QUSE11, + EMC_DLL_XFORM_QUSE12, + EMC_DLL_XFORM_QUSE13, + EMC_DLL_XFORM_QUSE14, + EMC_DLL_XFORM_QUSE15, + EMC_DLI_TRIM_TXDQS0, + EMC_DLI_TRIM_TXDQS1, + EMC_DLI_TRIM_TXDQS2, + EMC_DLI_TRIM_TXDQS3, + EMC_DLI_TRIM_TXDQS4, + EMC_DLI_TRIM_TXDQS5, + EMC_DLI_TRIM_TXDQS6, + EMC_DLI_TRIM_TXDQS7, + EMC_DLI_TRIM_TXDQS8, + EMC_DLI_TRIM_TXDQS9, + EMC_DLI_TRIM_TXDQS10, + EMC_DLI_TRIM_TXDQS11, + EMC_DLI_TRIM_TXDQS12, + EMC_DLI_TRIM_TXDQS13, + EMC_DLI_TRIM_TXDQS14, + EMC_DLI_TRIM_TXDQS15, + EMC_DLL_XFORM_DQ0, + EMC_DLL_XFORM_DQ1, + EMC_DLL_XFORM_DQ2, + EMC_DLL_XFORM_DQ3, + EMC_DLL_XFORM_DQ4, + EMC_DLL_XFORM_DQ5, + EMC_DLL_XFORM_DQ6, + EMC_DLL_XFORM_DQ7, + EMC_XM2CMDPADCTRL, + EMC_XM2CMDPADCTRL4, + EMC_XM2CMDPADCTRL5, + EMC_XM2DQSPADCTRL2, + EMC_XM2DQPADCTRL2, + EMC_XM2DQPADCTRL3, + EMC_XM2CLKPADCTRL, + EMC_XM2CLKPADCTRL2, + EMC_XM2COMPPADCTRL, + EMC_XM2VTTGENPADCTRL, + EMC_XM2VTTGENPADCTRL2, + EMC_XM2VTTGENPADCTRL3, + EMC_XM2DQSPADCTRL3, + EMC_XM2DQSPADCTRL4, + EMC_XM2DQSPADCTRL5, + EMC_XM2DQSPADCTRL6, + EMC_DSR_VTTGEN_DRV, + EMC_TXDSRVTTGEN, + EMC_FBIO_SPARE, + EMC_ZCAL_INTERVAL, + EMC_ZCAL_WAIT_CNT, + EMC_MRS_WAIT_CNT, + EMC_MRS_WAIT_CNT2, + EMC_CTT, + EMC_CTT_DURATION, + EMC_CFG_PIPE, + EMC_DYN_SELF_REF_CONTROL, + EMC_QPOP +}; + +struct emc_timing { + unsigned long rate; + + /* Store EMC burst data in a union to minimize mistakes. This allows + * us to use the same burst data lists as used by the downstream and + * ChromeOS kernels. + */ + union { + u32 emc_burst_data[ARRAY_SIZE(t124_emc_burst_regs)]; + struct { + u32 __pad0[121]; + u32 emc_xm2dqspadctrl2; + u32 __pad1[15]; + u32 emc_zcal_interval; + u32 __pad2[1]; + u32 emc_mrs_wait_cnt; + }; + }; + + u32 emc_zcal_cnt_long; + u32 emc_auto_cal_interval; + u32 emc_ctt_term_ctrl; + u32 emc_cfg; + u32 emc_cfg_2; + u32 emc_sel_dpd_ctrl; + u32 __emc_cfg_dig_dll; + u32 emc_bgbias_ctl0; + u32 emc_auto_cal_config2; + u32 emc_auto_cal_config3; + u32 emc_auto_cal_config; + u32 emc_mode_reset; + u32 emc_mode_1; + u32 emc_mode_2; + u32 emc_mode_4; +}; + +struct tegra_emc { + struct platform_device *pdev; + + struct tegra_mc *mc; + + void __iomem *emc_regs; + + enum emc_dram_type dram_type; + u8 dram_num; + + struct emc_timing last_timing; + struct emc_timing *timings; + unsigned int num_timings; + + bool changing_timing; +}; + +/* * * * * * * * * * * * * * * * * * * * * * * * * * + * Timing change sequence functions * + * * * * * * * * * * * * * * * * * * * * * * * * * */ + +static void emc_ccfifo_writel(struct tegra_emc *tegra, u32 val, + unsigned long offs) +{ + writel(val, tegra->emc_regs + EMC_CCFIFO_DATA); + writel(offs, tegra->emc_regs + EMC_CCFIFO_ADDR); +} + +static void emc_seq_update_timing(struct tegra_emc *tegra) +{ + int i; + + writel(1, tegra->emc_regs + EMC_TIMING_CONTROL); + + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { + if (!(readl(tegra->emc_regs + EMC_STATUS) & + EMC_STATUS_TIMING_UPDATE_STALLED)) + return; + } + + dev_err(&tegra->pdev->dev, "timing update failed\n"); +} + +static void emc_seq_disable_auto_cal(struct tegra_emc *tegra) +{ + int i; + + writel(0, tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); + + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { + if (!(readl(tegra->emc_regs + EMC_AUTO_CAL_STATUS) & + EMC_AUTO_CAL_STATUS_ACTIVE)) + return; + } + + dev_err(&tegra->pdev->dev, "auto cal disable failed\n"); +} + +static void emc_seq_wait_clkchange(struct tegra_emc *tegra) +{ + int i; + + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { + if (readl(tegra->emc_regs + EMC_INTSTATUS) & + EMC_INTSTATUS_CLKCHANGE_COMPLETE) + return; + } + + dev_err(&tegra->pdev->dev, "clkchange failed\n"); +} + +static void emc_prepare_timing_change(struct tegra_emc *tegra, + const struct emc_timing *timing) +{ + u32 val, val2; + bool update = false; + int pre_wait = 0; + int i; + enum emc_dll_change dll_change; + + if ((tegra->last_timing.emc_mode_1 & 0x1) == (timing->emc_mode_1 & 1)) + dll_change = DLL_CHANGE_NONE; + else if (timing->emc_mode_1 & 1) + dll_change = DLL_CHANGE_ON; + else + dll_change = DLL_CHANGE_OFF; + + /* Clear CLKCHANGE_COMPLETE interrupts */ + + writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, + tegra->emc_regs + EMC_INTSTATUS); + + /* Disable dynamic self-refresh */ + + val = readl(tegra->emc_regs + EMC_CFG); + if (val & EMC_CFG_PWR_MASK) { + val &= ~EMC_CFG_POWER_FEATURES_MASK; + writel(val, tegra->emc_regs + EMC_CFG); + + pre_wait = 5; + } + + /* Disable SEL_DPD_CTRL for clock change */ + + val = readl(tegra->emc_regs + EMC_SEL_DPD_CTRL); + if (val & (tegra->dram_type == DRAM_TYPE_DDR3 ? + EMC_SEL_DPD_CTRL_DDR3_MASK : EMC_SEL_DPD_CTRL_MASK)) { + val &= ~(EMC_SEL_DPD_CTRL_DATA_SEL_DPD | + EMC_SEL_DPD_CTRL_ODT_SEL_DPD | + EMC_SEL_DPD_CTRL_CA_SEL_DPD | + EMC_SEL_DPD_CTRL_CLK_SEL_DPD); + if (tegra->dram_type == DRAM_TYPE_DDR3) + val &= ~EMC_SEL_DPD_CTRL_RESET_SEL_DPD; + writel(val, tegra->emc_regs + EMC_SEL_DPD_CTRL); + } + + /* Prepare DQ/DQS for clock change */ + + val = readl(tegra->emc_regs + EMC_BGBIAS_CTL0); + val2 = tegra->last_timing.emc_bgbias_ctl0; + if (!(timing->emc_bgbias_ctl0 & + EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) && + (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) { + val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX; + update = true; + } + + if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) || + (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) { + update = true; + } + + if (update) { + writel(val2, tegra->emc_regs + EMC_BGBIAS_CTL0); + if (pre_wait < 5) + pre_wait = 5; + } + + update = false; + val = readl(tegra->emc_regs + EMC_XM2DQSPADCTRL2); + if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && + !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) { + val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE; + update = true; + } + + if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && + !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) { + val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE; + update = true; + } + + if (update) { + writel(val, tegra->emc_regs + EMC_XM2DQSPADCTRL2); + if (pre_wait < 30) + pre_wait = 30; + } + + /* Wait to settle */ + + if (pre_wait) { + emc_seq_update_timing(tegra); + udelay(pre_wait); + } + + /* Program CTT_TERM control */ + + if (tegra->last_timing.emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { + emc_seq_disable_auto_cal(tegra); + writel(timing->emc_ctt_term_ctrl, + tegra->emc_regs + EMC_CTT_TERM_CTRL); + emc_seq_update_timing(tegra); + } + + /* Program burst shadow registers */ + + for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) + __raw_writel(timing->emc_burst_data[i], + tegra->emc_regs + t124_emc_burst_regs[i]); + + tegra_mc_write_emem_configuration(tegra->mc, timing->rate); + + val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; + emc_ccfifo_writel(tegra, val, EMC_CFG); + + /* Program AUTO_CAL_CONFIG */ + + if (timing->emc_auto_cal_config2 != + tegra->last_timing.emc_auto_cal_config2) + emc_ccfifo_writel(tegra, timing->emc_auto_cal_config2, + EMC_AUTO_CAL_CONFIG2); + if (timing->emc_auto_cal_config3 != + tegra->last_timing.emc_auto_cal_config3) + emc_ccfifo_writel(tegra, timing->emc_auto_cal_config3, + EMC_AUTO_CAL_CONFIG3); + if (timing->emc_auto_cal_config != + tegra->last_timing.emc_auto_cal_config) { + val = timing->emc_auto_cal_config; + val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START; + emc_ccfifo_writel(tegra, val, EMC_AUTO_CAL_CONFIG); + } + + /* DDR3: predict MRS long wait count */ + + if (tegra->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) { + u32 cnt = 32; + + if (timing->emc_zcal_interval != 0 && + tegra->last_timing.emc_zcal_interval == 0) + cnt -= tegra->dram_num * 256; + + val = timing->emc_mrs_wait_cnt + & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK + >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT; + if (cnt < val) + cnt = val; + + val = timing->emc_mrs_wait_cnt + & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; + val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) + & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; + + writel(val, tegra->emc_regs + EMC_MRS_WAIT_CNT); + } + + val = timing->emc_cfg_2; + val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR; + emc_ccfifo_writel(tegra, val, EMC_CFG_2); + + /* DDR3: Turn off DLL and enter self-refresh */ + + if (tegra->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_EMRS); + + /* Disable refresh controller */ + + emc_ccfifo_writel(tegra, EMC_REFCTRL_DEV_SEL(tegra->dram_num), + EMC_REFCTRL); + if (tegra->dram_type == DRAM_TYPE_DDR3) + emc_ccfifo_writel(tegra, + EMC_DRAM_DEV_SEL(tegra->dram_num) + | EMC_SELF_REF_CMD_ENABLED, + EMC_SELF_REF); + + /* Flow control marker */ + + emc_ccfifo_writel(tegra, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); + + /* DDR3: Exit self-refresh */ + + if (tegra->dram_type == DRAM_TYPE_DDR3) + emc_ccfifo_writel(tegra, + EMC_DRAM_DEV_SEL(tegra->dram_num), + EMC_SELF_REF); + emc_ccfifo_writel(tegra, + EMC_REFCTRL_DEV_SEL(tegra->dram_num) + | EMC_REFCTRL_ENABLE, + EMC_REFCTRL); + + /* Set DRAM mode registers */ + + if (tegra->dram_type == DRAM_TYPE_DDR3) { + if (timing->emc_mode_1 != tegra->last_timing.emc_mode_1) + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_EMRS); + if (timing->emc_mode_2 != tegra->last_timing.emc_mode_2) + emc_ccfifo_writel(tegra, timing->emc_mode_2, EMC_EMRS2); + + if ((timing->emc_mode_reset != + tegra->last_timing.emc_mode_reset) || + dll_change == DLL_CHANGE_ON) { + val = timing->emc_mode_reset; + if (dll_change == DLL_CHANGE_ON) { + val |= EMC_MODE_SET_DLL_RESET; + val |= EMC_MODE_SET_LONG_CNT; + } else { + val &= ~EMC_MODE_SET_DLL_RESET; + } + emc_ccfifo_writel(tegra, val, EMC_MRS); + } + } else { + if (timing->emc_mode_2 != tegra->last_timing.emc_mode_2) + emc_ccfifo_writel(tegra, timing->emc_mode_2, EMC_MRW2); + if (timing->emc_mode_1 != tegra->last_timing.emc_mode_1) + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_MRW); + if (timing->emc_mode_4 != tegra->last_timing.emc_mode_4) + emc_ccfifo_writel(tegra, timing->emc_mode_4, EMC_MRW4); + } + + /* Issue ZCAL command if turning ZCAL on */ + + if (timing->emc_zcal_interval != 0 && + tegra->last_timing.emc_zcal_interval == 0) { + emc_ccfifo_writel(tegra, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); + if (tegra->dram_num > 1) + emc_ccfifo_writel(tegra, EMC_ZQ_CAL_LONG_CMD_DEV1, + EMC_ZQ_CAL); + } + + /* Write to RO register to remove stall after change */ + + emc_ccfifo_writel(tegra, 0, EMC_CCFIFO_STATUS); + + if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) + emc_ccfifo_writel(tegra, timing->emc_cfg_2, EMC_CFG_2); + + /* Disable AUTO_CAL for clock change */ + + emc_seq_disable_auto_cal(tegra); + + /* Read register to wait until programming has settled */ + + readl(tegra->emc_regs + EMC_INTSTATUS); +} + +static void emc_complete_timing_change(struct tegra_emc *tegra, + const struct emc_timing *timing) +{ + u32 val; + + /* Wait until the state machine has settled */ + + emc_seq_wait_clkchange(tegra); + + /* Restore AUTO_CAL */ + + if (timing->emc_ctt_term_ctrl != tegra->last_timing.emc_ctt_term_ctrl) + writel(timing->emc_auto_cal_interval, + tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); + + /* Restore dynamic self-refresh */ + + if (timing->emc_cfg & EMC_CFG_PWR_MASK) + writel(timing->emc_cfg, tegra->emc_regs + EMC_CFG); + + /* Set ZCAL wait count */ + + writel(timing->emc_zcal_cnt_long, tegra->emc_regs + EMC_ZCAL_WAIT_CNT); + + /* LPDDR3: Turn off BGBIAS if low frequency */ + + if (tegra->dram_type == DRAM_TYPE_LPDDR3 && + timing->emc_bgbias_ctl0 & + EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) { + val = timing->emc_bgbias_ctl0; + val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN; + val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD; + writel(val, tegra->emc_regs + EMC_BGBIAS_CTL0); + } else { + if (tegra->dram_type == DRAM_TYPE_DDR3 && + readl(tegra->emc_regs + EMC_BGBIAS_CTL0) != + timing->emc_bgbias_ctl0) { + writel(timing->emc_bgbias_ctl0, + tegra->emc_regs + EMC_BGBIAS_CTL0); + } + + writel(timing->emc_auto_cal_interval, + tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); + } + + /* Wait for timing to settle */ + + udelay(2); + + /* Reprogram SEL_DPD_CTRL */ + + writel(timing->emc_sel_dpd_ctrl, tegra->emc_regs + EMC_SEL_DPD_CTRL); + emc_seq_update_timing(tegra); + + tegra->last_timing = *timing; +} + +/* * * * * * * * * * * * * * * * * * * * * * * * * * + * Initialization and deinitialization * + * * * * * * * * * * * * * * * * * * * * * * * * * */ + +static void emc_read_current_timing(struct tegra_emc *tegra, + struct emc_timing *timing) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(t124_emc_burst_regs); ++i) + timing->emc_burst_data[i] = + readl(tegra->emc_regs + t124_emc_burst_regs[i]); + + timing->emc_cfg = readl(tegra->emc_regs + EMC_CFG); + + timing->emc_auto_cal_interval = 0; + timing->emc_zcal_cnt_long = 0; + timing->emc_mode_1 = 0; + timing->emc_mode_2 = 0; + timing->emc_mode_4 = 0; + timing->emc_mode_reset = 0; +} + +static int emc_init(struct tegra_emc *tegra) +{ + tegra->dram_type = readl(tegra->emc_regs + EMC_FBIO_CFG5); + tegra->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; + tegra->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; + + tegra->dram_num = tegra_mc_get_emem_device_count(tegra->mc); + + emc_read_current_timing(tegra, &tegra->last_timing); + + tegra->changing_timing = false; + + return 0; +} + +static int load_one_timing_from_dt(struct tegra_emc *tegra, + struct emc_timing *timing, + struct device_node *node) +{ + int err; + u32 tmp; + + err = of_property_read_u32(node, "clock-frequency", &tmp); + if (err) { + dev_err(&tegra->pdev->dev, + "timing %s: failed to read rate\n", node->name); + return err; + } + + timing->rate = tmp; + + err = of_property_read_u32_array(node, "nvidia,emc-configuration", + timing->emc_burst_data, + ARRAY_SIZE(timing->emc_burst_data)); + if (err) { + dev_err(&tegra->pdev->dev, + "timing %s: failed to read emc burst data\n", + node->name); + return err; + } + +#define EMC_READ_PROP(prop, dtprop) { \ + err = of_property_read_u32(node, dtprop, &timing->prop); \ + if (err) { \ + dev_err(&tegra->pdev->dev, \ + "timing %s: failed to read " #prop "\n", \ + node->name); \ + return err; \ + } \ +} + + EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") + EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") + EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") + EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") + EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") + EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") + EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0") + EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2") + EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3") + EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config") + EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset") + EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1") + EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2") + EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4") + +#undef EMC_READ_PROP + + return 0; +} + +static int cmp_timings(const void *_a, const void *_b) +{ + const struct emc_timing *a = _a; + const struct emc_timing *b = _b; + + if (a->rate < b->rate) + return -1; + else if (a->rate == b->rate) + return 0; + else + return 1; +} + +static int load_timings_from_dt(struct tegra_emc *tegra, + struct device_node *node) +{ + struct device_node *child; + int child_count = of_get_child_count(node); + int i = 0, err; + + tegra->timings = devm_kzalloc(&tegra->pdev->dev, + sizeof(struct emc_timing) * child_count, + GFP_KERNEL); + if (!tegra->timings) + return -ENOMEM; + + tegra->num_timings = child_count; + + for_each_child_of_node(node, child) { + struct emc_timing *timing = tegra->timings + (i++); + + err = load_one_timing_from_dt(tegra, timing, child); + if (err) + return err; + } + + sort(tegra->timings, tegra->num_timings, sizeof(struct emc_timing), + cmp_timings, NULL); + + return 0; +} + +static const struct of_device_id tegra_emc_of_match[] = { + { .compatible = "nvidia,tegra124-emc" }, + {} +}; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); + +static struct tegra_emc *emc_instance; + +void tegra_emc_prepare_timing_change(unsigned long rate) +{ + int i; + + if (!emc_instance) + return; + + for (i = 0; i < emc_instance->num_timings; ++i) { + if (emc_instance->timings[i].rate == rate) + break; + } + + if (i == emc_instance->num_timings) + return; + + emc_prepare_timing_change(emc_instance, emc_instance->timings + i); +} + +void tegra_emc_complete_timing_change(unsigned long rate) +{ + int i; + + if (!emc_instance) + return; + + for (i = 0; i < emc_instance->num_timings; ++i) { + if (emc_instance->timings[i].rate == rate) + break; + } + + if (i == emc_instance->num_timings) + return; + + emc_complete_timing_change(emc_instance, emc_instance->timings + i); +} + +static int tegra_emc_probe(struct platform_device *pdev) +{ + struct tegra_emc *tegra; + struct device_node *node; + struct platform_device *mc_pdev; + struct resource *res; + u32 ram_code, node_ram_code; + int err; + + tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); + if (!tegra) + return -ENOMEM; + + tegra->pdev = pdev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + tegra->emc_regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tegra->emc_regs)) { + dev_err(&pdev->dev, "failed to map EMC regs\n"); + return PTR_ERR(tegra->emc_regs); + } + + node = of_parse_phandle(pdev->dev.of_node, + "nvidia,memory-controller", 0); + if (!node) { + dev_err(&pdev->dev, "could not get memory controller\n"); + return -ENOENT; + } + + mc_pdev = of_find_device_by_node(node); + if (!mc_pdev) + return -ENOENT; + + tegra->mc = platform_get_drvdata(mc_pdev); + if (!tegra->mc) + return -ENOENT; + + of_node_put(node); + + ram_code = tegra_read_ram_code(); + + tegra->num_timings = 0; + + for_each_child_of_node(pdev->dev.of_node, node) { + if (strcmp(node->name, "timings")) + continue; + + err = of_property_read_u32(node, "nvidia,ram-code", + &node_ram_code); + if (err) { + dev_warn(&pdev->dev, + "skipping timing without ram-code\n"); + continue; + } + + if (node_ram_code != ram_code) + continue; + + err = load_timings_from_dt(tegra, node); + if (err) + return err; + break; + } + + if (tegra->num_timings == 0) + dev_warn(&pdev->dev, "no memory timings registered\n"); + + err = emc_init(tegra); + if (err) { + dev_err(&pdev->dev, "initialization failed: %d\n", err); + return err; + } + + platform_set_drvdata(pdev, tegra); + + emc_instance = tegra; + + return 0; +}; + +static struct platform_driver tegra_emc_driver = { + .probe = tegra_emc_probe, + .driver = { + .name = "tegra-emc", + .of_match_table = tegra_emc_of_match, + }, +}; + +static int tegra_emc_init(void) +{ + return platform_driver_register(&tegra_emc_driver); +} +subsys_initcall(tegra_emc_init); + +MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); +MODULE_DESCRIPTION("Tegra124 EMC memory driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/soc/tegra/memory.h b/include/soc/tegra/memory.h index f307516..0e0a2e9 100644 --- a/include/soc/tegra/memory.h +++ b/include/soc/tegra/memory.h @@ -13,5 +13,7 @@ struct tegra_mc; void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate); int tegra_mc_get_emem_device_count(struct tegra_mc *mc); +void tegra_emc_prepare_timing_change(unsigned long rate); +void tegra_emc_complete_timing_change(unsigned long rate); #endif /* __SOC_TEGRA_MEMORY_H__ */ -- 1.9.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v3 10/13] memory: tegra: Add EMC (external memory controller) driver 2014-10-29 16:22 ` [PATCH v3 10/13] memory: tegra: Add EMC (external memory controller) driver Tomeu Vizoso @ 2014-11-06 7:56 ` Alexandre Courbot [not found] ` <545B29AA.8030006-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Alexandre Courbot @ 2014-11-06 7:56 UTC (permalink / raw) To: Tomeu Vizoso, linux-tegra Cc: Javier Martinez Canillas, Mikko Perttunen, Stephen Warren, Thierry Reding, Alexandre Courbot, Grant Likely, Rob Herring, Greg Kroah-Hartman, Paul Gortmaker, Maxime Ripard, Nicolas Ferre, Ivan Khoronzhuk, Alexandre Belloni, Scott Wood, Bharat Bhushan, Santosh Shilimkar, Prabhakar Kushwaha, linux-kernel, devicetree On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: > From: Mikko Perttunen <mperttunen@nvidia.com> > > Implements functionality needed to change the rate of the memory bus clock. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> > > --- > > v2: * Use subsys_initcall(), so it gets probed after the MC driver and > before the CAR driver > --- > drivers/memory/Kconfig | 10 + > drivers/memory/Makefile | 1 - > drivers/memory/tegra/Makefile | 1 + > drivers/memory/tegra/tegra124-emc.c | 1133 +++++++++++++++++++++++++++++++++++ > include/soc/tegra/memory.h | 2 + > 5 files changed, 1146 insertions(+), 1 deletion(-) > create mode 100644 drivers/memory/tegra/tegra124-emc.c > > diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig > index 6d91c27..3ba3aef 100644 > --- a/drivers/memory/Kconfig > +++ b/drivers/memory/Kconfig > @@ -51,6 +51,16 @@ config MVEBU_DEVBUS > Armada 370 and Armada XP. This controller allows to handle flash > devices such as NOR, NAND, SRAM, and FPGA. > > +config TEGRA124_EMC > + bool "Tegra124 External Memory Controller driver" > + default y > + depends on ARCH_TEGRA_124_SOC > + help > + This driver is for the External Memory Controller (EMC) found on > + Tegra124 chips. The EMC controls the external DRAM on the board. > + This driver is required to change memory timings / clock rate for > + external memory. > + > config TEGRA20_MC > bool "Tegra20 Memory Controller(MC) driver" > default y > diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile > index 1c932e7..8e5ec8d 100644 > --- a/drivers/memory/Makefile > +++ b/drivers/memory/Makefile > @@ -12,5 +12,4 @@ obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o > obj-$(CONFIG_FSL_IFC) += fsl_ifc.o > obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o > obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o > - > obj-$(CONFIG_ARCH_TEGRA) += tegra/ > diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile > index 51b9e8f..4e84bef 100644 > --- a/drivers/memory/tegra/Makefile > +++ b/drivers/memory/tegra/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-mc.o > obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114-mc.o > obj-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-mc.o > obj-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124-mc.o > +obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o > diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c > new file mode 100644 > index 0000000..8438de2 > --- /dev/null > +++ b/drivers/memory/tegra/tegra124-emc.c > @@ -0,0 +1,1133 @@ > +/* > + * drivers/memory/tegra124-emc.c > + * > + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. > + * > + * Author: > + * Mikko Perttunen <mperttunen@nvidia.com> > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/clk.h> > +#include <linux/clkdev.h> > +#include <linux/delay.h> > +#include <linux/module.h> > +#include <linux/of_address.h> > +#include <linux/of_platform.h> > +#include <linux/platform_device.h> > +#include <linux/sort.h> > +#include <linux/string.h> > + > +#include <soc/tegra/fuse.h> > +#include <soc/tegra/memory.h> > + > +#define EMC_FBIO_CFG5 0x104 > +#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3 > +#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 > + > +#define EMC_INTSTATUS 0x0 > +#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) > + > +#define EMC_CFG 0xc > +#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31) > +#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30) > +#define EMC_CFG_DRAM_ACPD BIT(29) > +#define EMC_CFG_DYN_SREF BIT(28) > +#define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18)) > +#define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18) > + > +#define EMC_REFCTRL 0x20 > +#define EMC_REFCTRL_DEV_SEL_SHIFT 0 > +#define EMC_REFCTRL_ENABLE BIT(31) > + > +#define EMC_TIMING_CONTROL 0x28 > +#define EMC_RC 0x2c > +#define EMC_RFC 0x30 > +#define EMC_RAS 0x34 > +#define EMC_RP 0x38 > +#define EMC_R2W 0x3c > +#define EMC_W2R 0x40 > +#define EMC_R2P 0x44 > +#define EMC_W2P 0x48 > +#define EMC_RD_RCD 0x4c > +#define EMC_WR_RCD 0x50 > +#define EMC_RRD 0x54 > +#define EMC_REXT 0x58 > +#define EMC_WDV 0x5c > +#define EMC_QUSE 0x60 > +#define EMC_QRST 0x64 > +#define EMC_QSAFE 0x68 > +#define EMC_RDV 0x6c > +#define EMC_REFRESH 0x70 > +#define EMC_BURST_REFRESH_NUM 0x74 > +#define EMC_PDEX2WR 0x78 > +#define EMC_PDEX2RD 0x7c > +#define EMC_PCHG2PDEN 0x80 > +#define EMC_ACT2PDEN 0x84 > +#define EMC_AR2PDEN 0x88 > +#define EMC_RW2PDEN 0x8c > +#define EMC_TXSR 0x90 > +#define EMC_TCKE 0x94 > +#define EMC_TFAW 0x98 > +#define EMC_TRPAB 0x9c > +#define EMC_TCLKSTABLE 0xa0 > +#define EMC_TCLKSTOP 0xa4 > +#define EMC_TREFBW 0xa8 > +#define EMC_ODT_WRITE 0xb0 > +#define EMC_ODT_READ 0xb4 > +#define EMC_WEXT 0xb8 > +#define EMC_CTT 0xbc > +#define EMC_RFC_SLR 0xc0 > +#define EMC_MRS_WAIT_CNT2 0xc4 > + > +#define EMC_MRS_WAIT_CNT 0xc8 > +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 > +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ > + (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) > +#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 > +#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ > + (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) > + > +#define EMC_MRS 0xcc > +#define EMC_MODE_SET_DLL_RESET BIT(8) > +#define EMC_MODE_SET_LONG_CNT BIT(26) > +#define EMC_EMRS 0xd0 > +#define EMC_REF 0xd4 > +#define EMC_PRE 0xd8 > + > +#define EMC_SELF_REF 0xe0 > +#define EMC_SELF_REF_CMD_ENABLED BIT(0) > +#define EMC_SELF_REF_DEV_SEL_SHIFT 30 > + > +#define EMC_MRW 0xe8 > + > +#define EMC_MRR 0xec > +#define EMC_MRR_MA_SHIFT 16 > +#define LPDDR2_MR4_TEMP_SHIFT 0 > + > +#define EMC_XM2DQSPADCTRL3 0xf8 > +#define EMC_FBIO_SPARE 0x100 > + > +#define EMC_FBIO_CFG6 0x114 > +#define EMC_EMRS2 0x12c > +#define EMC_MRW2 0x134 > +#define EMC_MRW4 0x13c > +#define EMC_EINPUT 0x14c > +#define EMC_EINPUT_DURATION 0x150 > +#define EMC_PUTERM_EXTRA 0x154 > +#define EMC_TCKESR 0x158 > +#define EMC_TPD 0x15c > + > +#define EMC_AUTO_CAL_CONFIG 0x2a4 > +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31) > +#define EMC_AUTO_CAL_INTERVAL 0x2a8 > +#define EMC_AUTO_CAL_STATUS 0x2ac > +#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31) > +#define EMC_STATUS 0x2b4 > +#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) > + > +#define EMC_CFG_2 0x2b8 > +#define EMC_CFG_2_MODE_SHIFT 0 > +#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6) > + > +#define EMC_CFG_DIG_DLL 0x2bc > +#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 > +#define EMC_RDV_MASK 0x2cc > +#define EMC_WDV_MASK 0x2d0 > +#define EMC_CTT_DURATION 0x2d8 > +#define EMC_CTT_TERM_CTRL 0x2dc > +#define EMC_ZCAL_INTERVAL 0x2e0 > +#define EMC_ZCAL_WAIT_CNT 0x2e4 > + > +#define EMC_ZQ_CAL 0x2ec > +#define EMC_ZQ_CAL_CMD BIT(0) > +#define EMC_ZQ_CAL_LONG BIT(4) > +#define EMC_ZQ_CAL_LONG_CMD_DEV0 \ > + (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) > +#define EMC_ZQ_CAL_LONG_CMD_DEV1 \ > + (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) > + > +#define EMC_XM2CMDPADCTRL 0x2f0 > +#define EMC_XM2DQSPADCTRL 0x2f8 > +#define EMC_XM2DQSPADCTRL2 0x2fc > +#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0) > +#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5) > +#define EMC_XM2DQPADCTRL 0x300 > +#define EMC_XM2DQPADCTRL2 0x304 > +#define EMC_XM2CLKPADCTRL 0x308 > +#define EMC_XM2COMPPADCTRL 0x30c > +#define EMC_XM2VTTGENPADCTRL 0x310 > +#define EMC_XM2VTTGENPADCTRL2 0x314 > +#define EMC_XM2VTTGENPADCTRL3 0x318 > +#define EMC_XM2DQSPADCTRL4 0x320 > +#define EMC_DLL_XFORM_DQS0 0x328 > +#define EMC_DLL_XFORM_DQS1 0x32c > +#define EMC_DLL_XFORM_DQS2 0x330 > +#define EMC_DLL_XFORM_DQS3 0x334 > +#define EMC_DLL_XFORM_DQS4 0x338 > +#define EMC_DLL_XFORM_DQS5 0x33c > +#define EMC_DLL_XFORM_DQS6 0x340 > +#define EMC_DLL_XFORM_DQS7 0x344 > +#define EMC_DLL_XFORM_QUSE0 0x348 > +#define EMC_DLL_XFORM_QUSE1 0x34c > +#define EMC_DLL_XFORM_QUSE2 0x350 > +#define EMC_DLL_XFORM_QUSE3 0x354 > +#define EMC_DLL_XFORM_QUSE4 0x358 > +#define EMC_DLL_XFORM_QUSE5 0x35c > +#define EMC_DLL_XFORM_QUSE6 0x360 > +#define EMC_DLL_XFORM_QUSE7 0x364 > +#define EMC_DLL_XFORM_DQ0 0x368 > +#define EMC_DLL_XFORM_DQ1 0x36c > +#define EMC_DLL_XFORM_DQ2 0x370 > +#define EMC_DLL_XFORM_DQ3 0x374 > +#define EMC_DLI_TRIM_TXDQS0 0x3a8 > +#define EMC_DLI_TRIM_TXDQS1 0x3ac > +#define EMC_DLI_TRIM_TXDQS2 0x3b0 > +#define EMC_DLI_TRIM_TXDQS3 0x3b4 > +#define EMC_DLI_TRIM_TXDQS4 0x3b8 > +#define EMC_DLI_TRIM_TXDQS5 0x3bc > +#define EMC_DLI_TRIM_TXDQS6 0x3c0 > +#define EMC_DLI_TRIM_TXDQS7 0x3c4 > +#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc > +#define EMC_SEL_DPD_CTRL 0x3d8 > +#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8) > +#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5) > +#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4) > +#define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3) > +#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2) > +#define EMC_SEL_DPD_CTRL_DDR3_MASK \ > + ((0xf << 2) | BIT(8)) > +#define EMC_SEL_DPD_CTRL_MASK \ > + ((0x3 << 2) | BIT(5) | BIT(8)) > +#define EMC_PRE_REFRESH_REQ_CNT 0x3dc > +#define EMC_DYN_SELF_REF_CONTROL 0x3e0 > +#define EMC_TXSRDLL 0x3e4 > +#define EMC_CCFIFO_ADDR 0x3e8 > +#define EMC_CCFIFO_DATA 0x3ec > +#define EMC_CCFIFO_STATUS 0x3f0 > +#define EMC_CDB_CNTL_1 0x3f4 > +#define EMC_CDB_CNTL_2 0x3f8 > +#define EMC_XM2CLKPADCTRL2 0x3fc > +#define EMC_AUTO_CAL_CONFIG2 0x458 > +#define EMC_AUTO_CAL_CONFIG3 0x45c > +#define EMC_IBDLY 0x468 > +#define EMC_DLL_XFORM_ADDR0 0x46c > +#define EMC_DLL_XFORM_ADDR1 0x470 > +#define EMC_DLL_XFORM_ADDR2 0x474 > +#define EMC_DSR_VTTGEN_DRV 0x47c > +#define EMC_TXDSRVTTGEN 0x480 > +#define EMC_XM2CMDPADCTRL4 0x484 > +#define EMC_XM2CMDPADCTRL5 0x488 > +#define EMC_DLL_XFORM_DQS8 0x4a0 > +#define EMC_DLL_XFORM_DQS9 0x4a4 > +#define EMC_DLL_XFORM_DQS10 0x4a8 > +#define EMC_DLL_XFORM_DQS11 0x4ac > +#define EMC_DLL_XFORM_DQS12 0x4b0 > +#define EMC_DLL_XFORM_DQS13 0x4b4 > +#define EMC_DLL_XFORM_DQS14 0x4b8 > +#define EMC_DLL_XFORM_DQS15 0x4bc > +#define EMC_DLL_XFORM_QUSE8 0x4c0 > +#define EMC_DLL_XFORM_QUSE9 0x4c4 > +#define EMC_DLL_XFORM_QUSE10 0x4c8 > +#define EMC_DLL_XFORM_QUSE11 0x4cc > +#define EMC_DLL_XFORM_QUSE12 0x4d0 > +#define EMC_DLL_XFORM_QUSE13 0x4d4 > +#define EMC_DLL_XFORM_QUSE14 0x4d8 > +#define EMC_DLL_XFORM_QUSE15 0x4dc > +#define EMC_DLL_XFORM_DQ4 0x4e0 > +#define EMC_DLL_XFORM_DQ5 0x4e4 > +#define EMC_DLL_XFORM_DQ6 0x4e8 > +#define EMC_DLL_XFORM_DQ7 0x4ec > +#define EMC_DLI_TRIM_TXDQS8 0x520 > +#define EMC_DLI_TRIM_TXDQS9 0x524 > +#define EMC_DLI_TRIM_TXDQS10 0x528 > +#define EMC_DLI_TRIM_TXDQS11 0x52c > +#define EMC_DLI_TRIM_TXDQS12 0x530 > +#define EMC_DLI_TRIM_TXDQS13 0x534 > +#define EMC_DLI_TRIM_TXDQS14 0x538 > +#define EMC_DLI_TRIM_TXDQS15 0x53c > +#define EMC_CDB_CNTL_3 0x540 > +#define EMC_XM2DQSPADCTRL5 0x544 > +#define EMC_XM2DQSPADCTRL6 0x548 > +#define EMC_XM2DQPADCTRL3 0x54c > +#define EMC_DLL_XFORM_ADDR3 0x550 > +#define EMC_DLL_XFORM_ADDR4 0x554 > +#define EMC_DLL_XFORM_ADDR5 0x558 > +#define EMC_CFG_PIPE 0x560 > +#define EMC_QPOP 0x564 > +#define EMC_QUSE_WIDTH 0x568 > +#define EMC_PUTERM_WIDTH 0x56c > +#define EMC_BGBIAS_CTL0 0x570 > +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3) > +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2) > +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1) > +#define EMC_PUTERM_ADJ 0x574 > + > +#define DRAM_DEV_SEL_ALL 0 > +#define DRAM_DEV_SEL_0 (2 << 30) > +#define DRAM_DEV_SEL_1 (1 << 30) > + > +#define EMC_CFG_POWER_FEATURES_MASK \ > + (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \ > + EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN) > +#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) > +#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0) > + > +#define EMC_STATUS_UPDATE_TIMEOUT 1000 > + > +enum emc_dram_type { > + DRAM_TYPE_DDR3 = 0, > + DRAM_TYPE_DDR1 = 1, > + DRAM_TYPE_LPDDR3 = 2, > + DRAM_TYPE_DDR2 = 3 > +}; > + > +enum emc_dll_change { > + DLL_CHANGE_NONE, > + DLL_CHANGE_ON, > + DLL_CHANGE_OFF > +}; > + > +static int t124_emc_burst_regs[] = { > + EMC_RC, > + EMC_RFC, > + EMC_RFC_SLR, > + EMC_RAS, > + EMC_RP, > + EMC_R2W, > + EMC_W2R, > + EMC_R2P, > + EMC_W2P, > + EMC_RD_RCD, > + EMC_WR_RCD, > + EMC_RRD, > + EMC_REXT, > + EMC_WEXT, > + EMC_WDV, > + EMC_WDV_MASK, > + EMC_QUSE, > + EMC_QUSE_WIDTH, > + EMC_IBDLY, > + EMC_EINPUT, > + EMC_EINPUT_DURATION, > + EMC_PUTERM_EXTRA, > + EMC_PUTERM_WIDTH, > + EMC_PUTERM_ADJ, > + EMC_CDB_CNTL_1, > + EMC_CDB_CNTL_2, > + EMC_CDB_CNTL_3, > + EMC_QRST, > + EMC_QSAFE, > + EMC_RDV, > + EMC_RDV_MASK, > + EMC_REFRESH, > + EMC_BURST_REFRESH_NUM, > + EMC_PRE_REFRESH_REQ_CNT, > + EMC_PDEX2WR, > + EMC_PDEX2RD, > + EMC_PCHG2PDEN, > + EMC_ACT2PDEN, > + EMC_AR2PDEN, > + EMC_RW2PDEN, > + EMC_TXSR, > + EMC_TXSRDLL, > + EMC_TCKE, > + EMC_TCKESR, > + EMC_TPD, > + EMC_TFAW, > + EMC_TRPAB, > + EMC_TCLKSTABLE, > + EMC_TCLKSTOP, > + EMC_TREFBW, > + EMC_FBIO_CFG6, > + EMC_ODT_WRITE, > + EMC_ODT_READ, > + EMC_FBIO_CFG5, > + EMC_CFG_DIG_DLL, > + EMC_CFG_DIG_DLL_PERIOD, > + EMC_DLL_XFORM_DQS0, > + EMC_DLL_XFORM_DQS1, > + EMC_DLL_XFORM_DQS2, > + EMC_DLL_XFORM_DQS3, > + EMC_DLL_XFORM_DQS4, > + EMC_DLL_XFORM_DQS5, > + EMC_DLL_XFORM_DQS6, > + EMC_DLL_XFORM_DQS7, > + EMC_DLL_XFORM_DQS8, > + EMC_DLL_XFORM_DQS9, > + EMC_DLL_XFORM_DQS10, > + EMC_DLL_XFORM_DQS11, > + EMC_DLL_XFORM_DQS12, > + EMC_DLL_XFORM_DQS13, > + EMC_DLL_XFORM_DQS14, > + EMC_DLL_XFORM_DQS15, > + EMC_DLL_XFORM_QUSE0, > + EMC_DLL_XFORM_QUSE1, > + EMC_DLL_XFORM_QUSE2, > + EMC_DLL_XFORM_QUSE3, > + EMC_DLL_XFORM_QUSE4, > + EMC_DLL_XFORM_QUSE5, > + EMC_DLL_XFORM_QUSE6, > + EMC_DLL_XFORM_QUSE7, > + EMC_DLL_XFORM_ADDR0, > + EMC_DLL_XFORM_ADDR1, > + EMC_DLL_XFORM_ADDR2, > + EMC_DLL_XFORM_ADDR3, > + EMC_DLL_XFORM_ADDR4, > + EMC_DLL_XFORM_ADDR5, > + EMC_DLL_XFORM_QUSE8, > + EMC_DLL_XFORM_QUSE9, > + EMC_DLL_XFORM_QUSE10, > + EMC_DLL_XFORM_QUSE11, > + EMC_DLL_XFORM_QUSE12, > + EMC_DLL_XFORM_QUSE13, > + EMC_DLL_XFORM_QUSE14, > + EMC_DLL_XFORM_QUSE15, > + EMC_DLI_TRIM_TXDQS0, > + EMC_DLI_TRIM_TXDQS1, > + EMC_DLI_TRIM_TXDQS2, > + EMC_DLI_TRIM_TXDQS3, > + EMC_DLI_TRIM_TXDQS4, > + EMC_DLI_TRIM_TXDQS5, > + EMC_DLI_TRIM_TXDQS6, > + EMC_DLI_TRIM_TXDQS7, > + EMC_DLI_TRIM_TXDQS8, > + EMC_DLI_TRIM_TXDQS9, > + EMC_DLI_TRIM_TXDQS10, > + EMC_DLI_TRIM_TXDQS11, > + EMC_DLI_TRIM_TXDQS12, > + EMC_DLI_TRIM_TXDQS13, > + EMC_DLI_TRIM_TXDQS14, > + EMC_DLI_TRIM_TXDQS15, > + EMC_DLL_XFORM_DQ0, > + EMC_DLL_XFORM_DQ1, > + EMC_DLL_XFORM_DQ2, > + EMC_DLL_XFORM_DQ3, > + EMC_DLL_XFORM_DQ4, > + EMC_DLL_XFORM_DQ5, > + EMC_DLL_XFORM_DQ6, > + EMC_DLL_XFORM_DQ7, > + EMC_XM2CMDPADCTRL, > + EMC_XM2CMDPADCTRL4, > + EMC_XM2CMDPADCTRL5, > + EMC_XM2DQSPADCTRL2, > + EMC_XM2DQPADCTRL2, > + EMC_XM2DQPADCTRL3, > + EMC_XM2CLKPADCTRL, > + EMC_XM2CLKPADCTRL2, > + EMC_XM2COMPPADCTRL, > + EMC_XM2VTTGENPADCTRL, > + EMC_XM2VTTGENPADCTRL2, > + EMC_XM2VTTGENPADCTRL3, > + EMC_XM2DQSPADCTRL3, > + EMC_XM2DQSPADCTRL4, > + EMC_XM2DQSPADCTRL5, > + EMC_XM2DQSPADCTRL6, > + EMC_DSR_VTTGEN_DRV, > + EMC_TXDSRVTTGEN, > + EMC_FBIO_SPARE, > + EMC_ZCAL_INTERVAL, > + EMC_ZCAL_WAIT_CNT, > + EMC_MRS_WAIT_CNT, > + EMC_MRS_WAIT_CNT2, > + EMC_CTT, > + EMC_CTT_DURATION, > + EMC_CFG_PIPE, > + EMC_DYN_SELF_REF_CONTROL, > + EMC_QPOP > +}; > + > +struct emc_timing { > + unsigned long rate; > + > + /* Store EMC burst data in a union to minimize mistakes. This allows > + * us to use the same burst data lists as used by the downstream and > + * ChromeOS kernels. > + */ nit: Comment style. > + union { > + u32 emc_burst_data[ARRAY_SIZE(t124_emc_burst_regs)]; > + struct { > + u32 __pad0[121]; > + u32 emc_xm2dqspadctrl2; > + u32 __pad1[15]; > + u32 emc_zcal_interval; > + u32 __pad2[1]; > + u32 emc_mrs_wait_cnt; > + }; > + }; > + > + u32 emc_zcal_cnt_long; > + u32 emc_auto_cal_interval; > + u32 emc_ctt_term_ctrl; > + u32 emc_cfg; > + u32 emc_cfg_2; > + u32 emc_sel_dpd_ctrl; > + u32 __emc_cfg_dig_dll; > + u32 emc_bgbias_ctl0; > + u32 emc_auto_cal_config2; > + u32 emc_auto_cal_config3; > + u32 emc_auto_cal_config; > + u32 emc_mode_reset; > + u32 emc_mode_1; > + u32 emc_mode_2; > + u32 emc_mode_4; > +}; > + > +struct tegra_emc { > + struct platform_device *pdev; > + > + struct tegra_mc *mc; > + > + void __iomem *emc_regs; > + > + enum emc_dram_type dram_type; > + u8 dram_num; > + > + struct emc_timing last_timing; > + struct emc_timing *timings; > + unsigned int num_timings; > + > + bool changing_timing; This field is just set to false once, and then never touched anywhere - is it needed at all? > +}; > + > +/* * * * * * * * * * * * * * * * * * * * * * * * * * > + * Timing change sequence functions * > + * * * * * * * * * * * * * * * * * * * * * * * * * */ > + > +static void emc_ccfifo_writel(struct tegra_emc *tegra, u32 val, > + unsigned long offs) > +{ > + writel(val, tegra->emc_regs + EMC_CCFIFO_DATA); > + writel(offs, tegra->emc_regs + EMC_CCFIFO_ADDR); > +} > + > +static void emc_seq_update_timing(struct tegra_emc *tegra) > +{ > + int i; > + > + writel(1, tegra->emc_regs + EMC_TIMING_CONTROL); > + > + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { > + if (!(readl(tegra->emc_regs + EMC_STATUS) & > + EMC_STATUS_TIMING_UPDATE_STALLED)) > + return; > + } > + > + dev_err(&tegra->pdev->dev, "timing update failed\n"); > +} > + > +static void emc_seq_disable_auto_cal(struct tegra_emc *tegra) > +{ > + int i; > + > + writel(0, tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); > + > + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { > + if (!(readl(tegra->emc_regs + EMC_AUTO_CAL_STATUS) & > + EMC_AUTO_CAL_STATUS_ACTIVE)) > + return; > + } > + > + dev_err(&tegra->pdev->dev, "auto cal disable failed\n"); > +} > + > +static void emc_seq_wait_clkchange(struct tegra_emc *tegra) > +{ > + int i; > + > + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { > + if (readl(tegra->emc_regs + EMC_INTSTATUS) & > + EMC_INTSTATUS_CLKCHANGE_COMPLETE) > + return; > + } > + > + dev_err(&tegra->pdev->dev, "clkchange failed\n"); > +} > + > +static void emc_prepare_timing_change(struct tegra_emc *tegra, > + const struct emc_timing *timing) > +{ > + u32 val, val2; > + bool update = false; > + int pre_wait = 0; > + int i; > + enum emc_dll_change dll_change; > + > + if ((tegra->last_timing.emc_mode_1 & 0x1) == (timing->emc_mode_1 & 1)) > + dll_change = DLL_CHANGE_NONE; > + else if (timing->emc_mode_1 & 1) > + dll_change = DLL_CHANGE_ON; > + else > + dll_change = DLL_CHANGE_OFF; > + > + /* Clear CLKCHANGE_COMPLETE interrupts */ > + > + writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, > + tegra->emc_regs + EMC_INTSTATUS); > + > + /* Disable dynamic self-refresh */ > + > + val = readl(tegra->emc_regs + EMC_CFG); > + if (val & EMC_CFG_PWR_MASK) { > + val &= ~EMC_CFG_POWER_FEATURES_MASK; > + writel(val, tegra->emc_regs + EMC_CFG); > + > + pre_wait = 5; > + } > + > + /* Disable SEL_DPD_CTRL for clock change */ > + > + val = readl(tegra->emc_regs + EMC_SEL_DPD_CTRL); > + if (val & (tegra->dram_type == DRAM_TYPE_DDR3 ? > + EMC_SEL_DPD_CTRL_DDR3_MASK : EMC_SEL_DPD_CTRL_MASK)) { > + val &= ~(EMC_SEL_DPD_CTRL_DATA_SEL_DPD | > + EMC_SEL_DPD_CTRL_ODT_SEL_DPD | > + EMC_SEL_DPD_CTRL_CA_SEL_DPD | > + EMC_SEL_DPD_CTRL_CLK_SEL_DPD); > + if (tegra->dram_type == DRAM_TYPE_DDR3) > + val &= ~EMC_SEL_DPD_CTRL_RESET_SEL_DPD; > + writel(val, tegra->emc_regs + EMC_SEL_DPD_CTRL); > + } > + > + /* Prepare DQ/DQS for clock change */ > + > + val = readl(tegra->emc_regs + EMC_BGBIAS_CTL0); > + val2 = tegra->last_timing.emc_bgbias_ctl0; > + if (!(timing->emc_bgbias_ctl0 & > + EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) && > + (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) { > + val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX; > + update = true; > + } > + > + if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) || > + (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) { > + update = true; > + } > + > + if (update) { > + writel(val2, tegra->emc_regs + EMC_BGBIAS_CTL0); > + if (pre_wait < 5) > + pre_wait = 5; > + } > + > + update = false; > + val = readl(tegra->emc_regs + EMC_XM2DQSPADCTRL2); > + if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && > + !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) { > + val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE; > + update = true; > + } > + > + if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && > + !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) { > + val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE; > + update = true; > + } > + > + if (update) { > + writel(val, tegra->emc_regs + EMC_XM2DQSPADCTRL2); > + if (pre_wait < 30) > + pre_wait = 30; > + } > + > + /* Wait to settle */ > + > + if (pre_wait) { > + emc_seq_update_timing(tegra); > + udelay(pre_wait); > + } > + > + /* Program CTT_TERM control */ > + > + if (tegra->last_timing.emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { > + emc_seq_disable_auto_cal(tegra); > + writel(timing->emc_ctt_term_ctrl, > + tegra->emc_regs + EMC_CTT_TERM_CTRL); > + emc_seq_update_timing(tegra); > + } > + > + /* Program burst shadow registers */ > + > + for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) > + __raw_writel(timing->emc_burst_data[i], > + tegra->emc_regs + t124_emc_burst_regs[i]); > + > + tegra_mc_write_emem_configuration(tegra->mc, timing->rate); > + > + val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; > + emc_ccfifo_writel(tegra, val, EMC_CFG); > + > + /* Program AUTO_CAL_CONFIG */ > + > + if (timing->emc_auto_cal_config2 != > + tegra->last_timing.emc_auto_cal_config2) > + emc_ccfifo_writel(tegra, timing->emc_auto_cal_config2, > + EMC_AUTO_CAL_CONFIG2); > + if (timing->emc_auto_cal_config3 != > + tegra->last_timing.emc_auto_cal_config3) > + emc_ccfifo_writel(tegra, timing->emc_auto_cal_config3, > + EMC_AUTO_CAL_CONFIG3); > + if (timing->emc_auto_cal_config != > + tegra->last_timing.emc_auto_cal_config) { > + val = timing->emc_auto_cal_config; > + val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START; > + emc_ccfifo_writel(tegra, val, EMC_AUTO_CAL_CONFIG); > + } > + > + /* DDR3: predict MRS long wait count */ > + > + if (tegra->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) { > + u32 cnt = 32; > + > + if (timing->emc_zcal_interval != 0 && > + tegra->last_timing.emc_zcal_interval == 0) > + cnt -= tegra->dram_num * 256; > + > + val = timing->emc_mrs_wait_cnt > + & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK > + >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT; > + if (cnt < val) > + cnt = val; > + > + val = timing->emc_mrs_wait_cnt > + & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; > + val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) > + & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; > + > + writel(val, tegra->emc_regs + EMC_MRS_WAIT_CNT); > + } > + > + val = timing->emc_cfg_2; > + val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR; > + emc_ccfifo_writel(tegra, val, EMC_CFG_2); > + > + /* DDR3: Turn off DLL and enter self-refresh */ > + > + if (tegra->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) > + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_EMRS); > + > + /* Disable refresh controller */ > + > + emc_ccfifo_writel(tegra, EMC_REFCTRL_DEV_SEL(tegra->dram_num), > + EMC_REFCTRL); > + if (tegra->dram_type == DRAM_TYPE_DDR3) > + emc_ccfifo_writel(tegra, > + EMC_DRAM_DEV_SEL(tegra->dram_num) > + | EMC_SELF_REF_CMD_ENABLED, > + EMC_SELF_REF); > + > + /* Flow control marker */ > + > + emc_ccfifo_writel(tegra, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); > + > + /* DDR3: Exit self-refresh */ > + > + if (tegra->dram_type == DRAM_TYPE_DDR3) > + emc_ccfifo_writel(tegra, > + EMC_DRAM_DEV_SEL(tegra->dram_num), > + EMC_SELF_REF); > + emc_ccfifo_writel(tegra, > + EMC_REFCTRL_DEV_SEL(tegra->dram_num) > + | EMC_REFCTRL_ENABLE, > + EMC_REFCTRL); > + > + /* Set DRAM mode registers */ > + > + if (tegra->dram_type == DRAM_TYPE_DDR3) { > + if (timing->emc_mode_1 != tegra->last_timing.emc_mode_1) > + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_EMRS); > + if (timing->emc_mode_2 != tegra->last_timing.emc_mode_2) > + emc_ccfifo_writel(tegra, timing->emc_mode_2, EMC_EMRS2); > + > + if ((timing->emc_mode_reset != > + tegra->last_timing.emc_mode_reset) || > + dll_change == DLL_CHANGE_ON) { > + val = timing->emc_mode_reset; > + if (dll_change == DLL_CHANGE_ON) { > + val |= EMC_MODE_SET_DLL_RESET; > + val |= EMC_MODE_SET_LONG_CNT; > + } else { > + val &= ~EMC_MODE_SET_DLL_RESET; > + } > + emc_ccfifo_writel(tegra, val, EMC_MRS); > + } > + } else { > + if (timing->emc_mode_2 != tegra->last_timing.emc_mode_2) > + emc_ccfifo_writel(tegra, timing->emc_mode_2, EMC_MRW2); > + if (timing->emc_mode_1 != tegra->last_timing.emc_mode_1) > + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_MRW); > + if (timing->emc_mode_4 != tegra->last_timing.emc_mode_4) > + emc_ccfifo_writel(tegra, timing->emc_mode_4, EMC_MRW4); > + } > + > + /* Issue ZCAL command if turning ZCAL on */ > + > + if (timing->emc_zcal_interval != 0 && > + tegra->last_timing.emc_zcal_interval == 0) { > + emc_ccfifo_writel(tegra, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); > + if (tegra->dram_num > 1) > + emc_ccfifo_writel(tegra, EMC_ZQ_CAL_LONG_CMD_DEV1, > + EMC_ZQ_CAL); > + } > + > + /* Write to RO register to remove stall after change */ > + > + emc_ccfifo_writel(tegra, 0, EMC_CCFIFO_STATUS); > + > + if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) > + emc_ccfifo_writel(tegra, timing->emc_cfg_2, EMC_CFG_2); > + > + /* Disable AUTO_CAL for clock change */ > + > + emc_seq_disable_auto_cal(tegra); > + > + /* Read register to wait until programming has settled */ > + > + readl(tegra->emc_regs + EMC_INTSTATUS); > +} > + > +static void emc_complete_timing_change(struct tegra_emc *tegra, > + const struct emc_timing *timing) > +{ > + u32 val; > + > + /* Wait until the state machine has settled */ > + > + emc_seq_wait_clkchange(tegra); > + > + /* Restore AUTO_CAL */ > + > + if (timing->emc_ctt_term_ctrl != tegra->last_timing.emc_ctt_term_ctrl) > + writel(timing->emc_auto_cal_interval, > + tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); > + > + /* Restore dynamic self-refresh */ > + > + if (timing->emc_cfg & EMC_CFG_PWR_MASK) > + writel(timing->emc_cfg, tegra->emc_regs + EMC_CFG); > + > + /* Set ZCAL wait count */ > + > + writel(timing->emc_zcal_cnt_long, tegra->emc_regs + EMC_ZCAL_WAIT_CNT); > + > + /* LPDDR3: Turn off BGBIAS if low frequency */ > + > + if (tegra->dram_type == DRAM_TYPE_LPDDR3 && > + timing->emc_bgbias_ctl0 & > + EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) { > + val = timing->emc_bgbias_ctl0; > + val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN; > + val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD; > + writel(val, tegra->emc_regs + EMC_BGBIAS_CTL0); > + } else { > + if (tegra->dram_type == DRAM_TYPE_DDR3 && > + readl(tegra->emc_regs + EMC_BGBIAS_CTL0) != > + timing->emc_bgbias_ctl0) { > + writel(timing->emc_bgbias_ctl0, > + tegra->emc_regs + EMC_BGBIAS_CTL0); > + } > + > + writel(timing->emc_auto_cal_interval, > + tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); > + } > + > + /* Wait for timing to settle */ > + > + udelay(2); > + > + /* Reprogram SEL_DPD_CTRL */ > + > + writel(timing->emc_sel_dpd_ctrl, tegra->emc_regs + EMC_SEL_DPD_CTRL); > + emc_seq_update_timing(tegra); > + > + tegra->last_timing = *timing; > +} > + > +/* * * * * * * * * * * * * * * * * * * * * * * * * * > + * Initialization and deinitialization * > + * * * * * * * * * * * * * * * * * * * * * * * * * */ > + > +static void emc_read_current_timing(struct tegra_emc *tegra, > + struct emc_timing *timing) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(t124_emc_burst_regs); ++i) > + timing->emc_burst_data[i] = > + readl(tegra->emc_regs + t124_emc_burst_regs[i]); > + > + timing->emc_cfg = readl(tegra->emc_regs + EMC_CFG); > + > + timing->emc_auto_cal_interval = 0; > + timing->emc_zcal_cnt_long = 0; > + timing->emc_mode_1 = 0; > + timing->emc_mode_2 = 0; > + timing->emc_mode_4 = 0; > + timing->emc_mode_reset = 0; > +} > + > +static int emc_init(struct tegra_emc *tegra) > +{ > + tegra->dram_type = readl(tegra->emc_regs + EMC_FBIO_CFG5); > + tegra->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; > + tegra->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; > + > + tegra->dram_num = tegra_mc_get_emem_device_count(tegra->mc); > + > + emc_read_current_timing(tegra, &tegra->last_timing); > + > + tegra->changing_timing = false; > + > + return 0; > +} > + > +static int load_one_timing_from_dt(struct tegra_emc *tegra, > + struct emc_timing *timing, > + struct device_node *node) > +{ > + int err; > + u32 tmp; > + > + err = of_property_read_u32(node, "clock-frequency", &tmp); > + if (err) { > + dev_err(&tegra->pdev->dev, > + "timing %s: failed to read rate\n", node->name); > + return err; > + } > + > + timing->rate = tmp; > + > + err = of_property_read_u32_array(node, "nvidia,emc-configuration", > + timing->emc_burst_data, > + ARRAY_SIZE(timing->emc_burst_data)); > + if (err) { > + dev_err(&tegra->pdev->dev, > + "timing %s: failed to read emc burst data\n", > + node->name); > + return err; > + } > + > +#define EMC_READ_PROP(prop, dtprop) { \ > + err = of_property_read_u32(node, dtprop, &timing->prop); \ > + if (err) { \ > + dev_err(&tegra->pdev->dev, \ > + "timing %s: failed to read " #prop "\n", \ > + node->name); \ > + return err; \ > + } \ > +} Let's make this static inline and let the compiler decide whether it is worth expanding it 14 times. > + > + EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") > + EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") > + EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") > + EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") > + EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") > + EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") > + EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0") > + EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2") > + EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3") > + EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config") > + EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset") > + EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1") > + EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2") > + EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4") > + > +#undef EMC_READ_PROP > + > + return 0; > +} > + > +static int cmp_timings(const void *_a, const void *_b) > +{ > + const struct emc_timing *a = _a; > + const struct emc_timing *b = _b; > + > + if (a->rate < b->rate) > + return -1; > + else if (a->rate == b->rate) > + return 0; > + else > + return 1; > +} > + > +static int load_timings_from_dt(struct tegra_emc *tegra, > + struct device_node *node) > +{ > + struct device_node *child; > + int child_count = of_get_child_count(node); > + int i = 0, err; > + > + tegra->timings = devm_kzalloc(&tegra->pdev->dev, > + sizeof(struct emc_timing) * child_count, > + GFP_KERNEL); > + if (!tegra->timings) > + return -ENOMEM; > + > + tegra->num_timings = child_count; > + > + for_each_child_of_node(node, child) { > + struct emc_timing *timing = tegra->timings + (i++); > + > + err = load_one_timing_from_dt(tegra, timing, child); > + if (err) > + return err; > + } > + > + sort(tegra->timings, tegra->num_timings, sizeof(struct emc_timing), > + cmp_timings, NULL); > + > + return 0; > +} > + > +static const struct of_device_id tegra_emc_of_match[] = { > + { .compatible = "nvidia,tegra124-emc" }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); > + > +static struct tegra_emc *emc_instance; > + > +void tegra_emc_prepare_timing_change(unsigned long rate) > +{ > + int i; > + > + if (!emc_instance) > + return; > + > + for (i = 0; i < emc_instance->num_timings; ++i) { > + if (emc_instance->timings[i].rate == rate) > + break; > + } > + > + if (i == emc_instance->num_timings) > + return; Same comment as previous patch - we should probably report this one way or the other. > + > + emc_prepare_timing_change(emc_instance, emc_instance->timings + i); > +} > + > +void tegra_emc_complete_timing_change(unsigned long rate) > +{ > + int i; > + > + if (!emc_instance) > + return; > + > + for (i = 0; i < emc_instance->num_timings; ++i) { > + if (emc_instance->timings[i].rate == rate) > + break; > + } > + > + if (i == emc_instance->num_timings) > + return; Same here. > + > + emc_complete_timing_change(emc_instance, emc_instance->timings + i); > +} > + > +static int tegra_emc_probe(struct platform_device *pdev) > +{ > + struct tegra_emc *tegra; > + struct device_node *node; > + struct platform_device *mc_pdev; > + struct resource *res; > + u32 ram_code, node_ram_code; > + int err; > + > + tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); > + if (!tegra) > + return -ENOMEM; > + > + tegra->pdev = pdev; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + tegra->emc_regs = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(tegra->emc_regs)) { > + dev_err(&pdev->dev, "failed to map EMC regs\n"); > + return PTR_ERR(tegra->emc_regs); > + } > + > + node = of_parse_phandle(pdev->dev.of_node, > + "nvidia,memory-controller", 0); > + if (!node) { > + dev_err(&pdev->dev, "could not get memory controller\n"); > + return -ENOENT; > + } > + > + mc_pdev = of_find_device_by_node(node); > + if (!mc_pdev) > + return -ENOENT; Isn't there a risk that we will return -ENOENT depending on the probe order? I.e. if this device is probed before the MC device? > + > + tegra->mc = platform_get_drvdata(mc_pdev); > + if (!tegra->mc) > + return -ENOENT; > + > + of_node_put(node); > + > + ram_code = tegra_read_ram_code(); > + > + tegra->num_timings = 0; > + > + for_each_child_of_node(pdev->dev.of_node, node) { > + if (strcmp(node->name, "timings")) > + continue; > + > + err = of_property_read_u32(node, "nvidia,ram-code", > + &node_ram_code); > + if (err) { > + dev_warn(&pdev->dev, > + "skipping timing without ram-code\n"); > + continue; > + } > + > + if (node_ram_code != ram_code) > + continue; > + > + err = load_timings_from_dt(tegra, node); > + if (err) > + return err; > + break; > + } > + > + if (tegra->num_timings == 0) > + dev_warn(&pdev->dev, "no memory timings registered\n"); > + > + err = emc_init(tegra); > + if (err) { > + dev_err(&pdev->dev, "initialization failed: %d\n", err); > + return err; > + } > + > + platform_set_drvdata(pdev, tegra); > + > + emc_instance = tegra; > + > + return 0; > +}; > + > +static struct platform_driver tegra_emc_driver = { > + .probe = tegra_emc_probe, > + .driver = { > + .name = "tegra-emc", > + .of_match_table = tegra_emc_of_match, > + }, > +}; > + > +static int tegra_emc_init(void) > +{ > + return platform_driver_register(&tegra_emc_driver); > +} > +subsys_initcall(tegra_emc_init); > + > +MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); > +MODULE_DESCRIPTION("Tegra124 EMC memory driver"); > +MODULE_LICENSE("GPL v2"); > diff --git a/include/soc/tegra/memory.h b/include/soc/tegra/memory.h > index f307516..0e0a2e9 100644 > --- a/include/soc/tegra/memory.h > +++ b/include/soc/tegra/memory.h > @@ -13,5 +13,7 @@ struct tegra_mc; > > void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate); > int tegra_mc_get_emem_device_count(struct tegra_mc *mc); > +void tegra_emc_prepare_timing_change(unsigned long rate); > +void tegra_emc_complete_timing_change(unsigned long rate); > > #endif /* __SOC_TEGRA_MEMORY_H__ */ > ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <545B29AA.8030006-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH v3 10/13] memory: tegra: Add EMC (external memory controller) driver [not found] ` <545B29AA.8030006-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-11-06 11:35 ` Mikko Perttunen [not found] ` <545B5D15.6030705-/1wQRMveznE@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Mikko Perttunen @ 2014-11-06 11:35 UTC (permalink / raw) To: Alexandre Courbot, Tomeu Vizoso, linux-tegra-u79uwXL29TY76Z2rM5mHXA Cc: Javier Martinez Canillas, Mikko Perttunen, Stephen Warren, Thierry Reding, Alexandre Courbot, Grant Likely, Rob Herring, Greg Kroah-Hartman, Paul Gortmaker, Maxime Ripard, Nicolas Ferre, Ivan Khoronzhuk, Alexandre Belloni, Scott Wood, Bharat Bhushan, Santosh Shilimkar, Prabhakar Kushwaha, linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA On 11/06/2014 09:56 AM, Alexandre Courbot wrote: > On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >> From: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >> >> Implements functionality needed to change the rate of the memory bus >> clock. >> >> Signed-off-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >> Signed-off-by: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> >> >> --- >> >> v2: * Use subsys_initcall(), so it gets probed after the MC driver and >> before the CAR driver >> --- >> drivers/memory/Kconfig | 10 + >> drivers/memory/Makefile | 1 - >> drivers/memory/tegra/Makefile | 1 + >> drivers/memory/tegra/tegra124-emc.c | 1133 >> +++++++++++++++++++++++++++++++++++ >> include/soc/tegra/memory.h | 2 + >> 5 files changed, 1146 insertions(+), 1 deletion(-) >> create mode 100644 drivers/memory/tegra/tegra124-emc.c >> >> diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig >> index 6d91c27..3ba3aef 100644 >> --- a/drivers/memory/Kconfig >> +++ b/drivers/memory/Kconfig >> @@ -51,6 +51,16 @@ config MVEBU_DEVBUS >> Armada 370 and Armada XP. This controller allows to handle flash >> devices such as NOR, NAND, SRAM, and FPGA. >> >> +config TEGRA124_EMC >> + bool "Tegra124 External Memory Controller driver" >> + default y >> + depends on ARCH_TEGRA_124_SOC >> + help >> + This driver is for the External Memory Controller (EMC) found on >> + Tegra124 chips. The EMC controls the external DRAM on the board. >> + This driver is required to change memory timings / clock rate for >> + external memory. >> + >> config TEGRA20_MC >> bool "Tegra20 Memory Controller(MC) driver" >> default y >> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile >> index 1c932e7..8e5ec8d 100644 >> --- a/drivers/memory/Makefile >> +++ b/drivers/memory/Makefile >> @@ -12,5 +12,4 @@ obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o >> obj-$(CONFIG_FSL_IFC) += fsl_ifc.o >> obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o >> obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o >> - >> obj-$(CONFIG_ARCH_TEGRA) += tegra/ >> diff --git a/drivers/memory/tegra/Makefile >> b/drivers/memory/tegra/Makefile >> index 51b9e8f..4e84bef 100644 >> --- a/drivers/memory/tegra/Makefile >> +++ b/drivers/memory/tegra/Makefile >> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-mc.o >> obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114-mc.o >> obj-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-mc.o >> obj-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124-mc.o >> +obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o >> diff --git a/drivers/memory/tegra/tegra124-emc.c >> b/drivers/memory/tegra/tegra124-emc.c >> new file mode 100644 >> index 0000000..8438de2 >> --- /dev/null >> +++ b/drivers/memory/tegra/tegra124-emc.c >> @@ -0,0 +1,1133 @@ >> +/* >> + * drivers/memory/tegra124-emc.c >> + * >> + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. >> + * >> + * Author: >> + * Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >> + * >> + * This software is licensed under the terms of the GNU General Public >> + * License version 2, as published by the Free Software Foundation, and >> + * may be copied, distributed, and modified under those terms. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/clk.h> >> +#include <linux/clkdev.h> >> +#include <linux/delay.h> >> +#include <linux/module.h> >> +#include <linux/of_address.h> >> +#include <linux/of_platform.h> >> +#include <linux/platform_device.h> >> +#include <linux/sort.h> >> +#include <linux/string.h> >> + >> +#include <soc/tegra/fuse.h> >> +#include <soc/tegra/memory.h> >> + >> +#define EMC_FBIO_CFG5 0x104 >> +#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3 >> +#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 >> + >> +#define EMC_INTSTATUS 0x0 >> +#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) >> + >> +#define EMC_CFG 0xc >> +#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31) >> +#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30) >> +#define EMC_CFG_DRAM_ACPD BIT(29) >> +#define EMC_CFG_DYN_SREF BIT(28) >> +#define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18)) >> +#define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18) >> + >> +#define EMC_REFCTRL 0x20 >> +#define EMC_REFCTRL_DEV_SEL_SHIFT 0 >> +#define EMC_REFCTRL_ENABLE BIT(31) >> + >> +#define EMC_TIMING_CONTROL 0x28 >> +#define EMC_RC 0x2c >> +#define EMC_RFC 0x30 >> +#define EMC_RAS 0x34 >> +#define EMC_RP 0x38 >> +#define EMC_R2W 0x3c >> +#define EMC_W2R 0x40 >> +#define EMC_R2P 0x44 >> +#define EMC_W2P 0x48 >> +#define EMC_RD_RCD 0x4c >> +#define EMC_WR_RCD 0x50 >> +#define EMC_RRD 0x54 >> +#define EMC_REXT 0x58 >> +#define EMC_WDV 0x5c >> +#define EMC_QUSE 0x60 >> +#define EMC_QRST 0x64 >> +#define EMC_QSAFE 0x68 >> +#define EMC_RDV 0x6c >> +#define EMC_REFRESH 0x70 >> +#define EMC_BURST_REFRESH_NUM 0x74 >> +#define EMC_PDEX2WR 0x78 >> +#define EMC_PDEX2RD 0x7c >> +#define EMC_PCHG2PDEN 0x80 >> +#define EMC_ACT2PDEN 0x84 >> +#define EMC_AR2PDEN 0x88 >> +#define EMC_RW2PDEN 0x8c >> +#define EMC_TXSR 0x90 >> +#define EMC_TCKE 0x94 >> +#define EMC_TFAW 0x98 >> +#define EMC_TRPAB 0x9c >> +#define EMC_TCLKSTABLE 0xa0 >> +#define EMC_TCLKSTOP 0xa4 >> +#define EMC_TREFBW 0xa8 >> +#define EMC_ODT_WRITE 0xb0 >> +#define EMC_ODT_READ 0xb4 >> +#define EMC_WEXT 0xb8 >> +#define EMC_CTT 0xbc >> +#define EMC_RFC_SLR 0xc0 >> +#define EMC_MRS_WAIT_CNT2 0xc4 >> + >> +#define EMC_MRS_WAIT_CNT 0xc8 >> +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 >> +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ >> + (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) >> +#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 >> +#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ >> + (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) >> + >> +#define EMC_MRS 0xcc >> +#define EMC_MODE_SET_DLL_RESET BIT(8) >> +#define EMC_MODE_SET_LONG_CNT BIT(26) >> +#define EMC_EMRS 0xd0 >> +#define EMC_REF 0xd4 >> +#define EMC_PRE 0xd8 >> + >> +#define EMC_SELF_REF 0xe0 >> +#define EMC_SELF_REF_CMD_ENABLED BIT(0) >> +#define EMC_SELF_REF_DEV_SEL_SHIFT 30 >> + >> +#define EMC_MRW 0xe8 >> + >> +#define EMC_MRR 0xec >> +#define EMC_MRR_MA_SHIFT 16 >> +#define LPDDR2_MR4_TEMP_SHIFT 0 >> + >> +#define EMC_XM2DQSPADCTRL3 0xf8 >> +#define EMC_FBIO_SPARE 0x100 >> + >> +#define EMC_FBIO_CFG6 0x114 >> +#define EMC_EMRS2 0x12c >> +#define EMC_MRW2 0x134 >> +#define EMC_MRW4 0x13c >> +#define EMC_EINPUT 0x14c >> +#define EMC_EINPUT_DURATION 0x150 >> +#define EMC_PUTERM_EXTRA 0x154 >> +#define EMC_TCKESR 0x158 >> +#define EMC_TPD 0x15c >> + >> +#define EMC_AUTO_CAL_CONFIG 0x2a4 >> +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31) >> +#define EMC_AUTO_CAL_INTERVAL 0x2a8 >> +#define EMC_AUTO_CAL_STATUS 0x2ac >> +#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31) >> +#define EMC_STATUS 0x2b4 >> +#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) >> + >> +#define EMC_CFG_2 0x2b8 >> +#define EMC_CFG_2_MODE_SHIFT 0 >> +#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6) >> + >> +#define EMC_CFG_DIG_DLL 0x2bc >> +#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 >> +#define EMC_RDV_MASK 0x2cc >> +#define EMC_WDV_MASK 0x2d0 >> +#define EMC_CTT_DURATION 0x2d8 >> +#define EMC_CTT_TERM_CTRL 0x2dc >> +#define EMC_ZCAL_INTERVAL 0x2e0 >> +#define EMC_ZCAL_WAIT_CNT 0x2e4 >> + >> +#define EMC_ZQ_CAL 0x2ec >> +#define EMC_ZQ_CAL_CMD BIT(0) >> +#define EMC_ZQ_CAL_LONG BIT(4) >> +#define EMC_ZQ_CAL_LONG_CMD_DEV0 \ >> + (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) >> +#define EMC_ZQ_CAL_LONG_CMD_DEV1 \ >> + (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) >> + >> +#define EMC_XM2CMDPADCTRL 0x2f0 >> +#define EMC_XM2DQSPADCTRL 0x2f8 >> +#define EMC_XM2DQSPADCTRL2 0x2fc >> +#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0) >> +#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5) >> +#define EMC_XM2DQPADCTRL 0x300 >> +#define EMC_XM2DQPADCTRL2 0x304 >> +#define EMC_XM2CLKPADCTRL 0x308 >> +#define EMC_XM2COMPPADCTRL 0x30c >> +#define EMC_XM2VTTGENPADCTRL 0x310 >> +#define EMC_XM2VTTGENPADCTRL2 0x314 >> +#define EMC_XM2VTTGENPADCTRL3 0x318 >> +#define EMC_XM2DQSPADCTRL4 0x320 >> +#define EMC_DLL_XFORM_DQS0 0x328 >> +#define EMC_DLL_XFORM_DQS1 0x32c >> +#define EMC_DLL_XFORM_DQS2 0x330 >> +#define EMC_DLL_XFORM_DQS3 0x334 >> +#define EMC_DLL_XFORM_DQS4 0x338 >> +#define EMC_DLL_XFORM_DQS5 0x33c >> +#define EMC_DLL_XFORM_DQS6 0x340 >> +#define EMC_DLL_XFORM_DQS7 0x344 >> +#define EMC_DLL_XFORM_QUSE0 0x348 >> +#define EMC_DLL_XFORM_QUSE1 0x34c >> +#define EMC_DLL_XFORM_QUSE2 0x350 >> +#define EMC_DLL_XFORM_QUSE3 0x354 >> +#define EMC_DLL_XFORM_QUSE4 0x358 >> +#define EMC_DLL_XFORM_QUSE5 0x35c >> +#define EMC_DLL_XFORM_QUSE6 0x360 >> +#define EMC_DLL_XFORM_QUSE7 0x364 >> +#define EMC_DLL_XFORM_DQ0 0x368 >> +#define EMC_DLL_XFORM_DQ1 0x36c >> +#define EMC_DLL_XFORM_DQ2 0x370 >> +#define EMC_DLL_XFORM_DQ3 0x374 >> +#define EMC_DLI_TRIM_TXDQS0 0x3a8 >> +#define EMC_DLI_TRIM_TXDQS1 0x3ac >> +#define EMC_DLI_TRIM_TXDQS2 0x3b0 >> +#define EMC_DLI_TRIM_TXDQS3 0x3b4 >> +#define EMC_DLI_TRIM_TXDQS4 0x3b8 >> +#define EMC_DLI_TRIM_TXDQS5 0x3bc >> +#define EMC_DLI_TRIM_TXDQS6 0x3c0 >> +#define EMC_DLI_TRIM_TXDQS7 0x3c4 >> +#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc >> +#define EMC_SEL_DPD_CTRL 0x3d8 >> +#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8) >> +#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5) >> +#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4) >> +#define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3) >> +#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2) >> +#define EMC_SEL_DPD_CTRL_DDR3_MASK \ >> + ((0xf << 2) | BIT(8)) >> +#define EMC_SEL_DPD_CTRL_MASK \ >> + ((0x3 << 2) | BIT(5) | BIT(8)) >> +#define EMC_PRE_REFRESH_REQ_CNT 0x3dc >> +#define EMC_DYN_SELF_REF_CONTROL 0x3e0 >> +#define EMC_TXSRDLL 0x3e4 >> +#define EMC_CCFIFO_ADDR 0x3e8 >> +#define EMC_CCFIFO_DATA 0x3ec >> +#define EMC_CCFIFO_STATUS 0x3f0 >> +#define EMC_CDB_CNTL_1 0x3f4 >> +#define EMC_CDB_CNTL_2 0x3f8 >> +#define EMC_XM2CLKPADCTRL2 0x3fc >> +#define EMC_AUTO_CAL_CONFIG2 0x458 >> +#define EMC_AUTO_CAL_CONFIG3 0x45c >> +#define EMC_IBDLY 0x468 >> +#define EMC_DLL_XFORM_ADDR0 0x46c >> +#define EMC_DLL_XFORM_ADDR1 0x470 >> +#define EMC_DLL_XFORM_ADDR2 0x474 >> +#define EMC_DSR_VTTGEN_DRV 0x47c >> +#define EMC_TXDSRVTTGEN 0x480 >> +#define EMC_XM2CMDPADCTRL4 0x484 >> +#define EMC_XM2CMDPADCTRL5 0x488 >> +#define EMC_DLL_XFORM_DQS8 0x4a0 >> +#define EMC_DLL_XFORM_DQS9 0x4a4 >> +#define EMC_DLL_XFORM_DQS10 0x4a8 >> +#define EMC_DLL_XFORM_DQS11 0x4ac >> +#define EMC_DLL_XFORM_DQS12 0x4b0 >> +#define EMC_DLL_XFORM_DQS13 0x4b4 >> +#define EMC_DLL_XFORM_DQS14 0x4b8 >> +#define EMC_DLL_XFORM_DQS15 0x4bc >> +#define EMC_DLL_XFORM_QUSE8 0x4c0 >> +#define EMC_DLL_XFORM_QUSE9 0x4c4 >> +#define EMC_DLL_XFORM_QUSE10 0x4c8 >> +#define EMC_DLL_XFORM_QUSE11 0x4cc >> +#define EMC_DLL_XFORM_QUSE12 0x4d0 >> +#define EMC_DLL_XFORM_QUSE13 0x4d4 >> +#define EMC_DLL_XFORM_QUSE14 0x4d8 >> +#define EMC_DLL_XFORM_QUSE15 0x4dc >> +#define EMC_DLL_XFORM_DQ4 0x4e0 >> +#define EMC_DLL_XFORM_DQ5 0x4e4 >> +#define EMC_DLL_XFORM_DQ6 0x4e8 >> +#define EMC_DLL_XFORM_DQ7 0x4ec >> +#define EMC_DLI_TRIM_TXDQS8 0x520 >> +#define EMC_DLI_TRIM_TXDQS9 0x524 >> +#define EMC_DLI_TRIM_TXDQS10 0x528 >> +#define EMC_DLI_TRIM_TXDQS11 0x52c >> +#define EMC_DLI_TRIM_TXDQS12 0x530 >> +#define EMC_DLI_TRIM_TXDQS13 0x534 >> +#define EMC_DLI_TRIM_TXDQS14 0x538 >> +#define EMC_DLI_TRIM_TXDQS15 0x53c >> +#define EMC_CDB_CNTL_3 0x540 >> +#define EMC_XM2DQSPADCTRL5 0x544 >> +#define EMC_XM2DQSPADCTRL6 0x548 >> +#define EMC_XM2DQPADCTRL3 0x54c >> +#define EMC_DLL_XFORM_ADDR3 0x550 >> +#define EMC_DLL_XFORM_ADDR4 0x554 >> +#define EMC_DLL_XFORM_ADDR5 0x558 >> +#define EMC_CFG_PIPE 0x560 >> +#define EMC_QPOP 0x564 >> +#define EMC_QUSE_WIDTH 0x568 >> +#define EMC_PUTERM_WIDTH 0x56c >> +#define EMC_BGBIAS_CTL0 0x570 >> +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3) >> +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2) >> +#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1) >> +#define EMC_PUTERM_ADJ 0x574 >> + >> +#define DRAM_DEV_SEL_ALL 0 >> +#define DRAM_DEV_SEL_0 (2 << 30) >> +#define DRAM_DEV_SEL_1 (1 << 30) >> + >> +#define EMC_CFG_POWER_FEATURES_MASK \ >> + (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \ >> + EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN) >> +#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << >> EMC_REFCTRL_DEV_SEL_SHIFT) >> +#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : >> DRAM_DEV_SEL_0) >> + >> +#define EMC_STATUS_UPDATE_TIMEOUT 1000 >> + >> +enum emc_dram_type { >> + DRAM_TYPE_DDR3 = 0, >> + DRAM_TYPE_DDR1 = 1, >> + DRAM_TYPE_LPDDR3 = 2, >> + DRAM_TYPE_DDR2 = 3 >> +}; >> + >> +enum emc_dll_change { >> + DLL_CHANGE_NONE, >> + DLL_CHANGE_ON, >> + DLL_CHANGE_OFF >> +}; >> + >> +static int t124_emc_burst_regs[] = { >> + EMC_RC, >> + EMC_RFC, >> + EMC_RFC_SLR, >> + EMC_RAS, >> + EMC_RP, >> + EMC_R2W, >> + EMC_W2R, >> + EMC_R2P, >> + EMC_W2P, >> + EMC_RD_RCD, >> + EMC_WR_RCD, >> + EMC_RRD, >> + EMC_REXT, >> + EMC_WEXT, >> + EMC_WDV, >> + EMC_WDV_MASK, >> + EMC_QUSE, >> + EMC_QUSE_WIDTH, >> + EMC_IBDLY, >> + EMC_EINPUT, >> + EMC_EINPUT_DURATION, >> + EMC_PUTERM_EXTRA, >> + EMC_PUTERM_WIDTH, >> + EMC_PUTERM_ADJ, >> + EMC_CDB_CNTL_1, >> + EMC_CDB_CNTL_2, >> + EMC_CDB_CNTL_3, >> + EMC_QRST, >> + EMC_QSAFE, >> + EMC_RDV, >> + EMC_RDV_MASK, >> + EMC_REFRESH, >> + EMC_BURST_REFRESH_NUM, >> + EMC_PRE_REFRESH_REQ_CNT, >> + EMC_PDEX2WR, >> + EMC_PDEX2RD, >> + EMC_PCHG2PDEN, >> + EMC_ACT2PDEN, >> + EMC_AR2PDEN, >> + EMC_RW2PDEN, >> + EMC_TXSR, >> + EMC_TXSRDLL, >> + EMC_TCKE, >> + EMC_TCKESR, >> + EMC_TPD, >> + EMC_TFAW, >> + EMC_TRPAB, >> + EMC_TCLKSTABLE, >> + EMC_TCLKSTOP, >> + EMC_TREFBW, >> + EMC_FBIO_CFG6, >> + EMC_ODT_WRITE, >> + EMC_ODT_READ, >> + EMC_FBIO_CFG5, >> + EMC_CFG_DIG_DLL, >> + EMC_CFG_DIG_DLL_PERIOD, >> + EMC_DLL_XFORM_DQS0, >> + EMC_DLL_XFORM_DQS1, >> + EMC_DLL_XFORM_DQS2, >> + EMC_DLL_XFORM_DQS3, >> + EMC_DLL_XFORM_DQS4, >> + EMC_DLL_XFORM_DQS5, >> + EMC_DLL_XFORM_DQS6, >> + EMC_DLL_XFORM_DQS7, >> + EMC_DLL_XFORM_DQS8, >> + EMC_DLL_XFORM_DQS9, >> + EMC_DLL_XFORM_DQS10, >> + EMC_DLL_XFORM_DQS11, >> + EMC_DLL_XFORM_DQS12, >> + EMC_DLL_XFORM_DQS13, >> + EMC_DLL_XFORM_DQS14, >> + EMC_DLL_XFORM_DQS15, >> + EMC_DLL_XFORM_QUSE0, >> + EMC_DLL_XFORM_QUSE1, >> + EMC_DLL_XFORM_QUSE2, >> + EMC_DLL_XFORM_QUSE3, >> + EMC_DLL_XFORM_QUSE4, >> + EMC_DLL_XFORM_QUSE5, >> + EMC_DLL_XFORM_QUSE6, >> + EMC_DLL_XFORM_QUSE7, >> + EMC_DLL_XFORM_ADDR0, >> + EMC_DLL_XFORM_ADDR1, >> + EMC_DLL_XFORM_ADDR2, >> + EMC_DLL_XFORM_ADDR3, >> + EMC_DLL_XFORM_ADDR4, >> + EMC_DLL_XFORM_ADDR5, >> + EMC_DLL_XFORM_QUSE8, >> + EMC_DLL_XFORM_QUSE9, >> + EMC_DLL_XFORM_QUSE10, >> + EMC_DLL_XFORM_QUSE11, >> + EMC_DLL_XFORM_QUSE12, >> + EMC_DLL_XFORM_QUSE13, >> + EMC_DLL_XFORM_QUSE14, >> + EMC_DLL_XFORM_QUSE15, >> + EMC_DLI_TRIM_TXDQS0, >> + EMC_DLI_TRIM_TXDQS1, >> + EMC_DLI_TRIM_TXDQS2, >> + EMC_DLI_TRIM_TXDQS3, >> + EMC_DLI_TRIM_TXDQS4, >> + EMC_DLI_TRIM_TXDQS5, >> + EMC_DLI_TRIM_TXDQS6, >> + EMC_DLI_TRIM_TXDQS7, >> + EMC_DLI_TRIM_TXDQS8, >> + EMC_DLI_TRIM_TXDQS9, >> + EMC_DLI_TRIM_TXDQS10, >> + EMC_DLI_TRIM_TXDQS11, >> + EMC_DLI_TRIM_TXDQS12, >> + EMC_DLI_TRIM_TXDQS13, >> + EMC_DLI_TRIM_TXDQS14, >> + EMC_DLI_TRIM_TXDQS15, >> + EMC_DLL_XFORM_DQ0, >> + EMC_DLL_XFORM_DQ1, >> + EMC_DLL_XFORM_DQ2, >> + EMC_DLL_XFORM_DQ3, >> + EMC_DLL_XFORM_DQ4, >> + EMC_DLL_XFORM_DQ5, >> + EMC_DLL_XFORM_DQ6, >> + EMC_DLL_XFORM_DQ7, >> + EMC_XM2CMDPADCTRL, >> + EMC_XM2CMDPADCTRL4, >> + EMC_XM2CMDPADCTRL5, >> + EMC_XM2DQSPADCTRL2, >> + EMC_XM2DQPADCTRL2, >> + EMC_XM2DQPADCTRL3, >> + EMC_XM2CLKPADCTRL, >> + EMC_XM2CLKPADCTRL2, >> + EMC_XM2COMPPADCTRL, >> + EMC_XM2VTTGENPADCTRL, >> + EMC_XM2VTTGENPADCTRL2, >> + EMC_XM2VTTGENPADCTRL3, >> + EMC_XM2DQSPADCTRL3, >> + EMC_XM2DQSPADCTRL4, >> + EMC_XM2DQSPADCTRL5, >> + EMC_XM2DQSPADCTRL6, >> + EMC_DSR_VTTGEN_DRV, >> + EMC_TXDSRVTTGEN, >> + EMC_FBIO_SPARE, >> + EMC_ZCAL_INTERVAL, >> + EMC_ZCAL_WAIT_CNT, >> + EMC_MRS_WAIT_CNT, >> + EMC_MRS_WAIT_CNT2, >> + EMC_CTT, >> + EMC_CTT_DURATION, >> + EMC_CFG_PIPE, >> + EMC_DYN_SELF_REF_CONTROL, >> + EMC_QPOP >> +}; >> + >> +struct emc_timing { >> + unsigned long rate; >> + >> + /* Store EMC burst data in a union to minimize mistakes. This allows >> + * us to use the same burst data lists as used by the downstream and >> + * ChromeOS kernels. >> + */ > > nit: Comment style. > >> + union { >> + u32 emc_burst_data[ARRAY_SIZE(t124_emc_burst_regs)]; >> + struct { >> + u32 __pad0[121]; >> + u32 emc_xm2dqspadctrl2; >> + u32 __pad1[15]; >> + u32 emc_zcal_interval; >> + u32 __pad2[1]; >> + u32 emc_mrs_wait_cnt; >> + }; >> + }; >> + >> + u32 emc_zcal_cnt_long; >> + u32 emc_auto_cal_interval; >> + u32 emc_ctt_term_ctrl; >> + u32 emc_cfg; >> + u32 emc_cfg_2; >> + u32 emc_sel_dpd_ctrl; >> + u32 __emc_cfg_dig_dll; >> + u32 emc_bgbias_ctl0; >> + u32 emc_auto_cal_config2; >> + u32 emc_auto_cal_config3; >> + u32 emc_auto_cal_config; >> + u32 emc_mode_reset; >> + u32 emc_mode_1; >> + u32 emc_mode_2; >> + u32 emc_mode_4; >> +}; >> + >> +struct tegra_emc { >> + struct platform_device *pdev; >> + >> + struct tegra_mc *mc; >> + >> + void __iomem *emc_regs; >> + >> + enum emc_dram_type dram_type; >> + u8 dram_num; >> + >> + struct emc_timing last_timing; >> + struct emc_timing *timings; >> + unsigned int num_timings; >> + >> + bool changing_timing; > > This field is just set to false once, and then never touched anywhere - > is it needed at all? It's not, looks like I missed it when splitting the driver into emc and clk parts. The clk part is using a similar variable. > >> +}; >> + >> +/* * * * * * * * * * * * * * * * * * * * * * * * * * >> + * Timing change sequence functions * >> + * * * * * * * * * * * * * * * * * * * * * * * * * */ >> + >> +static void emc_ccfifo_writel(struct tegra_emc *tegra, u32 val, >> + unsigned long offs) >> +{ >> + writel(val, tegra->emc_regs + EMC_CCFIFO_DATA); >> + writel(offs, tegra->emc_regs + EMC_CCFIFO_ADDR); >> +} >> + >> +static void emc_seq_update_timing(struct tegra_emc *tegra) >> +{ >> + int i; >> + >> + writel(1, tegra->emc_regs + EMC_TIMING_CONTROL); >> + >> + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { >> + if (!(readl(tegra->emc_regs + EMC_STATUS) & >> + EMC_STATUS_TIMING_UPDATE_STALLED)) >> + return; >> + } >> + >> + dev_err(&tegra->pdev->dev, "timing update failed\n"); >> +} >> + >> +static void emc_seq_disable_auto_cal(struct tegra_emc *tegra) >> +{ >> + int i; >> + >> + writel(0, tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); >> + >> + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { >> + if (!(readl(tegra->emc_regs + EMC_AUTO_CAL_STATUS) & >> + EMC_AUTO_CAL_STATUS_ACTIVE)) >> + return; >> + } >> + >> + dev_err(&tegra->pdev->dev, "auto cal disable failed\n"); >> +} >> + >> +static void emc_seq_wait_clkchange(struct tegra_emc *tegra) >> +{ >> + int i; >> + >> + for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { >> + if (readl(tegra->emc_regs + EMC_INTSTATUS) & >> + EMC_INTSTATUS_CLKCHANGE_COMPLETE) >> + return; >> + } >> + >> + dev_err(&tegra->pdev->dev, "clkchange failed\n"); >> +} >> + >> +static void emc_prepare_timing_change(struct tegra_emc *tegra, >> + const struct emc_timing *timing) >> +{ >> + u32 val, val2; >> + bool update = false; >> + int pre_wait = 0; >> + int i; >> + enum emc_dll_change dll_change; >> + >> + if ((tegra->last_timing.emc_mode_1 & 0x1) == (timing->emc_mode_1 >> & 1)) >> + dll_change = DLL_CHANGE_NONE; >> + else if (timing->emc_mode_1 & 1) >> + dll_change = DLL_CHANGE_ON; >> + else >> + dll_change = DLL_CHANGE_OFF; >> + >> + /* Clear CLKCHANGE_COMPLETE interrupts */ >> + >> + writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, >> + tegra->emc_regs + EMC_INTSTATUS); >> + >> + /* Disable dynamic self-refresh */ >> + >> + val = readl(tegra->emc_regs + EMC_CFG); >> + if (val & EMC_CFG_PWR_MASK) { >> + val &= ~EMC_CFG_POWER_FEATURES_MASK; >> + writel(val, tegra->emc_regs + EMC_CFG); >> + >> + pre_wait = 5; >> + } >> + >> + /* Disable SEL_DPD_CTRL for clock change */ >> + >> + val = readl(tegra->emc_regs + EMC_SEL_DPD_CTRL); >> + if (val & (tegra->dram_type == DRAM_TYPE_DDR3 ? >> + EMC_SEL_DPD_CTRL_DDR3_MASK : EMC_SEL_DPD_CTRL_MASK)) { >> + val &= ~(EMC_SEL_DPD_CTRL_DATA_SEL_DPD | >> + EMC_SEL_DPD_CTRL_ODT_SEL_DPD | >> + EMC_SEL_DPD_CTRL_CA_SEL_DPD | >> + EMC_SEL_DPD_CTRL_CLK_SEL_DPD); >> + if (tegra->dram_type == DRAM_TYPE_DDR3) >> + val &= ~EMC_SEL_DPD_CTRL_RESET_SEL_DPD; >> + writel(val, tegra->emc_regs + EMC_SEL_DPD_CTRL); >> + } >> + >> + /* Prepare DQ/DQS for clock change */ >> + >> + val = readl(tegra->emc_regs + EMC_BGBIAS_CTL0); >> + val2 = tegra->last_timing.emc_bgbias_ctl0; >> + if (!(timing->emc_bgbias_ctl0 & >> + EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) && >> + (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) { >> + val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX; >> + update = true; >> + } >> + >> + if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) || >> + (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) { >> + update = true; >> + } >> + >> + if (update) { >> + writel(val2, tegra->emc_regs + EMC_BGBIAS_CTL0); >> + if (pre_wait < 5) >> + pre_wait = 5; >> + } >> + >> + update = false; >> + val = readl(tegra->emc_regs + EMC_XM2DQSPADCTRL2); >> + if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && >> + !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) { >> + val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE; >> + update = true; >> + } >> + >> + if (timing->emc_xm2dqspadctrl2 & >> EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && >> + !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) { >> + val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE; >> + update = true; >> + } >> + >> + if (update) { >> + writel(val, tegra->emc_regs + EMC_XM2DQSPADCTRL2); >> + if (pre_wait < 30) >> + pre_wait = 30; >> + } >> + >> + /* Wait to settle */ >> + >> + if (pre_wait) { >> + emc_seq_update_timing(tegra); >> + udelay(pre_wait); >> + } >> + >> + /* Program CTT_TERM control */ >> + >> + if (tegra->last_timing.emc_ctt_term_ctrl != >> timing->emc_ctt_term_ctrl) { >> + emc_seq_disable_auto_cal(tegra); >> + writel(timing->emc_ctt_term_ctrl, >> + tegra->emc_regs + EMC_CTT_TERM_CTRL); >> + emc_seq_update_timing(tegra); >> + } >> + >> + /* Program burst shadow registers */ >> + >> + for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) >> + __raw_writel(timing->emc_burst_data[i], >> + tegra->emc_regs + t124_emc_burst_regs[i]); >> + >> + tegra_mc_write_emem_configuration(tegra->mc, timing->rate); >> + >> + val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; >> + emc_ccfifo_writel(tegra, val, EMC_CFG); >> + >> + /* Program AUTO_CAL_CONFIG */ >> + >> + if (timing->emc_auto_cal_config2 != >> + tegra->last_timing.emc_auto_cal_config2) >> + emc_ccfifo_writel(tegra, timing->emc_auto_cal_config2, >> + EMC_AUTO_CAL_CONFIG2); >> + if (timing->emc_auto_cal_config3 != >> + tegra->last_timing.emc_auto_cal_config3) >> + emc_ccfifo_writel(tegra, timing->emc_auto_cal_config3, >> + EMC_AUTO_CAL_CONFIG3); >> + if (timing->emc_auto_cal_config != >> + tegra->last_timing.emc_auto_cal_config) { >> + val = timing->emc_auto_cal_config; >> + val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START; >> + emc_ccfifo_writel(tegra, val, EMC_AUTO_CAL_CONFIG); >> + } >> + >> + /* DDR3: predict MRS long wait count */ >> + >> + if (tegra->dram_type == DRAM_TYPE_DDR3 && dll_change == >> DLL_CHANGE_ON) { >> + u32 cnt = 32; >> + >> + if (timing->emc_zcal_interval != 0 && >> + tegra->last_timing.emc_zcal_interval == 0) >> + cnt -= tegra->dram_num * 256; >> + >> + val = timing->emc_mrs_wait_cnt >> + & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK >> + >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT; >> + if (cnt < val) >> + cnt = val; >> + >> + val = timing->emc_mrs_wait_cnt >> + & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; >> + val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) >> + & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; >> + >> + writel(val, tegra->emc_regs + EMC_MRS_WAIT_CNT); >> + } >> + >> + val = timing->emc_cfg_2; >> + val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR; >> + emc_ccfifo_writel(tegra, val, EMC_CFG_2); >> + >> + /* DDR3: Turn off DLL and enter self-refresh */ >> + >> + if (tegra->dram_type == DRAM_TYPE_DDR3 && dll_change == >> DLL_CHANGE_OFF) >> + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_EMRS); >> + >> + /* Disable refresh controller */ >> + >> + emc_ccfifo_writel(tegra, EMC_REFCTRL_DEV_SEL(tegra->dram_num), >> + EMC_REFCTRL); >> + if (tegra->dram_type == DRAM_TYPE_DDR3) >> + emc_ccfifo_writel(tegra, >> + EMC_DRAM_DEV_SEL(tegra->dram_num) >> + | EMC_SELF_REF_CMD_ENABLED, >> + EMC_SELF_REF); >> + >> + /* Flow control marker */ >> + >> + emc_ccfifo_writel(tegra, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); >> + >> + /* DDR3: Exit self-refresh */ >> + >> + if (tegra->dram_type == DRAM_TYPE_DDR3) >> + emc_ccfifo_writel(tegra, >> + EMC_DRAM_DEV_SEL(tegra->dram_num), >> + EMC_SELF_REF); >> + emc_ccfifo_writel(tegra, >> + EMC_REFCTRL_DEV_SEL(tegra->dram_num) >> + | EMC_REFCTRL_ENABLE, >> + EMC_REFCTRL); >> + >> + /* Set DRAM mode registers */ >> + >> + if (tegra->dram_type == DRAM_TYPE_DDR3) { >> + if (timing->emc_mode_1 != tegra->last_timing.emc_mode_1) >> + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_EMRS); >> + if (timing->emc_mode_2 != tegra->last_timing.emc_mode_2) >> + emc_ccfifo_writel(tegra, timing->emc_mode_2, EMC_EMRS2); >> + >> + if ((timing->emc_mode_reset != >> + tegra->last_timing.emc_mode_reset) || >> + dll_change == DLL_CHANGE_ON) { >> + val = timing->emc_mode_reset; >> + if (dll_change == DLL_CHANGE_ON) { >> + val |= EMC_MODE_SET_DLL_RESET; >> + val |= EMC_MODE_SET_LONG_CNT; >> + } else { >> + val &= ~EMC_MODE_SET_DLL_RESET; >> + } >> + emc_ccfifo_writel(tegra, val, EMC_MRS); >> + } >> + } else { >> + if (timing->emc_mode_2 != tegra->last_timing.emc_mode_2) >> + emc_ccfifo_writel(tegra, timing->emc_mode_2, EMC_MRW2); >> + if (timing->emc_mode_1 != tegra->last_timing.emc_mode_1) >> + emc_ccfifo_writel(tegra, timing->emc_mode_1, EMC_MRW); >> + if (timing->emc_mode_4 != tegra->last_timing.emc_mode_4) >> + emc_ccfifo_writel(tegra, timing->emc_mode_4, EMC_MRW4); >> + } >> + >> + /* Issue ZCAL command if turning ZCAL on */ >> + >> + if (timing->emc_zcal_interval != 0 && >> + tegra->last_timing.emc_zcal_interval == 0) { >> + emc_ccfifo_writel(tegra, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); >> + if (tegra->dram_num > 1) >> + emc_ccfifo_writel(tegra, EMC_ZQ_CAL_LONG_CMD_DEV1, >> + EMC_ZQ_CAL); >> + } >> + >> + /* Write to RO register to remove stall after change */ >> + >> + emc_ccfifo_writel(tegra, 0, EMC_CCFIFO_STATUS); >> + >> + if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) >> + emc_ccfifo_writel(tegra, timing->emc_cfg_2, EMC_CFG_2); >> + >> + /* Disable AUTO_CAL for clock change */ >> + >> + emc_seq_disable_auto_cal(tegra); >> + >> + /* Read register to wait until programming has settled */ >> + >> + readl(tegra->emc_regs + EMC_INTSTATUS); >> +} >> + >> +static void emc_complete_timing_change(struct tegra_emc *tegra, >> + const struct emc_timing *timing) >> +{ >> + u32 val; >> + >> + /* Wait until the state machine has settled */ >> + >> + emc_seq_wait_clkchange(tegra); >> + >> + /* Restore AUTO_CAL */ >> + >> + if (timing->emc_ctt_term_ctrl != >> tegra->last_timing.emc_ctt_term_ctrl) >> + writel(timing->emc_auto_cal_interval, >> + tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); >> + >> + /* Restore dynamic self-refresh */ >> + >> + if (timing->emc_cfg & EMC_CFG_PWR_MASK) >> + writel(timing->emc_cfg, tegra->emc_regs + EMC_CFG); >> + >> + /* Set ZCAL wait count */ >> + >> + writel(timing->emc_zcal_cnt_long, tegra->emc_regs + >> EMC_ZCAL_WAIT_CNT); >> + >> + /* LPDDR3: Turn off BGBIAS if low frequency */ >> + >> + if (tegra->dram_type == DRAM_TYPE_LPDDR3 && >> + timing->emc_bgbias_ctl0 & >> + EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) { >> + val = timing->emc_bgbias_ctl0; >> + val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN; >> + val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD; >> + writel(val, tegra->emc_regs + EMC_BGBIAS_CTL0); >> + } else { >> + if (tegra->dram_type == DRAM_TYPE_DDR3 && >> + readl(tegra->emc_regs + EMC_BGBIAS_CTL0) != >> + timing->emc_bgbias_ctl0) { >> + writel(timing->emc_bgbias_ctl0, >> + tegra->emc_regs + EMC_BGBIAS_CTL0); >> + } >> + >> + writel(timing->emc_auto_cal_interval, >> + tegra->emc_regs + EMC_AUTO_CAL_INTERVAL); >> + } >> + >> + /* Wait for timing to settle */ >> + >> + udelay(2); >> + >> + /* Reprogram SEL_DPD_CTRL */ >> + >> + writel(timing->emc_sel_dpd_ctrl, tegra->emc_regs + >> EMC_SEL_DPD_CTRL); >> + emc_seq_update_timing(tegra); >> + >> + tegra->last_timing = *timing; >> +} >> + >> +/* * * * * * * * * * * * * * * * * * * * * * * * * * >> + * Initialization and deinitialization * >> + * * * * * * * * * * * * * * * * * * * * * * * * * */ >> + >> +static void emc_read_current_timing(struct tegra_emc *tegra, >> + struct emc_timing *timing) >> +{ >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(t124_emc_burst_regs); ++i) >> + timing->emc_burst_data[i] = >> + readl(tegra->emc_regs + t124_emc_burst_regs[i]); >> + >> + timing->emc_cfg = readl(tegra->emc_regs + EMC_CFG); >> + >> + timing->emc_auto_cal_interval = 0; >> + timing->emc_zcal_cnt_long = 0; >> + timing->emc_mode_1 = 0; >> + timing->emc_mode_2 = 0; >> + timing->emc_mode_4 = 0; >> + timing->emc_mode_reset = 0; >> +} >> + >> +static int emc_init(struct tegra_emc *tegra) >> +{ >> + tegra->dram_type = readl(tegra->emc_regs + EMC_FBIO_CFG5); >> + tegra->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; >> + tegra->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; >> + >> + tegra->dram_num = tegra_mc_get_emem_device_count(tegra->mc); >> + >> + emc_read_current_timing(tegra, &tegra->last_timing); >> + >> + tegra->changing_timing = false; >> + >> + return 0; >> +} >> + >> +static int load_one_timing_from_dt(struct tegra_emc *tegra, >> + struct emc_timing *timing, >> + struct device_node *node) >> +{ >> + int err; >> + u32 tmp; >> + >> + err = of_property_read_u32(node, "clock-frequency", &tmp); >> + if (err) { >> + dev_err(&tegra->pdev->dev, >> + "timing %s: failed to read rate\n", node->name); >> + return err; >> + } >> + >> + timing->rate = tmp; >> + >> + err = of_property_read_u32_array(node, "nvidia,emc-configuration", >> + timing->emc_burst_data, >> + ARRAY_SIZE(timing->emc_burst_data)); >> + if (err) { >> + dev_err(&tegra->pdev->dev, >> + "timing %s: failed to read emc burst data\n", >> + node->name); >> + return err; >> + } >> + >> +#define EMC_READ_PROP(prop, dtprop) { \ >> + err = of_property_read_u32(node, dtprop, &timing->prop); \ >> + if (err) { \ >> + dev_err(&tegra->pdev->dev, \ >> + "timing %s: failed to read " #prop "\n", \ >> + node->name); \ >> + return err; \ >> + } \ >> +} > > Let's make this static inline and let the compiler decide whether it is > worth expanding it 14 times. > >> + >> + EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") >> + EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") >> + EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") >> + EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") >> + EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") >> + EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") >> + EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0") >> + EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2") >> + EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3") >> + EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config") >> + EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset") >> + EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1") >> + EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2") >> + EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4") >> + >> +#undef EMC_READ_PROP >> + >> + return 0; >> +} >> + >> +static int cmp_timings(const void *_a, const void *_b) >> +{ >> + const struct emc_timing *a = _a; >> + const struct emc_timing *b = _b; >> + >> + if (a->rate < b->rate) >> + return -1; >> + else if (a->rate == b->rate) >> + return 0; >> + else >> + return 1; >> +} >> + >> +static int load_timings_from_dt(struct tegra_emc *tegra, >> + struct device_node *node) >> +{ >> + struct device_node *child; >> + int child_count = of_get_child_count(node); >> + int i = 0, err; >> + >> + tegra->timings = devm_kzalloc(&tegra->pdev->dev, >> + sizeof(struct emc_timing) * child_count, >> + GFP_KERNEL); >> + if (!tegra->timings) >> + return -ENOMEM; >> + >> + tegra->num_timings = child_count; >> + >> + for_each_child_of_node(node, child) { >> + struct emc_timing *timing = tegra->timings + (i++); >> + >> + err = load_one_timing_from_dt(tegra, timing, child); >> + if (err) >> + return err; >> + } >> + >> + sort(tegra->timings, tegra->num_timings, sizeof(struct emc_timing), >> + cmp_timings, NULL); >> + >> + return 0; >> +} >> + >> +static const struct of_device_id tegra_emc_of_match[] = { >> + { .compatible = "nvidia,tegra124-emc" }, >> + {} >> +}; >> +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); >> + >> +static struct tegra_emc *emc_instance; >> + >> +void tegra_emc_prepare_timing_change(unsigned long rate) >> +{ >> + int i; >> + >> + if (!emc_instance) >> + return; >> + >> + for (i = 0; i < emc_instance->num_timings; ++i) { >> + if (emc_instance->timings[i].rate == rate) >> + break; >> + } >> + >> + if (i == emc_instance->num_timings) >> + return; > > Same comment as previous patch - we should probably report this one way > or the other. True. > >> + >> + emc_prepare_timing_change(emc_instance, emc_instance->timings + i); >> +} >> + >> +void tegra_emc_complete_timing_change(unsigned long rate) >> +{ >> + int i; >> + >> + if (!emc_instance) >> + return; >> + >> + for (i = 0; i < emc_instance->num_timings; ++i) { >> + if (emc_instance->timings[i].rate == rate) >> + break; >> + } >> + >> + if (i == emc_instance->num_timings) >> + return; > > Same here. > >> + >> + emc_complete_timing_change(emc_instance, emc_instance->timings + i); >> +} >> + >> +static int tegra_emc_probe(struct platform_device *pdev) >> +{ >> + struct tegra_emc *tegra; >> + struct device_node *node; >> + struct platform_device *mc_pdev; >> + struct resource *res; >> + u32 ram_code, node_ram_code; >> + int err; >> + >> + tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); >> + if (!tegra) >> + return -ENOMEM; >> + >> + tegra->pdev = pdev; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + tegra->emc_regs = devm_ioremap_resource(&pdev->dev, res); >> + if (IS_ERR(tegra->emc_regs)) { >> + dev_err(&pdev->dev, "failed to map EMC regs\n"); >> + return PTR_ERR(tegra->emc_regs); >> + } >> + >> + node = of_parse_phandle(pdev->dev.of_node, >> + "nvidia,memory-controller", 0); >> + if (!node) { >> + dev_err(&pdev->dev, "could not get memory controller\n"); >> + return -ENOENT; >> + } >> + >> + mc_pdev = of_find_device_by_node(node); >> + if (!mc_pdev) >> + return -ENOENT; > > Isn't there a risk that we will return -ENOENT depending on the probe > order? I.e. if this device is probed before the MC device? Yes.. I remember having some trouble with this code. IIRC, I couldn't figure out a way to sanely detect if the MC driver had been probed or not. Clearly this is not good, though. > >> + >> + tegra->mc = platform_get_drvdata(mc_pdev); >> + if (!tegra->mc) >> + return -ENOENT; >> + >> + of_node_put(node); >> + >> + ram_code = tegra_read_ram_code(); >> + >> + tegra->num_timings = 0; >> + >> + for_each_child_of_node(pdev->dev.of_node, node) { >> + if (strcmp(node->name, "timings")) >> + continue; >> + >> + err = of_property_read_u32(node, "nvidia,ram-code", >> + &node_ram_code); >> + if (err) { >> + dev_warn(&pdev->dev, >> + "skipping timing without ram-code\n"); >> + continue; >> + } >> + >> + if (node_ram_code != ram_code) >> + continue; >> + >> + err = load_timings_from_dt(tegra, node); >> + if (err) >> + return err; >> + break; >> + } >> + >> + if (tegra->num_timings == 0) >> + dev_warn(&pdev->dev, "no memory timings registered\n"); >> + >> + err = emc_init(tegra); >> + if (err) { >> + dev_err(&pdev->dev, "initialization failed: %d\n", err); >> + return err; >> + } >> + >> + platform_set_drvdata(pdev, tegra); >> + >> + emc_instance = tegra; >> + >> + return 0; >> +}; >> + >> +static struct platform_driver tegra_emc_driver = { >> + .probe = tegra_emc_probe, >> + .driver = { >> + .name = "tegra-emc", >> + .of_match_table = tegra_emc_of_match, >> + }, >> +}; >> + >> +static int tegra_emc_init(void) >> +{ >> + return platform_driver_register(&tegra_emc_driver); >> +} >> +subsys_initcall(tegra_emc_init); >> + >> +MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>"); >> +MODULE_DESCRIPTION("Tegra124 EMC memory driver"); >> +MODULE_LICENSE("GPL v2"); >> diff --git a/include/soc/tegra/memory.h b/include/soc/tegra/memory.h >> index f307516..0e0a2e9 100644 >> --- a/include/soc/tegra/memory.h >> +++ b/include/soc/tegra/memory.h >> @@ -13,5 +13,7 @@ struct tegra_mc; >> >> void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned >> long rate); >> int tegra_mc_get_emem_device_count(struct tegra_mc *mc); >> +void tegra_emc_prepare_timing_change(unsigned long rate); >> +void tegra_emc_complete_timing_change(unsigned long rate); >> >> #endif /* __SOC_TEGRA_MEMORY_H__ */ >> ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <545B5D15.6030705-/1wQRMveznE@public.gmane.org>]
* Re: [PATCH v3 10/13] memory: tegra: Add EMC (external memory controller) driver [not found] ` <545B5D15.6030705-/1wQRMveznE@public.gmane.org> @ 2014-11-07 16:16 ` Tomeu Vizoso 0 siblings, 0 replies; 23+ messages in thread From: Tomeu Vizoso @ 2014-11-07 16:16 UTC (permalink / raw) To: Mikko Perttunen Cc: Alexandre Courbot, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Javier Martinez Canillas, Mikko Perttunen, Stephen Warren, Thierry Reding, Alexandre Courbot, Grant Likely, Rob Herring, Greg Kroah-Hartman, Paul Gortmaker, Maxime Ripard, Nicolas Ferre, Ivan Khoronzhuk, Alexandre Belloni, Scott Wood, Bharat Bhushan, Santosh Shilimkar, Prabhakar Kushwaha, linux-kernel On 6 November 2014 12:35, Mikko Perttunen <mikko.perttunen-/1wQRMveznE@public.gmane.org> wrote: > On 11/06/2014 09:56 AM, Alexandre Courbot wrote: >> >> On 10/30/2014 01:22 AM, Tomeu Vizoso wrote: >>> +static int tegra_emc_probe(struct platform_device *pdev) >>> +{ >>> + struct tegra_emc *tegra; >>> + struct device_node *node; >>> + struct platform_device *mc_pdev; >>> + struct resource *res; >>> + u32 ram_code, node_ram_code; >>> + int err; >>> + >>> + tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); >>> + if (!tegra) >>> + return -ENOMEM; >>> + >>> + tegra->pdev = pdev; >>> + >>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >>> + tegra->emc_regs = devm_ioremap_resource(&pdev->dev, res); >>> + if (IS_ERR(tegra->emc_regs)) { >>> + dev_err(&pdev->dev, "failed to map EMC regs\n"); >>> + return PTR_ERR(tegra->emc_regs); >>> + } >>> + >>> + node = of_parse_phandle(pdev->dev.of_node, >>> + "nvidia,memory-controller", 0); >>> + if (!node) { >>> + dev_err(&pdev->dev, "could not get memory controller\n"); >>> + return -ENOENT; >>> + } >>> + >>> + mc_pdev = of_find_device_by_node(node); >>> + if (!mc_pdev) >>> + return -ENOENT; >> >> >> Isn't there a risk that we will return -ENOENT depending on the probe >> order? I.e. if this device is probed before the MC device? > > > Yes.. I remember having some trouble with this code. IIRC, I couldn't figure > out a way to sanely detect if the MC driver had been probed or not. Clearly > this is not good, though. Yeah, I found this issue during testing and resorted to subsys_initcall(). Any better ideas? Thanks, Tomeu ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2014-11-07 16:16 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-10-29 16:22 [PATCH v3 00/13] Tegra124 EMC (external memory controller) support Tomeu Vizoso
2014-10-29 16:22 ` [PATCH v3 02/13] of: Document long-ram-code property in nvidia,tegra20-apbmisc Tomeu Vizoso
2014-10-29 16:22 ` [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car Tomeu Vizoso
2014-11-06 6:37 ` Alexandre Courbot
[not found] ` <545B172C.4060105-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-11-06 9:11 ` Tomeu Vizoso
[not found] ` <CAAObsKBe8kigKfEs_ER+1X5fqLw3dZD69XHicEn4cVuQTyoFAw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-11-06 9:15 ` Alexandre Courbot
2014-11-06 15:12 ` Rob Herring
2014-11-07 5:31 ` Alexandre Courbot
2014-11-07 11:35 ` Mikko Perttunen
[not found] ` <545C5927.3010001-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-11-07 13:03 ` Tomeu Vizoso
[not found] ` <CAL_JsqKYSF3JVrXH_dkqRXQrgUU3igzvoK1C2k1Caz-4UuHX6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-11-07 13:10 ` Tomeu Vizoso
2014-10-29 16:22 ` [PATCH v3 05/13] of: Document timings subnode of nvidia,tegra-mc Tomeu Vizoso
[not found] ` <1414599796-30597-6-git-send-email-tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2014-11-06 8:12 ` Alexandre Courbot
[not found] ` <545B2D6B.9030001-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-11-06 10:32 ` Tomeu Vizoso
2014-10-29 16:22 ` [PATCH v3 06/13] of: Add Tegra124 EMC bindings Tomeu Vizoso
2014-10-29 16:22 ` [PATCH v3 07/13] ARM: tegra: Add EMC to Tegra124 device tree Tomeu Vizoso
2014-10-29 16:22 ` [PATCH v3 08/13] ARM: tegra: Add EMC timings to Jetson TK1 " Tomeu Vizoso
[not found] ` <1414599796-30597-9-git-send-email-tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2014-11-06 12:21 ` Nikolaus Schulz
[not found] ` <20141106122149.GC3863-GNrqntRiisjPWV3K8zbkiAH8Oo8bv1DvZkel5v8DVj8@public.gmane.org>
2014-11-07 16:12 ` Tomeu Vizoso
2014-10-29 16:22 ` [PATCH v3 10/13] memory: tegra: Add EMC (external memory controller) driver Tomeu Vizoso
2014-11-06 7:56 ` Alexandre Courbot
[not found] ` <545B29AA.8030006-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-11-06 11:35 ` Mikko Perttunen
[not found] ` <545B5D15.6030705-/1wQRMveznE@public.gmane.org>
2014-11-07 16:16 ` Tomeu Vizoso
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