From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Subject: Re: [PATCH v3 04/13] of: document new emc-timings subnode in nvidia,tegra124-car
Date: Fri, 07 Nov 2014 14:10:57 +0100
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To: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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List-Id: devicetree@vger.kernel.org

On 11/06/2014 04:12 PM, Rob Herring wrote:
> On Thu, Nov 6, 2014 at 12:37 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
>>>                 #clock-cells = <1>;
>>>                 #reset-cells = <1>;
>>>         };
>>> @@ -60,4 +83,23 @@ Example board file:
>>>         &tegra_car {
>>>                 clocks = <&clk_32k> <&osc>;
>>>         };
>>> +
>>> +       clock@0,60006000 {
>>> +               emc-timings@3 {
>>> +                       nvidia,ram-code = <3>;
>>> +
>>> +                       timing@12750000 {
>>> +                               clock-frequency = <12750000>;
>>> +                               nvidia,parent-clock-frequency =
>>> <408000000>;
>>> +                               clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
>>> +                               clock-names = "emc-parent";
> 
> Why do you need both clocks and hardcoded values? clock-frequency is
> the desired freq you want to set TEGRA124_CLK_PLL_P to?

For the EMC clock to run at 12.75 MHz, its parent should become
TEGRA124_CLK_PLL_P and it has to be running at 408 MHz.

> The clocks property really belongs as part of the memory controller
> node or a memory device node.

What would be the rationale for that? The clock provider needs to know
what clock should become the parent of the EMC clock when changing rates.

Thanks,

Tomeu