From: Dinh Nguyen <dinguyen@opensource.altera.com>
To: tthayer@opensource.altera.com, bp@alien8.de,
dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, grant.likely@linaro.org
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com
Subject: Re: [PATCHv5 1/5] arm: socfpga: Enable L2 Cache ECC on startup.
Date: Wed, 12 Nov 2014 01:32:03 -0600 [thread overview]
Message-ID: <54630CF3.6020409@opensource.altera.com> (raw)
In-Reply-To: <1415751263-1830-2-git-send-email-tthayer@opensource.altera.com>
On 11/11/14, 6:14 PM, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> This patch enables the ECC for L2 cache on machine
> startup. The ECC has to be enabled before data is
> is stored in memory otherwise the ECC will fail on
> reads.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> v2: Split OCRAM initialization into separate patch.
>
> v3/4: No change
>
> v5: Remove l2cache.h, use io.h instead of clk-provider.h
> Make copyright header inclusive. Remove MAINTAINERS entry.
> ---
> arch/arm/mach-socfpga/Makefile | 1 +
> arch/arm/mach-socfpga/core.h | 2 ++
> arch/arm/mach-socfpga/l2_cache.c | 41 ++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-socfpga/socfpga.c | 4 +++-
> 4 files changed, 47 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-socfpga/l2_cache.c
>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
next prev parent reply other threads:[~2014-11-12 7:32 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-12 0:14 [PATCHv5 0/5] Add Altera peripheral memories to EDAC framework tthayer
2014-11-12 0:14 ` [PATCHv5 1/5] arm: socfpga: Enable L2 Cache ECC on startup tthayer
2014-11-12 7:32 ` Dinh Nguyen [this message]
2014-11-12 0:14 ` [PATCHv5 2/5] arm: socfpga: Enable OCRAM " tthayer
2014-11-12 7:33 ` Dinh Nguyen
[not found] ` <1415751263-1830-3-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2014-12-02 15:11 ` Mark Rutland
2014-12-02 17:54 ` Thor Thayer
2014-11-12 0:14 ` [PATCHv5 3/5] edac: altera: Remove SDRAM module compile tthayer
2014-11-12 0:14 ` [PATCHv5 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support tthayer
2014-12-02 15:25 ` Mark Rutland
2014-12-02 17:55 ` Thor Thayer
2014-11-12 0:14 ` [PATCHv5 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC tthayer
2014-11-18 20:56 ` [RESEND PATCHv5 " Thor Thayer
2014-12-01 20:47 ` Thor Thayer
2014-12-02 15:01 ` Mark Rutland
2014-12-02 17:51 ` Thor Thayer
2014-12-02 14:57 ` [PATCHv5 " Mark Rutland
2014-12-02 17:55 ` Thor Thayer
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