From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chanwoo Choi Subject: Re: [03/19] clk: samsung: exynos5433: Add clocks using common clock framework Date: Fri, 28 Nov 2014 10:57:17 +0900 Message-ID: <5477D67D.2080407@samsung.com> References: <1417073716-22997-4-git-send-email-cw00.choi@samsung.com> <54770FA2.9090804@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-reply-to: <54770FA2.9090804@samsung.com> Sender: linux-kernel-owner@vger.kernel.org To: Pankaj Dubey Cc: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, kgene.kim@samsung.com, mark.rutland@arm.com, arnd@arndb.de, olof@lixom.net, catalin.marinas@arm.com, will.deacon@arm.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, thomas.abraham@linaro.org, linus.walleij@linaro.org, kyungmin.park@samsung.com, inki.dae@samsung.com, chanho61.park@samsung.com, geunsik.lim@samsung.com, sw0312.kim@samsung.com, jh80.chung@samsung.com, a.kesavan@samsung.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Hi Pankaj, On 11/27/2014 08:48 PM, Pankaj Dubey wrote: > Hi Chanwoo, > > On Thursday 27 November 2014 01:05 PM, Chanwoo Choi wrote: >> This patch adds the support for CMU (Clock Management Units) of Exynos5433 >> which is 64bit SoC and has Octa-cores. This patch supports necessary clocks >> for kernel boot as following: >> - PLL/MMC/UART/MCT/I2C/SPI >> >> Cc: Sylwester Nawrocki >> Cc: Tomasz Figa >> Signed-off-by: Chanwoo Choi >> Acked-by: Inki Dae >> Acked-by: Geunsik Lim >> >> --- >> drivers/clk/samsung/Makefile | 1 + >> drivers/clk/samsung/clk-exynos5433.c | 971 +++++++++++++++++++++++++++++++++ >> include/dt-bindings/clock/exynos5433.h | 200 +++++++ >> 3 files changed, 1172 insertions(+) >> create mode 100644 drivers/clk/samsung/clk-exynos5433.c >> create mode 100644 include/dt-bindings/clock/exynos5433.h >> (snip) >> + >> +static struct samsung_div_clock top_div_clks[] __initdata = { >> + /* DIV_TOP2 */ >> + DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", >> + DIV_TOP2, 0, 3), >> + >> + /* DIV_TOP3 */ >> + DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx", >> + "mout_bus_pll_user", DIV_TOP3, 24, 3), > > Isn't this clock name should be div_aclk_imem_sssx_266 as per UM? You're right. So, I fxied clock name on patch11[1] for CMU_BUSx domains. - [1] [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains /* DIV_TOP3 */ - DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx", + DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", "mout_bus_pll_user", DIV_TOP3, 24, 3), Best Regards, Chanwoo Choi