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Mon, 5 Feb 2024 08:46:50 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 5 Feb 2024 08:46:50 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 5 Feb 2024 08:46:50 -0600 Received: from [172.24.227.94] (uda0132425.dhcp.ti.com [172.24.227.94]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 415EkkLc111910; Mon, 5 Feb 2024 08:46:47 -0600 Message-ID: <547d7069-3457-4ee3-ad1c-fedc9db5da62@ti.com> Date: Mon, 5 Feb 2024 20:16:45 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: ti: Add DT overlay for PCIe + USB3.0 SERDES personality card Content-Language: en-US To: Roger Quadros , CC: , , , , , , , , , , "Kishon Vijay Abraham I" References: <20240126114530.40913-1-rogerq@kernel.org> <20240126114530.40913-4-rogerq@kernel.org> From: Vignesh Raghavendra In-Reply-To: <20240126114530.40913-4-rogerq@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On 26/01/24 17:15, Roger Quadros wrote: > From: Kishon Vijay Abraham I > [...] > # Boards with J7200 SoC > k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo > diff --git a/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso > new file mode 100644 > index 000000000000..c63b7241c005 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso > @@ -0,0 +1,67 @@ > +// SPDX-License-Identifier: GPL-2.0-only OR MIT > +/** > + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM > + * > + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ > + */ > + > +/dts-v1/; > +/plugin/; > +#include > +#include > +#include > + > +#include "k3-pinctrl.h" > + > +&serdes1 { > + status = "okay"; > +}; > + > +&pcie1_rc { > + num-lanes = <1>; > + phys = <&serdes1 PHY_TYPE_PCIE 0>; > + phy-names = "pcie-phy0"; > + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; > + status = "okay"; > +}; > + > +&pcie1_ep { > + num-lanes = <1>; > + phys = <&serdes1 PHY_TYPE_PCIE 0>; > + phy-names = "pcie-phy0"; > +}; > + > +&main_pmx0 { > + usb0_pins_default: usb0_pins_default { No underscores in node-name and also should end with -pins > + pinctrl-single,pins = < > + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ > + >; > + }; > +}; > + > +&serdes0 { > + status = "okay"; > + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; > + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; > +}; > + > +&dwc3_0 { > + status = "okay"; > + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ > + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ > + phys = <&serdes0 PHY_TYPE_USB3 0>; > + phy-names = "usb3-phy"; > +}; > + > +&usb0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&usb0_pins_default>; > + dr_mode = "host"; > + maximum-speed = "super-speed"; > + snps,dis-u1-entry-quirk; > + snps,dis-u2-entry-quirk; > +}; > + > +&usb0_phy { > + status = "okay"; > +}; BTW, this breaks build on 6.8-rc1 DTOVL arch/arm64/boot/dts/ti/k3-am654-gp-evm.dtb Failed to apply 'arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtbo': FDT_ERR_NOTFOUND -- Regards Vignesh