* [PATCH 01/19] clk: samsung: exynos5433: Add clocks using common clock framework
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
[not found] ` <1417510196-6714-2-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
[not found] ` <1417510196-6714-1-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (16 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 106 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5433.c | 967 +++++++++++++++++++++
include/dt-bindings/clock/exynos5433.h | 199 +++++
4 files changed, 1273 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5433.c
create mode 100644 include/dt-bindings/clock/exynos5433.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
new file mode 100644
index 0000000..72cd0ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -0,0 +1,106 @@
+* Samsung Exynos5433 CMU (Clock Management Units)
+
+The Exynos5433 clock controller generates and supplies clock to various
+controllers within the Exynos5433 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
+ which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
+ domains and bus clocks.
+ - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
+ which generates clocks for LLI (Low Latency Interface) IP.
+ - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
+ which generates clocks for DRAM Memory Controller domain.
+ - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
+ which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
+ - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
+ which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
+ - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
+ which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5433.h header and can be used in device
+tree sources.
+
+Example 1: Examples of clock controller nodes are listed below.
+
+ cmu_top: clock-controller@0x10030000 {
+ compatible = "samsung,exynos5433-cmu-top";
+ reg = <0x10030000 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_cpif: clock-controller@0x10fc0000 {
+ compatible = "samsung,exynos5433-cmu-cpif";
+ reg = <0x10fc0000 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_mif: clock-controller@0x105b0000 {
+ compatible = "samsung,exynos5433-cmu-mif";
+ reg = <0x105b0000 0x100c>;
+ #clock-cells = <1>;
+ };
+
+ cmu_peric: clock-controller@0x14c80000 {
+ compatible = "samsung,exynos5433-cmu-peric";
+ reg = <0x14c80000 0x0b08>;
+ #clock-cells = <1>;
+ };
+
+ cmu_peris: clock-controller@0x10040000 {
+ compatible = "samsung,exynos5433-cmu-peris";
+ reg = <0x10040000 0x0b20>;
+ #clock-cells = <1>;
+ };
+
+ cmu_fsys: clock-controller@0x156e0000 {
+ compatible = "samsung,exynos5433-cmu-fsys";
+ reg = <0x156e0000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller.
+
+ serial_0: serial@14C10000 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x14C10000 0x100>;
+ interrupts = <0 421 0>;
+ clocks = <&cmu_peric CLK_PCLK_UART0>,
+ <&cmu_peric CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+ status = "disabled";
+ };
+
+Example 3: SPI controller node that consumes the clock generated by the clock
+ controller.
+
+ spi_0: spi@14d20000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d20000 0x100>;
+ interrupts = <0 432 0>;
+ dmas = <&pdma0 9>, <&pdma0 8>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI0>,
+ <&cmu_top CLK_SCLK_SPI0_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ status = "disabled";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 006c6f2..17e9af7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
+obj-$(CONFIG_ARCH_EXYNOS5433) += clk-exynos5433.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
new file mode 100644
index 0000000..0877663
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -0,0 +1,967 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5443 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include <dt-bindings/clock/exynos5433.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+/*
+ * Register offset definitions for CMU_TOP
+ */
+#define ISP_PLL_LOCK 0x0000
+#define AUD_PLL_LOCK 0x0004
+#define ISP_PLL_CON0 0x0100
+#define ISP_PLL_CON1 0x0104
+#define ISP_PLL_FREQ_DET 0x0108
+#define AUD_PLL_CON0 0x0110
+#define AUD_PLL_CON1 0x0114
+#define AUD_PLL_CON2 0x0118
+#define AUD_PLL_FREQ_DET 0x011c
+#define MUX_SEL_TOP0 0x0200
+#define MUX_SEL_TOP1 0x0204
+#define MUX_SEL_TOP2 0x0208
+#define MUX_SEL_TOP3 0x020c
+#define MUX_SEL_TOP4 0x0210
+#define MUX_SEL_TOP_MSCL 0x0220
+#define MUX_SEL_TOP_CAM1 0x0224
+#define MUX_SEL_TOP_DISP 0x0228
+#define MUX_SEL_TOP_FSYS0 0x0230
+#define MUX_SEL_TOP_FSYS1 0x0234
+#define MUX_SEL_TOP_PERIC0 0x0238
+#define MUX_SEL_TOP_PERIC1 0x023c
+#define MUX_ENABLE_TOP0 0x0300
+#define MUX_ENABLE_TOP1 0x0304
+#define MUX_ENABLE_TOP2 0x0308
+#define MUX_ENABLE_TOP3 0x030c
+#define MUX_ENABLE_TOP4 0x0310
+#define MUX_ENABLE_TOP_MSCL 0x0320
+#define MUX_ENABLE_TOP_CAM1 0x0324
+#define MUX_ENABLE_TOP_DISP 0x0328
+#define MUX_ENABLE_TOP_FSYS0 0x0330
+#define MUX_ENABLE_TOP_FSYS1 0x0334
+#define MUX_ENABLE_TOP_PERIC0 0x0338
+#define MUX_ENABLE_TOP_PERIC1 0x033c
+#define MUX_STAT_TOP0 0x0400
+#define MUX_STAT_TOP1 0x0404
+#define MUX_STAT_TOP2 0x0408
+#define MUX_STAT_TOP3 0x040c
+#define MUX_STAT_TOP4 0x0410
+#define MUX_STAT_TOP_MSCL 0x0420
+#define MUX_STAT_TOP_CAM1 0x0424
+#define MUX_STAT_TOP_FSYS0 0x0430
+#define MUX_STAT_TOP_FSYS1 0x0434
+#define MUX_STAT_TOP_PERIC0 0x0438
+#define MUX_STAT_TOP_PERIC1 0x043c
+#define DIV_TOP0 0x0600
+#define DIV_TOP1 0x0604
+#define DIV_TOP2 0x0608
+#define DIV_TOP3 0x060c
+#define DIV_TOP4 0x0610
+#define DIV_TOP_MSCL 0x0618
+#define DIV_TOP_CAM10 0x061c
+#define DIV_TOP_CAM11 0x0620
+#define DIV_TOP_FSYS0 0x062c
+#define DIV_TOP_FSYS1 0x0630
+#define DIV_TOP_FSYS2 0x0634
+#define DIV_TOP_PERIC0 0x0638
+#define DIV_TOP_PERIC1 0x063c
+#define DIV_TOP_PERIC2 0x0640
+#define DIV_TOP_PERIC3 0x0644
+#define DIV_TOP_PERIC4 0x0648
+#define DIV_TOP_PLL_FREQ_DET 0x064c
+#define DIV_STAT_TOP0 0x0700
+#define DIV_STAT_TOP1 0x0704
+#define DIV_STAT_TOP2 0x0708
+#define DIV_STAT_TOP3 0x070c
+#define DIV_STAT_TOP4 0x0710
+#define DIV_STAT_TOP_MSCL 0x0718
+#define DIV_STAT_TOP_CAM10 0x071c
+#define DIV_STAT_TOP_CAM11 0x0720
+#define DIV_STAT_TOP_FSYS0 0x072c
+#define DIV_STAT_TOP_FSYS1 0x0730
+#define DIV_STAT_TOP_FSYS2 0x0734
+#define DIV_STAT_TOP_PERIC0 0x0738
+#define DIV_STAT_TOP_PERIC1 0x073c
+#define DIV_STAT_TOP_PERIC2 0x0740
+#define DIV_STAT_TOP_PERIC3 0x0744
+#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
+#define ENABLE_ACLK_TOP 0x0800
+#define ENABLE_SCLK_TOP 0x0a00
+#define ENABLE_SCLK_TOP_MSCL 0x0a04
+#define ENABLE_SCLK_TOP_CAM1 0x0a08
+#define ENABLE_SCLK_TOP_DISP 0x0a0c
+#define ENABLE_SCLK_TOP_FSYS 0x0a10
+#define ENABLE_SCLK_TOP_PERIC 0x0a14
+#define ENABLE_IP_TOP 0x0b00
+#define ENABLE_CMU_TOP 0x0c00
+#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
+
+static unsigned long top_clk_regs[] __initdata = {
+ ISP_PLL_LOCK,
+ AUD_PLL_LOCK,
+ ISP_PLL_CON0,
+ ISP_PLL_CON1,
+ ISP_PLL_FREQ_DET,
+ AUD_PLL_CON0,
+ AUD_PLL_CON1,
+ AUD_PLL_CON2,
+ AUD_PLL_FREQ_DET,
+ MUX_SEL_TOP0,
+ MUX_SEL_TOP1,
+ MUX_SEL_TOP2,
+ MUX_SEL_TOP3,
+ MUX_SEL_TOP4,
+ MUX_SEL_TOP_MSCL,
+ MUX_SEL_TOP_CAM1,
+ MUX_SEL_TOP_DISP,
+ MUX_SEL_TOP_FSYS0,
+ MUX_SEL_TOP_FSYS1,
+ MUX_SEL_TOP_PERIC0,
+ MUX_SEL_TOP_PERIC1,
+ MUX_ENABLE_TOP0,
+ MUX_ENABLE_TOP1,
+ MUX_ENABLE_TOP2,
+ MUX_ENABLE_TOP3,
+ MUX_ENABLE_TOP4,
+ MUX_ENABLE_TOP_MSCL,
+ MUX_ENABLE_TOP_CAM1,
+ MUX_ENABLE_TOP_DISP,
+ MUX_ENABLE_TOP_FSYS0,
+ MUX_ENABLE_TOP_FSYS1,
+ MUX_ENABLE_TOP_PERIC0,
+ MUX_ENABLE_TOP_PERIC1,
+ MUX_STAT_TOP0,
+ MUX_STAT_TOP1,
+ MUX_STAT_TOP2,
+ MUX_STAT_TOP3,
+ MUX_STAT_TOP4,
+ MUX_STAT_TOP_MSCL,
+ MUX_STAT_TOP_CAM1,
+ MUX_STAT_TOP_FSYS0,
+ MUX_STAT_TOP_FSYS1,
+ MUX_STAT_TOP_PERIC0,
+ MUX_STAT_TOP_PERIC1,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_TOP2,
+ DIV_TOP3,
+ DIV_TOP4,
+ DIV_TOP_MSCL,
+ DIV_TOP_CAM10,
+ DIV_TOP_CAM11,
+ DIV_TOP_FSYS0,
+ DIV_TOP_FSYS1,
+ DIV_TOP_FSYS2,
+ DIV_TOP_PERIC0,
+ DIV_TOP_PERIC1,
+ DIV_TOP_PERIC2,
+ DIV_TOP_PERIC3,
+ DIV_TOP_PERIC4,
+ DIV_TOP_PLL_FREQ_DET,
+ DIV_STAT_TOP0,
+ DIV_STAT_TOP1,
+ DIV_STAT_TOP2,
+ DIV_STAT_TOP3,
+ DIV_STAT_TOP4,
+ DIV_STAT_TOP_MSCL,
+ DIV_STAT_TOP_CAM10,
+ DIV_STAT_TOP_CAM11,
+ DIV_STAT_TOP_FSYS0,
+ DIV_STAT_TOP_FSYS1,
+ DIV_STAT_TOP_FSYS2,
+ DIV_STAT_TOP_PERIC0,
+ DIV_STAT_TOP_PERIC1,
+ DIV_STAT_TOP_PERIC2,
+ DIV_STAT_TOP_PERIC3,
+ DIV_STAT_TOP_PLL_FREQ_DET,
+ ENABLE_ACLK_TOP,
+ ENABLE_SCLK_TOP,
+ ENABLE_SCLK_TOP_MSCL,
+ ENABLE_SCLK_TOP_CAM1,
+ ENABLE_SCLK_TOP_DISP,
+ ENABLE_SCLK_TOP_FSYS,
+ ENABLE_SCLK_TOP_PERIC,
+ ENABLE_IP_TOP,
+ ENABLE_CMU_TOP,
+ ENABLE_CMU_TOP_DIV_STAT,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_p) = { "fin_pll", "fout_aud_pll", };
+PNAME(mout_isp_pll_p) = { "fin_pll", "fout_isp_pll", };
+PNAME(mout_aud_pll_user_p) = { "fin_pll", "mout_aud_pll", };
+PNAME(mout_mphy_pll_user_p) = { "fin_pll", "sclk_mphy_pll", };
+PNAME(mout_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll", };
+PNAME(mout_bus_pll_user_p) = { "fin_pll", "sclk_bus_pll", };
+PNAME(mout_bus_pll_user_t_p) = { "fin_pll", "mout_bus_pll_user", };
+
+PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
+PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
+PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
+ "mout_mfc_pll_user", };
+PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
+
+PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
+ "mout_mphy_pll_user", };
+PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
+ "mout_mphy_pll_user", };
+PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
+ "mout_mphy_pll_user", };
+
+PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
+PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
+
+PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
+PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
+PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
+PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
+PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
+
+static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
+ FFACTOR(0, "sclk_bus_pll", "fout_bus_pll", 1, 1, 0),
+ FFACTOR(0, "sclk_mfc_pll", "fout_mfc_pll", 1, 1, 0),
+};
+
+static struct samsung_mux_clock top_mux_clks[] __initdata = {
+ /* MUX_SEL_TOP0 */
+ MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
+ 4, 1),
+ MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
+ 0, 1),
+
+ /* MUX_SEL_TOP1 */
+ MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
+ mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
+ MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
+ MUX_SEL_TOP1, 8, 1),
+ MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
+ MUX_SEL_TOP1, 4, 1),
+ MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
+ MUX_SEL_TOP1, 0, 1),
+
+ /* MUX_SEL_TOP2 */
+ MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
+ mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
+ mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
+ mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
+ MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
+ MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
+
+ /* MUX_SEL_TOP3 */
+ MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
+ mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
+ MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
+ mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
+ MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
+ mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
+ MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
+ mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
+ MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+
+ /* MUX_SEL_TOP_MSCL */
+ MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
+ MUX_SEL_TOP_MSCL, 8, 1),
+ MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
+ MUX_SEL_TOP_MSCL, 4, 1),
+ MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_MSCL, 0, 1),
+
+ /* MUX_SEL_TOP_FSYS0 */
+ MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
+ MUX_SEL_TOP_FSYS0, 28, 1),
+ MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_FSYS0, 24, 1),
+ MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
+ MUX_SEL_TOP_FSYS0, 20, 1),
+ MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_FSYS0, 16, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
+ MUX_SEL_TOP_FSYS0, 12, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
+ MUX_SEL_TOP_FSYS0, 8, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
+ MUX_SEL_TOP_FSYS0, 4, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_FSYS0, 0, 1),
+
+ /* MUX_SEL_TOP_PERIC0 */
+ MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 28, 1),
+ MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 24, 1),
+ MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 20, 1),
+ MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 16, 1),
+ MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 12, 1),
+ MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 8, 1),
+ MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 4, 1),
+ MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 0, 1),
+};
+
+static struct samsung_div_clock top_div_clks[] __initdata = {
+ /* DIV_TOP2 */
+ DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
+ DIV_TOP2, 0, 3),
+
+ /* DIV_TOP3 */
+ DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx",
+ "mout_bus_pll_user", DIV_TOP3, 24, 3),
+ DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
+ "mout_bus_pll_user", DIV_TOP3, 20, 3),
+ DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
+ "mout_bus_pll_user", DIV_TOP3, 16, 3),
+ DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
+ "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
+ DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
+ "mout_bus_pll_user", DIV_TOP3, 8, 3),
+ DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
+ "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
+ DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
+ "mout_bus_pll_user", DIV_TOP3, 0, 3),
+
+ /* DIV_TOP_FSYS0 */
+ DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
+ DIV_TOP_FSYS0, 16, 8),
+ DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
+ DIV_TOP_FSYS0, 12, 4),
+ DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
+ DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
+ DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
+
+ /* DIV_TOP_FSYS1 */
+ DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
+ DIV_TOP_FSYS1, 4, 8),
+ DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
+ DIV_TOP_FSYS1, 0, 4),
+
+ /* DIV_TOP_PERIC0 */
+ DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
+ DIV_TOP_PERIC0, 16, 8),
+ DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
+ DIV_TOP_PERIC0, 12, 4),
+ DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
+ DIV_TOP_PERIC0, 4, 8),
+ DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
+ DIV_TOP_PERIC0, 0, 4),
+
+ /* DIV_TOP_PERIC1 */
+ DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
+ DIV_TOP_PERIC1, 4, 8),
+ DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
+ DIV_TOP_PERIC1, 0, 4),
+
+ /* DIV_TOP_PERIC2 */
+ DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
+ DIV_TOP_PERIC2, 8, 4),
+ DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
+ DIV_TOP_PERIC2, 4, 4),
+ DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
+ DIV_TOP_PERIC2, 0, 4),
+
+ /* DIV_TOP_PERIC4 */
+ DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
+ DIV_TOP_PERIC4, 16, 8),
+ DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
+ DIV_TOP_PERIC4, 12, 4),
+ DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
+ DIV_TOP_PERIC4, 4, 8),
+ DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
+ DIV_TOP_PERIC4, 0, 4),
+};
+
+static struct samsung_gate_clock top_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_TOP */
+ GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
+ ENABLE_ACLK_TOP, 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
+ ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
+ ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_TOP_FSYS */
+ GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
+ ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
+ GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
+ ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
+ GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
+ ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
+
+ /* ENABLE_SCLK_TOP_PERIC */
+ GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
+ ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
+ ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
+ ENABLE_SCLK_TOP_PERIC, 5, 0, 0),
+ GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
+ ENABLE_SCLK_TOP_PERIC, 4, 0, 0),
+ GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
+ ENABLE_SCLK_TOP_PERIC, 3, 0, 0),
+ GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
+ ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
+ ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
+ ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+};
+
+/*
+ * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
+ * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
+ */
+static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
+ PLL_35XX_RATE(2500000000, 625, 6, 0),
+ PLL_35XX_RATE(2400000000, 500, 5, 0),
+ PLL_35XX_RATE(2300000000, 575, 6, 0),
+ PLL_35XX_RATE(2200000000, 550, 6, 0),
+ PLL_35XX_RATE(2100000000, 350, 4, 0),
+ PLL_35XX_RATE(2000000000, 500, 6, 0),
+ PLL_35XX_RATE(1900000000, 475, 6, 0),
+ PLL_35XX_RATE(1800000000, 375, 5, 0),
+ PLL_35XX_RATE(1700000000, 425, 6, 0),
+ PLL_35XX_RATE(1600000000, 400, 6, 0),
+ PLL_35XX_RATE(1500000000, 250, 4, 0),
+ PLL_35XX_RATE(1400000000, 350, 6, 0),
+ PLL_35XX_RATE(1332000000, 222, 4, 0),
+ PLL_35XX_RATE(1300000000, 325, 6, 0),
+ PLL_35XX_RATE(1200000000, 500, 5, 1),
+ PLL_35XX_RATE(1100000000, 550, 6, 1),
+ PLL_35XX_RATE(1086000000, 362, 4, 1),
+ PLL_35XX_RATE(1066000000, 533, 6, 1),
+ PLL_35XX_RATE(1000000000, 500, 6, 1),
+ PLL_35XX_RATE(933000000, 311, 4, 1),
+ PLL_35XX_RATE(921000000, 307, 4, 1),
+ PLL_35XX_RATE(900000000, 375, 5, 1),
+ PLL_35XX_RATE(825000000, 275, 4, 1),
+ PLL_35XX_RATE(800000000, 400, 6, 1),
+ PLL_35XX_RATE(733000000, 733, 12, 1),
+ PLL_35XX_RATE(700000000, 360, 6, 1),
+ PLL_35XX_RATE(667000000, 222, 4, 1),
+ PLL_35XX_RATE(633000000, 211, 4, 1),
+ PLL_35XX_RATE(600000000, 500, 5, 2),
+ PLL_35XX_RATE(552000000, 460, 5, 2),
+ PLL_35XX_RATE(550000000, 550, 6, 2),
+ PLL_35XX_RATE(543000000, 362, 4, 2),
+ PLL_35XX_RATE(533000000, 533, 6, 2),
+ PLL_35XX_RATE(500000000, 500, 6, 2),
+ PLL_35XX_RATE(444000000, 370, 5, 2),
+ PLL_35XX_RATE(420000000, 350, 5, 2),
+ PLL_35XX_RATE(400000000, 400, 6, 2),
+ PLL_35XX_RATE(350000000, 360, 6, 2),
+ PLL_35XX_RATE(333000000, 222, 4, 2),
+ PLL_35XX_RATE(300000000, 500, 5, 3),
+ PLL_35XX_RATE(266000000, 532, 6, 3),
+ PLL_35XX_RATE(200000000, 400, 6, 3),
+ PLL_35XX_RATE(166000000, 332, 6, 3),
+ PLL_35XX_RATE(160000000, 320, 6, 3),
+ PLL_35XX_RATE(133000000, 552, 6, 4),
+ PLL_35XX_RATE(100000000, 400, 6, 4),
+ { /* sentinel */ }
+};
+
+/* AUD_PLL */
+static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
+ PLL_36XX_RATE(400000000, 200, 3, 2, 0),
+ PLL_36XX_RATE(393216000, 197, 3, 2, -25690),
+ PLL_36XX_RATE(384000000, 128, 2, 2, 0),
+ PLL_36XX_RATE(368640000, 246, 4, 2, -15729),
+ PLL_36XX_RATE(361507200, 181, 3, 2, -16148),
+ PLL_36XX_RATE(338688000, 113, 2, 2, -6816),
+ PLL_36XX_RATE(294912000, 98, 1, 3, 19923),
+ PLL_36XX_RATE(288000000, 96, 1, 3, 0),
+ PLL_36XX_RATE(252000000, 84, 1, 3, 0),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_clock top_pll_clks[] __initdata = {
+ PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
+ ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
+ PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
+ AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
+};
+
+static struct samsung_cmu_info top_cmu_info __initdata = {
+ .pll_clks = top_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
+ .mux_clks = top_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
+ .div_clks = top_div_clks,
+ .nr_div_clks = ARRAY_SIZE(top_div_clks),
+ .gate_clks = top_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
+ .fixed_factor_clks = top_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
+ .nr_clk_ids = TOP_NR_CLK,
+ .clk_regs = top_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
+};
+
+static void __init exynos5433_cmu_top_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &top_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
+ exynos5433_cmu_top_init);
+
+/*
+ * Register offset definitions for CMU_CPIF
+ */
+#define MPHY_PLL_LOCK 0x0000
+#define MPHY_PLL_CON0 0x0100
+#define MPHY_PLL_CON1 0x0104
+#define MPHY_PLL_FREQ_DET 0x010c
+#define MUX_SEL_CPIF0 0x0200
+#define DIV_CPIF 0x0600
+#define ENABLE_SCLK_CPIF 0x0a00
+
+static unsigned long cpif_clk_regs[] __initdata = {
+ MPHY_PLL_LOCK,
+ MPHY_PLL_CON0,
+ MPHY_PLL_CON1,
+ MPHY_PLL_FREQ_DET,
+ MUX_SEL_CPIF0,
+ ENABLE_SCLK_CPIF,
+};
+
+/* list of all parent clock list */
+PNAME(mout_mphy_pll_p) = { "fin_pll", "fout_mphy_pll", };
+
+static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
+ PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "fin_pll",
+ MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
+ /* MUX_SEL_CPIF0 */
+ MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
+ 0, 1),
+};
+
+static struct samsung_div_clock cpif_div_clks[] __initdata = {
+ /* DIV_CPIF */
+ DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
+ 0, 6),
+};
+
+static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
+ /* ENABLE_SCLK_CPIF */
+ GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
+ ENABLE_SCLK_CPIF, 9, 0, 0),
+ GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
+ ENABLE_SCLK_CPIF, 4, 0, 0),
+};
+
+static struct samsung_cmu_info cpif_cmu_info __initdata = {
+ .pll_clks = cpif_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
+ .mux_clks = cpif_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
+ .div_clks = cpif_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
+ .gate_clks = cpif_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
+ .nr_clk_ids = CPIF_NR_CLK,
+ .clk_regs = cpif_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
+};
+
+static void __init exynos5433_cmu_cpif_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &cpif_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
+ exynos5433_cmu_cpif_init);
+
+/*
+ * Register offset definitions for CMU_MIF
+ */
+#define MEM0_PLL_LOCK 0x0000
+#define MEM1_PLL_LOCK 0x0004
+#define BUS_PLL_LOCK 0x0008
+#define MFC_PLL_LOCK 0x000c
+#define MEM0_PLL_CON0 0x0100
+#define MEM0_PLL_CON1 0x0104
+#define MEM0_PLL_FREQ_DET 0x010c
+#define MEM1_PLL_CON0 0x0110
+#define MEM1_PLL_CON1 0x0114
+#define MEM1_PLL_FREQ_DET 0x011c
+#define BUS_PLL_CON0 0x0120
+#define BUS_PLL_CON1 0x0124
+#define BUS_PLL_FREQ_DET 0x012c
+#define MFC_PLL_CON0 0x0130
+#define MFC_PLL_CON1 0x0134
+#define MFC_PLL_FREQ_DET 0x013c
+
+static unsigned long mif_clk_regs[] __initdata = {
+ MEM0_PLL_LOCK,
+ MEM1_PLL_LOCK,
+ BUS_PLL_LOCK,
+ MFC_PLL_LOCK,
+ MEM0_PLL_CON0,
+ MEM0_PLL_CON1,
+ MEM0_PLL_FREQ_DET,
+ MEM1_PLL_CON0,
+ MEM1_PLL_CON1,
+ MEM1_PLL_FREQ_DET,
+ BUS_PLL_CON0,
+ BUS_PLL_CON1,
+ BUS_PLL_FREQ_DET,
+ MFC_PLL_CON0,
+ MFC_PLL_CON1,
+ MFC_PLL_FREQ_DET,
+};
+
+static struct samsung_pll_clock mif_pll_clks[] __initdata = {
+ PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "fin_pll",
+ MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "fin_pll",
+ MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
+ BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "fin_pll",
+ MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_cmu_info mif_cmu_info __initdata = {
+ .pll_clks = mif_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
+ .nr_clk_ids = MIF_NR_CLK,
+ .clk_regs = mif_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
+};
+
+static void __init exynos5433_cmu_mif_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &mif_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
+ exynos5433_cmu_mif_init);
+
+/*
+ * Register offset definitions for CMU_PERIC
+ */
+#define DIV_PERIC 0x0600
+#define ENABLE_ACLK_PERIC 0x0800
+#define ENABLE_PCLK_PERIC0 0x0900
+#define ENABLE_PCLK_PERIC1 0x0904
+#define ENABLE_SCLK_PERIC 0x0A00
+#define ENABLE_IP_PERIC0 0x0B00
+#define ENABLE_IP_PERIC1 0x0B04
+#define ENABLE_IP_PERIC2 0x0B08
+
+static unsigned long peric_clk_regs[] __initdata = {
+ DIV_PERIC,
+ ENABLE_ACLK_PERIC,
+ ENABLE_PCLK_PERIC0,
+ ENABLE_PCLK_PERIC1,
+ ENABLE_SCLK_PERIC,
+ ENABLE_IP_PERIC0,
+ ENABLE_IP_PERIC1,
+ ENABLE_IP_PERIC2,
+};
+
+static struct samsung_gate_clock peric_gate_clks[] __initdata = {
+ /* ENABLE_PCLK_PERIC0 */
+ GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 23, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 22, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 14, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 13, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 0, CLK_SET_RATE_PARENT, 0),
+
+ /* ENABLE_PCLK_PERIC1 */
+ GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
+ 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
+ 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* ENABLE_SCLK_PERIC */
+ GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
+ 19, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
+ 18, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
+ 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
+ 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
+ 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
+ ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
+ ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
+ ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_cmu_info peric_cmu_info __initdata = {
+ .gate_clks = peric_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
+ .nr_clk_ids = PERIC_NR_CLK,
+ .clk_regs = peric_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
+};
+
+static void __init exynos5433_cmu_peric_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &peric_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
+ exynos5433_cmu_peric_init);
+
+/*
+ * Register offset definitions for CMU_PERIS
+ */
+#define ENABLE_ACLK_PERIS 0x0800
+#define ENABLE_PCLK_PERIS 0x0900
+
+static unsigned long peris_clk_regs[] __initdata = {
+ ENABLE_ACLK_PERIS,
+ ENABLE_PCLK_PERIS,
+};
+
+static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ /* ENABLE_PCLK_PERIS */
+ GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_cmu_info peris_cmu_info __initdata = {
+ .gate_clks = peris_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
+ .nr_clk_ids = PERIS_NR_CLK,
+ .clk_regs = peris_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
+};
+
+static void __init exynos5433_cmu_peris_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &peris_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
+ exynos5433_cmu_peris_init);
+
+/*
+ * Register offset definitions for CMU_FSYS
+ */
+#define MUX_SEL_FSYS0 0x0200
+#define MUX_SEL_FSYS1 0x0204
+#define MUX_SEL_FSYS2 0x0208
+#define MUX_SEL_FSYS3 0x020c
+#define MUX_SEL_FSYS4 0x0210
+#define MUX_ENABLE_FSYS0 0x0300
+#define MUX_ENABLE_FSYS1 0x0304
+#define MUX_ENABLE_FSYS2 0x0308
+#define MUX_ENABLE_FSYS3 0x030c
+#define MUX_ENABLE_FSYS4 0x0310
+#define MUX_STAT_FSYS0 0x0400
+#define MUX_STAT_FSYS1 0x0404
+#define MUX_STAT_FSYS2 0x0408
+#define MUX_STAT_FSYS3 0x040c
+#define MUX_STAT_FSYS4 0x0410
+#define MUX_IGNORE_FSYS2 0x0508
+#define MUX_IGNORE_FSYS3 0x050c
+#define ENABLE_ACLK_FSYS0 0x0800
+#define ENABLE_ACLK_FSYS1 0x0804
+#define ENABLE_PCLK_FSYS 0x0900
+#define ENABLE_SCLK_FSYS 0x0a00
+#define ENABLE_IP_FSYS0 0x0b00
+#define ENABLE_IP_FSYS1 0x0b04
+
+/* list of all parent clock list */
+PNAME(mout_aclk_fsys_200_user_p) = { "fin_pll", "aclk_fsys_200", };
+PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2_fsys", };
+PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1_fsys", };
+PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0_fsys", };
+
+static unsigned long fsys_clk_regs[] __initdata = {
+ MUX_SEL_FSYS0,
+ MUX_SEL_FSYS1,
+ MUX_SEL_FSYS2,
+ MUX_SEL_FSYS3,
+ MUX_SEL_FSYS4,
+ MUX_ENABLE_FSYS0,
+ MUX_ENABLE_FSYS1,
+ MUX_ENABLE_FSYS2,
+ MUX_ENABLE_FSYS3,
+ MUX_ENABLE_FSYS4,
+ MUX_STAT_FSYS0,
+ MUX_STAT_FSYS1,
+ MUX_STAT_FSYS2,
+ MUX_STAT_FSYS3,
+ MUX_STAT_FSYS4,
+ MUX_IGNORE_FSYS2,
+ MUX_IGNORE_FSYS3,
+ ENABLE_ACLK_FSYS0,
+ ENABLE_ACLK_FSYS1,
+ ENABLE_PCLK_FSYS,
+ ENABLE_SCLK_FSYS,
+ ENABLE_IP_FSYS0,
+ ENABLE_IP_FSYS1,
+};
+
+static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
+ /* MUX_SEL_FSYS0 */
+ MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
+ mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
+
+ /* MUX_SEL_FSYS1 */
+ MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
+ mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
+ MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
+ mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
+ mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
+};
+
+static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_FSYS0 */
+ GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_FSYS */
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
+ ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
+ ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
+ ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+
+ /* ENABLE_IP_FSYS0 */
+ GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
+};
+
+static struct samsung_cmu_info fsys_cmu_info __initdata = {
+ .mux_clks = fsys_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
+ .gate_clks = fsys_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
+ .nr_clk_ids = FSYS_NR_CLK,
+ .clk_regs = fsys_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
+};
+
+static void __init exynos5433_cmu_fsys_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &fsys_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
+ exynos5433_cmu_fsys_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
new file mode 100644
index 0000000..ea35d52
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
+#define _DT_BINDINGS_CLOCK_EXYNOS5433_H
+
+/* CMU_TOP */
+#define CLK_FOUT_ISP_PLL 1
+#define CLK_FOUT_AUD_PLL 2
+
+#define CLK_MOUT_AUD_PLL 10
+#define CLK_MOUT_ISP_PLL 11
+#define CLK_MOUT_AUD_PLL_USER_T 12
+#define CLK_MOUT_MPHY_PLL_USER 13
+#define CLK_MOUT_MFC_PLL_USER 14
+#define CLK_MOUT_BUS_PLL_USER 15
+#define CLK_MOUT_ACLK_HEVC_400 16
+#define CLK_MOUT_ACLK_CAM1_333 17
+#define CLK_MOUT_ACLK_CAM1_552_B 18
+#define CLK_MOUT_ACLK_CAM1_552_A 19
+#define CLK_MOUT_ACLK_ISP_DIS_400 20
+#define CLK_MOUT_ACLK_ISP_400 21
+#define CLK_MOUT_ACLK_BUS0_400 22
+#define CLK_MOUT_ACLK_MSCL_400_B 23
+#define CLK_MOUT_ACLK_MSCL_400_A 24
+#define CLK_MOUT_ACLK_GSCL_333 25
+#define CLK_MOUT_ACLK_G2D_400_B 26
+#define CLK_MOUT_ACLK_G2D_400_A 27
+#define CLK_MOUT_SCLK_JPEG_C 28
+#define CLK_MOUT_SCLK_JPEG_B 29
+#define CLK_MOUT_SCLK_JPEG_A 30
+#define CLK_MOUT_SCLK_MMC2_B 31
+#define CLK_MOUT_SCLK_MMC2_A 32
+#define CLK_MOUT_SCLK_MMC1_B 33
+#define CLK_MOUT_SCLK_MMC1_A 34
+#define CLK_MOUT_SCLK_MMC0_D 35
+#define CLK_MOUT_SCLK_MMC0_C 36
+#define CLK_MOUT_SCLK_MMC0_B 37
+#define CLK_MOUT_SCLK_MMC0_A 38
+#define CLK_MOUT_SCLK_SPI4 39
+#define CLK_MOUT_SCLK_SPI3 40
+#define CLK_MOUT_SCLK_UART2 41
+#define CLK_MOUT_SCLK_UART1 42
+#define CLK_MOUT_SCLK_UART0 43
+#define CLK_MOUT_SCLK_SPI2 44
+#define CLK_MOUT_SCLK_SPI1 45
+#define CLK_MOUT_SCLK_SPI0 46
+
+#define CLK_DIV_ACLK_FSYS_200 100
+#define CLK_DIV_ACLK_IMEM_SSSX 101
+#define CLK_DIV_ACLK_IMEM_200 102
+#define CLK_DIV_ACLK_IMEM_266 103
+#define CLK_DIV_ACLK_PERIC_66_B 104
+#define CLK_DIV_ACLK_PERIC_66_A 105
+#define CLK_DIV_ACLK_PERIS_66_B 106
+#define CLK_DIV_ACLK_PERIS_66_A 107
+#define CLK_DIV_SCLK_MMC1_B 108
+#define CLK_DIV_SCLK_MMC1_A 109
+#define CLK_DIV_SCLK_MMC0_B 110
+#define CLK_DIV_SCLK_MMC0_A 111
+#define CLK_DIV_SCLK_MMC2_B 112
+#define CLK_DIV_SCLK_MMC2_A 113
+#define CLK_DIV_SCLK_SPI1_B 114
+#define CLK_DIV_SCLK_SPI1_A 115
+#define CLK_DIV_SCLK_SPI0_B 116
+#define CLK_DIV_SCLK_SPI0_A 117
+#define CLK_DIV_SCLK_SPI2_B 118
+#define CLK_DIV_SCLK_SPI2_A 119
+#define CLK_DIV_SCLK_UART2 120
+#define CLK_DIV_SCLK_UART1 121
+#define CLK_DIV_SCLK_UART0 122
+#define CLK_DIV_SCLK_SPI4_B 123
+#define CLK_DIV_SCLK_SPI4_A 124
+#define CLK_DIV_SCLK_SPI3_B 125
+#define CLK_DIV_SCLK_SPI3_A 126
+
+#define CLK_ACLK_PERIC_66 200
+#define CLK_ACLK_PERIS_66 201
+#define CLK_ACLK_FSYS_200 202
+#define CLK_SCLK_MMC2_FSYS 203
+#define CLK_SCLK_MMC1_FSYS 204
+#define CLK_SCLK_MMC0_FSYS 205
+#define CLK_SCLK_SPI4_PERIC 206
+#define CLK_SCLK_SPI3_PERIC 207
+#define CLK_SCLK_UART2_PERIC 208
+#define CLK_SCLK_UART1_PERIC 209
+#define CLK_SCLK_UART0_PERIC 210
+#define CLK_SCLK_SPI2_PERIC 211
+#define CLK_SCLK_SPI1_PERIC 212
+#define CLK_SCLK_SPI0_PERIC 213
+
+#define TOP_NR_CLK 214
+
+/* CMU_CPIF */
+#define CLK_FOUT_MPHY_PLL 1
+
+#define CLK_MOUT_MPHY_PLL 2
+
+#define CLK_DIV_SCLK_MPHY 10
+
+#define CLK_SCLK_MPHY_PLL 11
+#define CLK_SCLK_UFS_MPHY 11
+
+#define CPIF_NR_CLK 12
+
+/* CMU_MIF */
+#define CLK_FOUT_MEM0_PLL 1
+#define CLK_FOUT_MEM1_PLL 2
+#define CLK_FOUT_BUS_PLL 3
+#define CLK_FOUT_MFC_PLL 4
+
+#define MIF_NR_CLK 5
+
+/* CMU_PERIC */
+#define CLK_PCLK_SPI2 1
+#define CLK_PCLK_SPI1 2
+#define CLK_PCLK_SPI0 3
+#define CLK_PCLK_UART2 4
+#define CLK_PCLK_UART1 5
+#define CLK_PCLK_UART0 6
+#define CLK_PCLK_HSI2C3 7
+#define CLK_PCLK_HSI2C2 8
+#define CLK_PCLK_HSI2C1 9
+#define CLK_PCLK_HSI2C0 10
+#define CLK_PCLK_I2C7 11
+#define CLK_PCLK_I2C6 12
+#define CLK_PCLK_I2C5 13
+#define CLK_PCLK_I2C4 14
+#define CLK_PCLK_I2C3 15
+#define CLK_PCLK_I2C2 16
+#define CLK_PCLK_I2C1 17
+#define CLK_PCLK_I2C0 18
+#define CLK_PCLK_SPI4 19
+#define CLK_PCLK_SPI3 20
+#define CLK_PCLK_HSI2C11 21
+#define CLK_PCLK_HSI2C10 22
+#define CLK_PCLK_HSI2C9 23
+#define CLK_PCLK_HSI2C8 24
+#define CLK_PCLK_HSI2C7 25
+#define CLK_PCLK_HSI2C6 26
+#define CLK_PCLK_HSI2C5 27
+#define CLK_PCLK_HSI2C4 28
+#define CLK_SCLK_SPI4 29
+#define CLK_SCLK_SPI3 30
+#define CLK_SCLK_SPI2 31
+#define CLK_SCLK_SPI1 32
+#define CLK_SCLK_SPI0 33
+#define CLK_SCLK_UART2 34
+#define CLK_SCLK_UART1 35
+#define CLK_SCLK_UART0 36
+
+#define PERIC_NR_CLK 37
+
+/* CMU_PERIS */
+#define CLK_PCLK_HPM_APBIF 1
+#define CLK_PCLK_TMU1_APBIF 2
+#define CLK_PCLK_TMU0_APBIF 3
+#define CLK_PCLK_PMU_PERIS 4
+#define CLK_PCLK_SYSREG_PERIS 5
+#define CLK_PCLK_CMU_TOP_APBIF 6
+#define CLK_PCLK_WDT_APOLLO 7
+#define CLK_PCLK_WDT_ATLAS 8
+#define CLK_PCLK_MCT 9
+#define CLK_PCLK_HDMI_CEC 10
+
+#define PERIS_NR_CLK 11
+
+/* CMU_FSYS */
+#define CLK_MOUT_ACLK_FSYS_200_USER 1
+#define CLK_MOUT_SCLK_MMC2_USER 2
+#define CLK_MOUT_SCLK_MMC1_USER 3
+#define CLK_MOUT_SCLK_MMC0_USER 4
+
+#define CLK_ACLK_PCIE 50
+#define CLK_ACLK_PDMA1 51
+#define CLK_ACLK_TSI 52
+#define CLK_ACLK_MMC2 53
+#define CLK_ACLK_MMC1 54
+#define CLK_ACLK_MMC0 55
+#define CLK_ACLK_UFS 56
+#define CLK_ACLK_USBHOST20 57
+#define CLK_ACLK_USBHOST30 58
+#define CLK_ACLK_USBDRD30 59
+#define CLK_ACLK_PDMA0 60
+#define CLK_SCLK_MMC2 61
+#define CLK_SCLK_MMC1 62
+#define CLK_SCLK_MMC0 63
+#define CLK_PDMA1 64
+#define CLK_PDMA0 65
+
+#define FSYS_NR_CLK 66
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread[parent not found: <1417510196-6714-1-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>]
* [PATCH 02/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
[not found] ` <1417510196-6714-1-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
@ 2014-12-02 8:49 ` Chanwoo Choi
[not found] ` <1417510196-6714-3-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-12-02 8:49 ` [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain Chanwoo Choi
1 sibling, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: kgene.kim-Sze3O3UU22JBDgjK7y7TUQ, mark.rutland-5wv7dgnIgG8,
marc.zyngier-5wv7dgnIgG8, arnd-r2nGTMty4D4,
olof-nZhT3qVonbNeoWH0uzbU5w, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ,
tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w,
kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ,
inki.dae-Sze3O3UU22JBDgjK7y7TUQ,
chanho61.park-Sze3O3UU22JBDgjK7y7TUQ,
geunsik.lim-Sze3O3UU22JBDgjK7y7TUQ,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jh80.chung-Sze3O3UU22JBDgjK7y7TUQ,
cw00.choi-Sze3O3UU22JBDgjK7y7TUQ,
a.kesavan-Sze3O3UU22JBDgjK7y7TUQ,
pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki <s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Cc: Tomasz Figa <tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Geunsik Lim <geunsik.lim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/clk/samsung/clk-exynos5433.c | 90 ++++++++++++++++++++++++++++++++++
include/dt-bindings/clock/exynos5433.h | 31 +++++++++++-
2 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 0877663..88e8cac 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -208,6 +208,7 @@ PNAME(mout_mphy_pll_user_p) = { "fin_pll", "sclk_mphy_pll", };
PNAME(mout_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll", };
PNAME(mout_bus_pll_user_p) = { "fin_pll", "sclk_bus_pll", };
PNAME(mout_bus_pll_user_t_p) = { "fin_pll", "mout_bus_pll_user", };
+PNAME(mout_mphy_pll_user_t_p) = { "fin_pll", "mout_mphy_pll_user", };
PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
@@ -215,6 +216,12 @@ PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
"mout_mfc_pll_user", };
PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
+PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
+ "mout_mphy_pll_user", };
+PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
+ "mout_bus_pll_user", };
+PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
+
PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
"mout_mphy_pll_user", };
PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
@@ -231,11 +238,26 @@ PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
+PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
+ "fin_pll", "ioclk_spdif_extclk", };
+PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "fin_pll",
+ "mout_aud_pll_user_t",};
+PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "fin_pll",
+ "mout_aud_pll_user_t",};
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, "sclk_bus_pll", "fout_bus_pll", 1, 1, 0),
FFACTOR(0, "sclk_mfc_pll", "fout_mfc_pll", 1, 1, 0),
};
+static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
+ /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
+ FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
+ FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
+ /* Xi2s1SDI input clock for SPDIF */
+ FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
+};
+
static struct samsung_mux_clock top_mux_clks[] __initdata = {
/* MUX_SEL_TOP0 */
MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
@@ -281,6 +303,14 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+ /* MUX_SEL_TOP4 */
+ MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
+ mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
+ mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
+ mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
+
/* MUX_SEL_TOP_MSCL */
MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
MUX_SEL_TOP_MSCL, 8, 1),
@@ -289,6 +319,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
MUX_SEL_TOP_MSCL, 0, 1),
+ /* MUX_SEL_TOP_CAM1 */
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
+ MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
+
/* MUX_SEL_TOP_FSYS0 */
MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
MUX_SEL_TOP_FSYS0, 28, 1),
@@ -307,6 +351,16 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
MUX_SEL_TOP_FSYS0, 0, 1),
+ /* MUX_SEL_TOP_FSYS1 */
+ MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_FSYS1, 12, 1),
+ MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
+ mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
+ MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
+ MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
+
/* MUX_SEL_TOP_PERIC0 */
MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 28, 1),
@@ -324,6 +378,16 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
MUX_SEL_TOP_PERIC0, 4, 1),
MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 0, 1),
+
+ /* MUX_SEL_TOP_PERIC1 */
+ MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
+ MUX_SEL_TOP_PERIC1, 16, 1),
+ MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
+ MUX_SEL_TOP_PERIC1, 12, 2),
+ MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
+ MUX_SEL_TOP_PERIC1, 4, 2),
+ MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
+ MUX_SEL_TOP_PERIC1, 0, 2),
};
static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -387,6 +451,16 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
DIV_TOP_PERIC2, 0, 4),
+ /* DIV_TOP_PERIC3 */
+ DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
+ DIV_TOP_PERIC3, 16, 6),
+ DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
+ DIV_TOP_PERIC3, 8, 8),
+ DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
+ DIV_TOP_PERIC3, 4, 4),
+ DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
+ DIV_TOP_PERIC3, 0, 4),
+
/* DIV_TOP_PERIC4 */
DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
DIV_TOP_PERIC4, 16, 8),
@@ -420,6 +494,12 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
+ ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
+ ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
+ ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
ENABLE_SCLK_TOP_PERIC, 5, 0, 0),
GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
@@ -432,6 +512,14 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* MUX_ENABLE_TOP_PERIC1 */
+ GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
+ MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
+ GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
+ MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
+ GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
+ MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
};
/*
@@ -518,6 +606,8 @@ static struct samsung_cmu_info top_cmu_info __initdata = {
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
+ .fixed_clks = top_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.fixed_factor_clks = top_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
.nr_clk_ids = TOP_NR_CLK,
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index ea35d52..e0f7928 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -51,6 +51,23 @@
#define CLK_MOUT_SCLK_SPI2 44
#define CLK_MOUT_SCLK_SPI1 45
#define CLK_MOUT_SCLK_SPI0 46
+#define CLK_MOUT_ACLK_MFC_400_C 47
+#define CLK_MOUT_ACLK_MFC_400_B 48
+#define CLK_MOUT_ACLK_MFC_400_A 49
+#define CLK_MOUT_SCLK_ISP_SENSOR2 50
+#define CLK_MOUT_SCLK_ISP_SENSOR1 51
+#define CLK_MOUT_SCLK_ISP_SENSOR0 52
+#define CLK_MOUT_SCLK_ISP_UART 53
+#define CLK_MOUT_SCLK_ISP_SPI1 54
+#define CLK_MOUT_SCLK_ISP_SPI0 55
+#define CLK_MOUT_SCLK_PCIE_100 56
+#define CLK_MOUT_SCLK_UFSUNIPRO 57
+#define CLK_MOUT_SCLK_USBHOST30 58
+#define CLK_MOUT_SCLK_USBDRD30 59
+#define CLK_MOUT_SCLK_SLIMBUS 60
+#define CLK_MOUT_SCLK_SPDIF 61
+#define CLK_MOUT_SCLK_AUDIO1 62
+#define CLK_MOUT_SCLK_AUDIO0 63
#define CLK_DIV_ACLK_FSYS_200 100
#define CLK_DIV_ACLK_IMEM_SSSX 101
@@ -79,6 +96,10 @@
#define CLK_DIV_SCLK_SPI4_A 124
#define CLK_DIV_SCLK_SPI3_B 125
#define CLK_DIV_SCLK_SPI3_A 126
+#define CLK_DIV_SCLK_I2S1 127
+#define CLK_DIV_SCLK_PCM1 128
+#define CLK_DIV_SCLK_AUDIO1 129
+#define CLK_DIV_SCLK_AUDIO0 130
#define CLK_ACLK_PERIC_66 200
#define CLK_ACLK_PERIS_66 201
@@ -94,8 +115,14 @@
#define CLK_SCLK_SPI2_PERIC 211
#define CLK_SCLK_SPI1_PERIC 212
#define CLK_SCLK_SPI0_PERIC 213
-
-#define TOP_NR_CLK 214
+#define CLK_SCLK_SPDIF_PERIC 214
+#define CLK_SCLK_I2S1_PERIC 215
+#define CLK_SCLK_PCM1_PERIC 216
+#define CLK_SCLK_SLIMBUS 217
+#define CLK_SCLK_AUDIO1 218
+#define CLK_SCLK_AUDIO0 219
+
+#define TOP_NR_CLK 220
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
--
1.8.5.5
--
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^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
[not found] ` <1417510196-6714-1-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-12-02 8:49 ` [PATCH 02/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-08 11:31 ` Pankaj Dubey
1 sibling, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: kgene.kim-Sze3O3UU22JBDgjK7y7TUQ, mark.rutland-5wv7dgnIgG8,
marc.zyngier-5wv7dgnIgG8, arnd-r2nGTMty4D4,
olof-nZhT3qVonbNeoWH0uzbU5w, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ,
tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w,
kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ,
inki.dae-Sze3O3UU22JBDgjK7y7TUQ,
chanho61.park-Sze3O3UU22JBDgjK7y7TUQ,
geunsik.lim-Sze3O3UU22JBDgjK7y7TUQ,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jh80.chung-Sze3O3UU22JBDgjK7y7TUQ,
cw00.choi-Sze3O3UU22JBDgjK7y7TUQ,
a.kesavan-Sze3O3UU22JBDgjK7y7TUQ,
pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Inha Song
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki <s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Cc: Tomasz Figa <tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.]
Signed-off-by: Inha Song <ideal.song-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Geunsik Lim <geunsik.lim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/clk/samsung/clk-exynos5433.c | 80 +++++++++++++++++++++++++++++++++-
include/dt-bindings/clock/exynos5433.h | 34 ++++++++++++++-
2 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 88e8cac..a48b36c 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
/* Xi2s1SDI input clock for SPDIF */
FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
+ /* XspiCLK[4:0] input clock for SPI */
+ FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
+ FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
+ FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
+ FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
+ FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
+ /* Xi2s1SCLK input clock for I2S1_BCLK */
+ FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
};
static struct samsung_mux_clock top_mux_clks[] __initdata = {
@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
* Register offset definitions for CMU_PERIC
*/
#define DIV_PERIC 0x0600
+#define DIV_STAT_PERIC 0x0700
#define ENABLE_ACLK_PERIC 0x0800
#define ENABLE_PCLK_PERIC0 0x0900
#define ENABLE_PCLK_PERIC1 0x0904
@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
static unsigned long peric_clk_regs[] __initdata = {
DIV_PERIC,
+ DIV_STAT_PERIC,
ENABLE_ACLK_PERIC,
ENABLE_PCLK_PERIC0,
ENABLE_PCLK_PERIC1,
@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = {
ENABLE_IP_PERIC2,
};
+static struct samsung_div_clock peric_div_clks[] __initdata = {
+ /* DIV_PERIC */
+ DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "fin_pll", DIV_PERIC, 4, 8),
+ DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "fin_pll", DIV_PERIC, 0, 4),
+};
+
static struct samsung_gate_clock peric_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_PERIC */
+ GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_PCLK_PERIC0 */
+ GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 31, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 28, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 26, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 25, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
23, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
22, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 15,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
14, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
@@ -841,11 +894,34 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
/* ENABLE_SCLK_PERIC */
+ GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
+ ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
+ ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
19, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
18, CLK_SET_RATE_PARENT, 0),
-
+ GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
+ 17, 0, 0),
+ GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
+ 16, 0, 0),
+ GATE(CLK_SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC, 15, 0, 0),
+ GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
+ ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
+ ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
+ ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
+ "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
+ ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
+ ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
+ ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
5, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
@@ -861,6 +937,8 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
};
static struct samsung_cmu_info peric_cmu_info __initdata = {
+ .div_clks = peric_div_clks,
+ .nr_div_clks = ARRAY_SIZE(peric_div_clks),
.gate_clks = peric_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
.nr_clk_ids = PERIC_NR_CLK,
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index e0f7928..8535917 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -181,8 +181,40 @@
#define CLK_SCLK_UART2 34
#define CLK_SCLK_UART1 35
#define CLK_SCLK_UART0 36
+#define CLK_ACLK_AHB2APB_PERIC2P 37
+#define CLK_ACLK_AHB2APB_PERIC1P 38
+#define CLK_ACLK_AHB2APB_PERIC0P 39
+#define CLK_ACLK_PERICNP_66 40
+#define CLK_PCLK_SCI 41
+#define CLK_PCLK_GPIO_FINGER 42
+#define CLK_PCLK_GPIO_ESE 43
+#define CLK_PCLK_PWM 44
+#define CLK_PCLK_SPDIF 45
+#define CLK_PCLK_PCM1 46
+#define CLK_PCLK_I2S1 47
+#define CLK_PCLK_ADCIF 48
+#define CLK_PCLK_GPIO_TOUCH 49
+#define CLK_PCLK_GPIO_NFC 50
+#define CLK_PCLK_GPIO_PERIC 51
+#define CLK_PCLK_PMU_PERIC 52
+#define CLK_PCLK_SYSREG_PERIC 53
+#define CLK_SCLK_IOCLK_SPI4 54
+#define CLK_SCLK_IOCLK_SPI3 55
+#define CLK_SCLK_SCI 56
+#define CLK_SCLK_SC_IN 57
+#define CLK_SCLK_PWM 58
+#define CLK_SCLK_IOCLK_SPI2 59
+#define CLK_SCLK_IOCLK_SPI1 60
+#define CLK_SCLK_IOCLK_SPI0 61
+#define CLK_SCLK_IOCLK_I2S1_BCLK 62
+#define CLK_SCLK_SPDIF 63
+#define CLK_SCLK_PCM1 64
+#define CLK_SCLK_I2S1 65
-#define PERIC_NR_CLK 37
+#define CLK_DIV_SCLK_SCI 70
+#define CLK_DIV_SCLK_SC_IN 71
+
+#define PERIC_NR_CLK 72
/* CMU_PERIS */
#define CLK_PCLK_HPM_APBIF 1
--
1.8.5.5
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^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
2014-12-02 8:49 ` [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain Chanwoo Choi
@ 2014-12-08 11:31 ` Pankaj Dubey
[not found] ` <54858C13.8020704-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
0 siblings, 1 reply; 44+ messages in thread
From: Pankaj Dubey @ 2014-12-08 11:31 UTC (permalink / raw)
To: Chanwoo Choi, linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, a.kesavan, devicetree, linux-arm-kernel, Inha Song
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds missing divider/gate clocks of CMU_PERIC domain
> which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
> external input clock which has 'ioclk_*' prefix.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> [ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.]
> Signed-off-by: Inha Song <ideal.song@samsung.com>
> Acked-by: Inki Dae <inki.dae@samsung.com>
> Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos5433.c | 80 +++++++++++++++++++++++++++++++++-
> include/dt-bindings/clock/exynos5433.h | 34 ++++++++++++++-
> 2 files changed, 112 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index 88e8cac..a48b36c 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
> FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
> /* Xi2s1SDI input clock for SPDIF */
> FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
> + /* XspiCLK[4:0] input clock for SPI */
> + FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
> + FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
> + FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
> + FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
> + FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
> + /* Xi2s1SCLK input clock for I2S1_BCLK */
> + FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
> };
>
> static struct samsung_mux_clock top_mux_clks[] __initdata = {
> @@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
> * Register offset definitions for CMU_PERIC
> */
> #define DIV_PERIC 0x0600
> +#define DIV_STAT_PERIC 0x0700
> #define ENABLE_ACLK_PERIC 0x0800
> #define ENABLE_PCLK_PERIC0 0x0900
> #define ENABLE_PCLK_PERIC1 0x0904
> @@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
>
> static unsigned long peric_clk_regs[] __initdata = {
> DIV_PERIC,
> + DIV_STAT_PERIC,
IMO, this line should have been added in first place itself when you
added peric_clk_regs.
> ENABLE_ACLK_PERIC,
> ENABLE_PCLK_PERIC0,
> ENABLE_PCLK_PERIC1,
> @@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = {
> ENABLE_IP_PERIC2,
> };
>
> +static struct samsung_div_clock peric_div_clks[] __initdata = {
> + /* DIV_PERIC */
> + DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "fin_pll", DIV_PERIC, 4, 8),
As per UM I have DIV_SCLK_SCI has 4 bit wide as [7:4] please cross verify.
> + DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "fin_pll", DIV_PERIC, 0, 4),
> +};
> +
> static struct samsung_gate_clock peric_gate_clks[] __initdata = {
> + /* ENABLE_ACLK_PERIC */
> + GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
> + ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
> + ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
> + ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
> + ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
> +
> /* ENABLE_PCLK_PERIC0 */
> + GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> + 31, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
> + ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
> + ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> + 28, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> + 26, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> + 25, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> + 24, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> 23, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> 22, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> 21, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> + 20, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
> + ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
> + ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
> + ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
> + ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
> + ENABLE_PCLK_PERIC0, 15,
> + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
> GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> 14, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
> @@ -841,11 +894,34 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
> ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
>
> /* ENABLE_SCLK_PERIC */
> + GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
> + ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
> + ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
> 19, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
> 18, CLK_SET_RATE_PARENT, 0),
> -
> + GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
> + 17, 0, 0),
> + GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
> + 16, 0, 0),
> + GATE(CLK_SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC, 15, 0, 0),
> + GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
> + ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
> + ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
> + ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
> + "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
> + CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
> + ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
> + ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
> + ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
> 5, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
> @@ -861,6 +937,8 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
> };
>
> static struct samsung_cmu_info peric_cmu_info __initdata = {
> + .div_clks = peric_div_clks,
> + .nr_div_clks = ARRAY_SIZE(peric_div_clks),
> .gate_clks = peric_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
> .nr_clk_ids = PERIC_NR_CLK,
> diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
> index e0f7928..8535917 100644
> --- a/include/dt-bindings/clock/exynos5433.h
> +++ b/include/dt-bindings/clock/exynos5433.h
> @@ -181,8 +181,40 @@
> #define CLK_SCLK_UART2 34
> #define CLK_SCLK_UART1 35
> #define CLK_SCLK_UART0 36
> +#define CLK_ACLK_AHB2APB_PERIC2P 37
> +#define CLK_ACLK_AHB2APB_PERIC1P 38
> +#define CLK_ACLK_AHB2APB_PERIC0P 39
> +#define CLK_ACLK_PERICNP_66 40
> +#define CLK_PCLK_SCI 41
> +#define CLK_PCLK_GPIO_FINGER 42
> +#define CLK_PCLK_GPIO_ESE 43
> +#define CLK_PCLK_PWM 44
> +#define CLK_PCLK_SPDIF 45
> +#define CLK_PCLK_PCM1 46
> +#define CLK_PCLK_I2S1 47
> +#define CLK_PCLK_ADCIF 48
> +#define CLK_PCLK_GPIO_TOUCH 49
> +#define CLK_PCLK_GPIO_NFC 50
> +#define CLK_PCLK_GPIO_PERIC 51
> +#define CLK_PCLK_PMU_PERIC 52
> +#define CLK_PCLK_SYSREG_PERIC 53
> +#define CLK_SCLK_IOCLK_SPI4 54
> +#define CLK_SCLK_IOCLK_SPI3 55
> +#define CLK_SCLK_SCI 56
> +#define CLK_SCLK_SC_IN 57
> +#define CLK_SCLK_PWM 58
> +#define CLK_SCLK_IOCLK_SPI2 59
> +#define CLK_SCLK_IOCLK_SPI1 60
> +#define CLK_SCLK_IOCLK_SPI0 61
> +#define CLK_SCLK_IOCLK_I2S1_BCLK 62
> +#define CLK_SCLK_SPDIF 63
> +#define CLK_SCLK_PCM1 64
> +#define CLK_SCLK_I2S1 65
>
> -#define PERIC_NR_CLK 37
> +#define CLK_DIV_SCLK_SCI 70
> +#define CLK_DIV_SCLK_SC_IN 71
> +
> +#define PERIC_NR_CLK 72
>
> /* CMU_PERIS */
> #define CLK_PCLK_HPM_APBIF 1
>
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 04/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
2014-12-02 8:49 ` [PATCH 01/19] clk: samsung: exynos5433: Add clocks using common clock framework Chanwoo Choi
[not found] ` <1417510196-6714-1-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
@ 2014-12-02 8:49 ` Chanwoo Choi
[not found] ` <1417510196-6714-5-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-12-02 8:49 ` [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain Chanwoo Choi
` (14 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: mark.rutland, jh80.chung, geunsik.lim, kgene.kim, arnd, cw00.choi,
marc.zyngier, catalin.marinas, will.deacon, tomasz.figa,
a.kesavan, inki.dae, sw0312.kim, kyungmin.park, linux-arm-kernel,
s.nawrocki, pankaj.dubey, olof, chanho61.park, devicetree
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
drivers/clk/samsung/clk-exynos5433.c | 146 ++++++++++++++++++++++++++++++++-
include/dt-bindings/clock/exynos5433.h | 33 +++++++-
2 files changed, 176 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index a48b36c..7e4612f 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -248,6 +248,7 @@ PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "fin_pll",
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, "sclk_bus_pll", "fout_bus_pll", 1, 1, 0),
FFACTOR(0, "sclk_mfc_pll", "fout_mfc_pll", 1, 1, 0),
+ FFACTOR(0, "oscclk_efuse_common", "fin_pll", 1, 1, 0),
};
static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
@@ -957,15 +958,69 @@ CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
/*
* Register offset definitions for CMU_PERIS
*/
-#define ENABLE_ACLK_PERIS 0x0800
-#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_ACLK_PERIS 0x0800
+#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
+#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
+#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
+#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
+#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
+#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
+#define ENABLE_SCLK_PERIS 0x0a00
+#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
+#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
+#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
+#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
+#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
+#define ENABLE_IP_PERIS0 0x0b00
+#define ENABLE_IP_PERIS1 0x0b04
+#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
+#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
+#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
+#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
+#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
+#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
+#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
static unsigned long peris_clk_regs[] __initdata = {
ENABLE_ACLK_PERIS,
ENABLE_PCLK_PERIS,
+ ENABLE_PCLK_PERIS_SECURE_TZPC,
+ ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
+ ENABLE_SCLK_PERIS,
+ ENABLE_SCLK_PERIS_SECURE_SECKEY,
+ ENABLE_SCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
+ ENABLE_SCLK_PERIS_SECURE_OTP_CON,
+ ENABLE_IP_PERIS0,
+ ENABLE_IP_PERIS1,
+ ENABLE_IP_PERIS_SECURE_TZPC,
+ ENABLE_IP_PERIS_SECURE_SECKEY,
+ ENABLE_IP_PERIS_SECURE_CHIPID,
+ ENABLE_IP_PERIS_SECURE_TOPRTC,
+ ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
+ ENABLE_IP_PERIS_SECURE_OTP_CON,
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_PERIS */
+ GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_PCLK_PERIS */
GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
@@ -987,6 +1042,93 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = {
ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_TZPC */
+ GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
+ GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
+ GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
+ GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
+ GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
+ GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
+ GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
+ GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
+ GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
+ GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
+ GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
+ GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
+ GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
+ GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
+ GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
+ GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
+ GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
+ "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
+ GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
+ "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
+ GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
+ "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS */
+ GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS, 10, 0, 0),
+ GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS, 4, 0, 0),
+ GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS, 3, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
+ GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
+ GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
+ GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
+ GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
+ GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
+ GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
};
static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 8535917..48eb6f3 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -227,8 +227,39 @@
#define CLK_PCLK_WDT_ATLAS 8
#define CLK_PCLK_MCT 9
#define CLK_PCLK_HDMI_CEC 10
+#define CLK_ACLK_AHB2APB_PERIS1P 11
+#define CLK_ACLK_AHB2APB_PERIS0P 12
+#define CLK_ACLK_PERISNP_66 13
+#define CLK_PCLK_TZPC12 14
+#define CLK_PCLK_TZPC11 15
+#define CLK_PCLK_TZPC10 16
+#define CLK_PCLK_TZPC9 17
+#define CLK_PCLK_TZPC8 18
+#define CLK_PCLK_TZPC7 19
+#define CLK_PCLK_TZPC6 20
+#define CLK_PCLK_TZPC5 21
+#define CLK_PCLK_TZPC4 22
+#define CLK_PCLK_TZPC3 23
+#define CLK_PCLK_TZPC2 24
+#define CLK_PCLK_TZPC1 25
+#define CLK_PCLK_TZPC0 26
+#define CLK_PCLK_SECKEY_APBIF 27
+#define CLK_PCLK_CHIPID_APBIF 28
+#define CLK_PCLK_TOPRTC 29
+#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30
+#define CLK_PCLK_ANTIRBK_CNT_APBIF 31
+#define CLK_PCLK_OTP_CON_APBIF 32
+#define CLK_SCLK_ASV_TB 33
+#define CLK_SCLK_TMU1 34
+#define CLK_SCLK_TMU0 35
+#define CLK_SCLK_SECKEY 36
+#define CLK_SCLK_CHIPID 37
+#define CLK_SCLK_TOPRTC 38
+#define CLK_SCLK_CUSTOM_EFUSE 39
+#define CLK_SCLK_ANTIRBK_CNT 40
+#define CLK_SCLK_OTP_CON 41
-#define PERIS_NR_CLK 11
+#define PERIS_NR_CLK 42
/* CMU_FSYS */
#define CLK_MOUT_ACLK_FSYS_200_USER 1
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (2 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 04/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-08 11:36 ` Pankaj Dubey
2014-12-02 8:49 ` [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain Chanwoo Choi
` (13 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: mark.rutland, jh80.chung, geunsik.lim, kgene.kim, arnd, cw00.choi,
marc.zyngier, catalin.marinas, will.deacon, tomasz.figa,
a.kesavan, inki.dae, sw0312.kim, kyungmin.park, linux-arm-kernel,
s.nawrocki, pankaj.dubey, olof, chanho61.park, devicetree
This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++
include/dt-bindings/clock/exynos5433.h | 42 +++++-
3 files changed, 193 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 72cd0ba..27dd77b 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -19,6 +19,8 @@ Required Properties:
which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
- "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+ - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
+ which generates clocks for G2D/MDMA IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -70,6 +72,12 @@ Example 1: Examples of clock controller nodes are listed below.
#clock-cells = <1>;
};
+ cmu_g2d: clock-controller@0x12460000 {
+ compatible = "samsung,exynos5433-cmu-g2d";
+ reg = <0x12460000 0x0b08>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 7e4612f..4dec9fc 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -400,6 +400,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
};
static struct samsung_div_clock top_div_clks[] __initdata = {
+ /* DIV_TOP1 */
+ DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
+ DIV_TOP1, 28, 3),
+ DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
+ DIV_TOP1, 24, 3),
+ DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
+ DIV_TOP1, 20, 3),
+ DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
+ DIV_TOP1, 12, 3),
+ DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
+ DIV_TOP1, 8, 3),
+ DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
+ DIV_TOP1, 0, 3),
+
/* DIV_TOP2 */
DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
DIV_TOP2, 0, 3),
@@ -489,6 +503,10 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
+ ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
+ ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
@@ -1275,3 +1293,129 @@ static void __init exynos5433_cmu_fsys_init(struct device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
exynos5433_cmu_fsys_init);
+
+/*
+ * Register offset definitions for CMU_G2D
+ */
+#define MUX_SEL_G2D0 0x0200
+#define MUX_SEL_ENABLE_G2D0 0x0300
+#define MUX_SEL_STAT_G2D0 0x0400
+#define DIV_G2D 0x0600
+#define DIV_STAT_G2D 0x0700
+#define DIV_ENABLE_ACLK_G2D 0x0800
+#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
+#define DIV_ENABLE_PCLK_G2D 0x0900
+#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
+#define DIV_ENABLE_IP_G2D0 0x0b00
+#define DIV_ENABLE_IP_G2D1 0x0b04
+#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
+
+static unsigned long g2d_clk_regs[] __initdata = {
+ MUX_SEL_G2D0,
+ MUX_SEL_ENABLE_G2D0,
+ MUX_SEL_STAT_G2D0,
+ DIV_G2D,
+ DIV_STAT_G2D,
+ DIV_ENABLE_ACLK_G2D,
+ DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
+ DIV_ENABLE_PCLK_G2D,
+ DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
+ DIV_ENABLE_IP_G2D0,
+ DIV_ENABLE_IP_G2D1,
+ DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g2d_266_user_p) = { "fin_pll", "aclk_g2d_266", };
+PNAME(mout_aclk_g2d_400_user_p) = { "fin_pll", "aclk_g2d_400", };
+
+static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
+ /* MUX_SEL_G2D0 */
+ MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
+ mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
+ MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
+ mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
+};
+
+static struct samsung_div_clock g2d_div_clks[] __initdata = {
+ /* DIV_G2D */
+ DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
+ DIV_G2D, 0, 2),
+};
+
+static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
+ /* DIV_ENABLE_ACLK_G2D */
+ GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
+ DIV_ENABLE_ACLK_G2D, 12, 0, 0),
+ GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
+ DIV_ENABLE_ACLK_G2D, 11, 0, 0),
+ GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 10, 0, 0),
+ GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 9, 0, 0),
+ GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 8, 0, 0),
+ GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
+ "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
+ 7, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
+ DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
+ DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
+ DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
+ DIV_ENABLE_ACLK_G2D, 1, 0, 0),
+ GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 0, 0, 0),
+
+ /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
+ GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
+
+ /* DIV_ENABLE_PCLK_G2D */
+ GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 7, 0, 0),
+ GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 6, 0, 0),
+ GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 5, 0, 0),
+ GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 4, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 3, 0, 0),
+ GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
+ 0, 0, 0),
+
+ /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
+ GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
+};
+
+static struct samsung_cmu_info g2d_cmu_info __initdata = {
+ .mux_clks = g2d_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
+ .div_clks = g2d_div_clks,
+ .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
+ .gate_clks = g2d_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
+ .nr_clk_ids = G2D_NR_CLK,
+ .clk_regs = g2d_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
+};
+
+static void __init exynos5433_cmu_g2d_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &g2d_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
+ exynos5433_cmu_g2d_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 48eb6f3..054f767 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -100,6 +100,12 @@
#define CLK_DIV_SCLK_PCM1 128
#define CLK_DIV_SCLK_AUDIO1 129
#define CLK_DIV_SCLK_AUDIO0 130
+#define CLK_DIV_ACLK_GSCL_111 131
+#define CLK_DIV_ACLK_GSCL_333 132
+#define CLK_DIV_ACLK_HEVC_400 133
+#define CLK_DIV_ACLK_MFC_400 134
+#define CLK_DIV_ACLK_G2D_266 135
+#define CLK_DIV_ACLK_G2D_400 136
#define CLK_ACLK_PERIC_66 200
#define CLK_ACLK_PERIS_66 201
@@ -121,8 +127,10 @@
#define CLK_SCLK_SLIMBUS 217
#define CLK_SCLK_AUDIO1 218
#define CLK_SCLK_AUDIO0 219
+#define CLK_ACLK_G2D_266 220
+#define CLK_ACLK_G2D_400 221
-#define TOP_NR_CLK 220
+#define TOP_NR_CLK 222
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -286,4 +294,36 @@
#define FSYS_NR_CLK 66
+/* CMU_G2D */
+#define CLK_MUX_ACLK_G2D_266_USER 1
+#define CLK_MUX_ACLK_G2D_400_USER 2
+
+#define CLK_DIV_PCLK_G2D 3
+
+#define CLK_ACLK_SMMU_MDMA1 4
+#define CLK_ACLK_BTS_MDMA1 5
+#define CLK_ACLK_BTS_G2D 6
+#define CLK_ACLK_ALB_G2D 7
+#define CLK_ACLK_AXIUS_G2DX 8
+#define CLK_ACLK_ASYNCAXI_SYSX 9
+#define CLK_ACLK_AHB2APB_G2D1P 10
+#define CLK_ACLK_AHB2APB_G2D0P 11
+#define CLK_ACLK_XIU_G2DX 12
+#define CLK_ACLK_G2DNP_133 13
+#define CLK_ACLK_G2DND_400 14
+#define CLK_ACLK_MDMA1 15
+#define CLK_ACLK_G2D 16
+#define CLK_ACLK_SMMU_G2D 17
+#define CLK_PCLK_SMMU_MDMA1 18
+#define CLK_PCLK_BTS_MDMA1 19
+#define CLK_PCLK_BTS_G2D 20
+#define CLK_PCLK_ALB_G2D 21
+#define CLK_PCLK_ASYNCAXI_SYSX 22
+#define CLK_PCLK_PMU_G2D 23
+#define CLK_PCLK_SYSREG_G2D 24
+#define CLK_PCLK_G2D 25
+#define CLK_PCLK_SMMU_G2D 26
+
+#define G2D_NR_CLK 27
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
2014-12-02 8:49 ` [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain Chanwoo Choi
@ 2014-12-08 11:36 ` Pankaj Dubey
[not found] ` <54858D2B.3040809-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
0 siblings, 1 reply; 44+ messages in thread
From: Pankaj Dubey @ 2014-12-08 11:36 UTC (permalink / raw)
To: Chanwoo Choi, linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, a.kesavan, devicetree, linux-arm-kernel
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
nit: %s/clocksof/clocks of
> G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
> CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Inki Dae <inki.dae@samsung.com>
> Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
> ---
> .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
> drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++
> include/dt-bindings/clock/exynos5433.h | 42 +++++-
> 3 files changed, 193 insertions(+), 1 deletion(-)
>
Verified all changes in clock file against UM I have with me, all
changes are OK.
With small nit in commit message feel free to add:
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (3 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
[not found] ` <1417510196-6714-7-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-12-02 8:49 ` [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain Chanwoo Choi
` (12 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
drivers/clk/samsung/clk-exynos5433.c | 590 +++++++++++++++++++++++++++++++++
include/dt-bindings/clock/exynos5433.h | 190 ++++++++++-
2 files changed, 779 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 4dec9fc..10197a1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -737,6 +737,66 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
#define MFC_PLL_CON0 0x0130
#define MFC_PLL_CON1 0x0134
#define MFC_PLL_FREQ_DET 0x013c
+#define MUX_SEL_MIF0 0x0200
+#define MUX_SEL_MIF1 0x0204
+#define MUX_SEL_MIF2 0x0208
+#define MUX_SEL_MIF3 0x020c
+#define MUX_SEL_MIF4 0x0210
+#define MUX_SEL_MIF5 0x0214
+#define MUX_SEL_MIF6 0x0218
+#define MUX_SEL_MIF7 0x021c
+#define MUX_ENABLE_MIF0 0x0300
+#define MUX_ENABLE_MIF1 0x0304
+#define MUX_ENABLE_MIF2 0x0308
+#define MUX_ENABLE_MIF3 0x030c
+#define MUX_ENABLE_MIF4 0x0310
+#define MUX_ENABLE_MIF5 0x0314
+#define MUX_ENABLE_MIF6 0x0318
+#define MUX_ENABLE_MIF7 0x031c
+#define MUX_STAT_MIF0 0x0400
+#define MUX_STAT_MIF1 0x0404
+#define MUX_STAT_MIF2 0x0408
+#define MUX_STAT_MIF3 0x040c
+#define MUX_STAT_MIF4 0x0410
+#define MUX_STAT_MIF5 0x0414
+#define MUX_STAT_MIF6 0x0418
+#define MUX_STAT_MIF7 0x041c
+#define DIV_MIF1 0x0604
+#define DIV_MIF2 0x0608
+#define DIV_MIF3 0x060c
+#define DIV_MIF4 0x0610
+#define DIV_MIF5 0x0614
+#define DIV_MIF_PLL_FREQ_DET 0x0618
+#define DIV_STAT_MIF1 0x0704
+#define DIV_STAT_MIF2 0x0708
+#define DIV_STAT_MIF3 0x070c
+#define DIV_STAT_MIF4 0x0710
+#define DIV_STAT_MIF5 0x0714
+#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
+#define ENABLE_ACLK_MIF0 0x0800
+#define ENABLE_ACLK_MIF1 0x0804
+#define ENABLE_ACLK_MIF2 0x0808
+#define ENABLE_ACLK_MIF3 0x080c
+#define ENABLE_PCLK_MIF 0x0900
+#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
+#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
+#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
+#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
+#define ENABLE_SCLK_MIF 0x0a00
+#define ENABLE_IP_MIF0 0x0b00
+#define ENABLE_IP_MIF1 0x0b04
+#define ENABLE_IP_MIF2 0x0b08
+#define ENABLE_IP_MIF3 0x0b0c
+#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
+#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
+#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
+#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
+#define CLKOUT_CMU_MIF 0x0c00
+#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
+#define DREX_FREQ_CTRL0 0x1000
+#define DREX_FREQ_CTRL1 0x1004
+#define PAUSE 0x1008
+#define DDRPHY_LOCK_CTRL 0x100c
static unsigned long mif_clk_regs[] __initdata = {
MEM0_PLL_LOCK,
@@ -755,6 +815,66 @@ static unsigned long mif_clk_regs[] __initdata = {
MFC_PLL_CON0,
MFC_PLL_CON1,
MFC_PLL_FREQ_DET,
+ MUX_SEL_MIF0,
+ MUX_SEL_MIF1,
+ MUX_SEL_MIF2,
+ MUX_SEL_MIF3,
+ MUX_SEL_MIF4,
+ MUX_SEL_MIF5,
+ MUX_SEL_MIF6,
+ MUX_SEL_MIF7,
+ MUX_ENABLE_MIF0,
+ MUX_ENABLE_MIF1,
+ MUX_ENABLE_MIF2,
+ MUX_ENABLE_MIF3,
+ MUX_ENABLE_MIF4,
+ MUX_ENABLE_MIF5,
+ MUX_ENABLE_MIF6,
+ MUX_ENABLE_MIF7,
+ MUX_STAT_MIF0,
+ MUX_STAT_MIF1,
+ MUX_STAT_MIF2,
+ MUX_STAT_MIF3,
+ MUX_STAT_MIF4,
+ MUX_STAT_MIF5,
+ MUX_STAT_MIF6,
+ MUX_STAT_MIF7,
+ DIV_MIF1,
+ DIV_MIF2,
+ DIV_MIF3,
+ DIV_MIF4,
+ DIV_MIF5,
+ DIV_MIF_PLL_FREQ_DET,
+ DIV_STAT_MIF1,
+ DIV_STAT_MIF2,
+ DIV_STAT_MIF3,
+ DIV_STAT_MIF4,
+ DIV_STAT_MIF5,
+ DIV_STAT_MIF_PLL_FREQ_DET,
+ ENABLE_ACLK_MIF0,
+ ENABLE_ACLK_MIF1,
+ ENABLE_ACLK_MIF2,
+ ENABLE_ACLK_MIF3,
+ ENABLE_PCLK_MIF,
+ ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
+ ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
+ ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
+ ENABLE_PCLK_MIF_SECURE_RTC,
+ ENABLE_SCLK_MIF,
+ ENABLE_IP_MIF0,
+ ENABLE_IP_MIF1,
+ ENABLE_IP_MIF2,
+ ENABLE_IP_MIF3,
+ ENABLE_IP_MIF_SECURE_DREX0_TZ,
+ ENABLE_IP_MIF_SECURE_DREX1_TZ,
+ ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
+ ENABLE_IP_MIF_SECURE_RTC,
+ CLKOUT_CMU_MIF,
+ CLKOUT_CMU_MIF_DIV_STAT,
+ DREX_FREQ_CTRL0,
+ DREX_FREQ_CTRL1,
+ PAUSE,
+ DDRPHY_LOCK_CTRL,
};
static struct samsung_pll_clock mif_pll_clks[] __initdata = {
@@ -768,9 +888,479 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = {
MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
};
+/* list of all parent clock list */
+PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
+PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
+PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
+PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
+PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_mfc_pll", };
+PNAME(mout_bus_pll_p) = { "fin_pll", "fout_bus_pll", };
+PNAME(mout_mem1_pll_p) = { "fin_pll", "fout_mem1_pll", };
+PNAME(mout_mem0_pll_p) = { "fin_pll", "fout_mem0_pll", };
+
+PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
+PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
+PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
+PNAME(mout_clkm_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
+PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
+PNAME(mout_clkm_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
+
+PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
+PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
+
+PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
+ "mout_bus_pll_div2", };
+PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
+
+PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
+ "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
+ "mout_mfc_pll_div2", };
+PNAME(mout_sclk_decon_vclk_a_p) = { "fin_pll", "mout_bus_pll_div2", };
+PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
+ "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
+ "mout_mfc_pll_div2", };
+PNAME(mout_sclk_decon_eclk_a_p) = { "fin_pll", "mout_bus_pll_div2", };
+
+PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
+ "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
+ "mout_mfc_pll_div2", };
+PNAME(mout_sclk_decon_tv_eclk_a_p) = { "fin_pll", "mout_bus_pll_div2", };
+PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
+PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsd_a_p) = { "fin_pll", "mout_mfc_pll_div2", };
+
+PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
+PNAME(mout_sclk_dsim0_a_p) = { "fin_pll", "mout_bus_pll_div2", };
+
+PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
+ "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
+ "mout_mfc_pll_div2", };
+PNAME(mout_sclk_decon_tv_vclk_a_p) = { "fin_pll", "mout_bus_pll_div2", };
+PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
+PNAME(mout_sclk_dsim1_a_p) = { "fin_pll", "mout_bus_pll_div2", };
+
+static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
+ /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
+ FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
+ FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
+ FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
+ FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
+};
+
+static struct samsung_mux_clock mif_mux_clks[] __initdata = {
+ /* MUX_SEL_MIF0 */
+ MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
+ MUX_SEL_MIF0, 28, 1),
+ MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
+ MUX_SEL_MIF0, 24, 1),
+ MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
+ MUX_SEL_MIF0, 20, 1),
+ MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
+ MUX_SEL_MIF0, 16, 1),
+ MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
+ 12, 1),
+ MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
+ 8, 1),
+ MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
+ 4, 1),
+ MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
+ 0, 1),
+
+ /* MUX_SEL_MIF1 */
+ MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
+ MUX_SEL_MIF1, 24, 1),
+ MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
+ MUX_SEL_MIF1, 20, 1),
+ MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
+ MUX_SEL_MIF1, 16, 1),
+ MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clkm_phy_c_p,
+ MUX_SEL_MIF1, 12, 1),
+ MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
+ MUX_SEL_MIF1, 8, 1),
+ MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clkm_phy_a_p,
+ MUX_SEL_MIF1, 4, 1),
+
+ /* MUX_SEL_MIF2 */
+ MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
+ mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
+ MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
+ mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
+
+ /* MUX_SEL_MIF3 */
+ MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
+ mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
+ MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
+ mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
+
+ /* MUX_SEL_MIF4 */
+ MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
+ mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
+ MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
+ mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
+ MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
+ mout_sclk_decon_vclk_a_p, MUX_SEL_MIF4, 16, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
+ mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
+ mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
+ mout_sclk_decon_eclk_a_p, MUX_SEL_MIF4, 0, 1),
+
+ /* MUX_SEL_MIF5 */
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
+ mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
+ mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
+ mout_sclk_decon_tv_eclk_a_p, MUX_SEL_MIF5, 16, 1),
+ MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
+ MUX_SEL_MIF5, 8, 1),
+ MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
+ MUX_SEL_MIF5, 4, 1),
+ MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
+ MUX_SEL_MIF5, 0, 1),
+
+ /* MUX_SEL_MIF6 */
+ MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
+ MUX_SEL_MIF6, 8, 1),
+ MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
+ MUX_SEL_MIF6, 4, 1),
+ MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_dsim0_a_p,
+ MUX_SEL_MIF6, 0, 1),
+
+ /* MUX_SEL_MIF7 */
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
+ mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
+ mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
+ mout_sclk_decon_tv_vclk_a_p, MUX_SEL_MIF7, 16, 1),
+ MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
+ MUX_SEL_MIF7, 8, 1),
+ MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
+ MUX_SEL_MIF7, 4, 1),
+ MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_dsim1_a_p,
+ MUX_SEL_MIF7, 0, 1),
+};
+
+static struct samsung_div_clock mif_div_clks[] __initdata = {
+ /* DIV_MIF1 */
+ DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
+ DIV_MIF1, 16, 2),
+ DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
+ 12, 2),
+ DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
+ 8, 2),
+ DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
+ 4, 4),
+
+ /* DIV_MIF2 */
+ DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
+ DIV_MIF2, 20, 3),
+ DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
+ DIV_MIF2, 16, 4),
+ DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
+ DIV_MIF2, 12, 4),
+ DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
+ "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
+ DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
+ DIV_MIF2, 4, 2),
+ DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
+ DIV_MIF2, 0, 3),
+
+ /* DIV_MIF3 */
+ DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
+ DIV_MIF3, 16, 4),
+ DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
+ DIV_MIF3, 4, 3),
+ DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
+ DIV_MIF3, 0, 3),
+
+ /* DIV_MIF4 */
+ DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
+ DIV_MIF4, 24, 4),
+ DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
+ "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
+ DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
+ DIV_MIF4, 16, 4),
+ DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
+ DIV_MIF4, 12, 4),
+ DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
+ "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
+ DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
+ "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
+ DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
+ "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
+
+ /* DIV_MIF5 */
+ DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
+ 0, 3),
+};
+
+static struct samsung_gate_clock mif_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_MIF0 */
+ GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
+ 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
+ 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
+ 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_RCLK_DREX1, "rclk_drex1", "fin_pll", ENABLE_ACLK_MIF0,
+ 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_RCLK_DREX0, "rclk_drex0", "fin_pll", ENABLE_ACLK_MIF0,
+ 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_MIF1 */
+ GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
+ "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
+ "div_aclk_mif_200", ENABLE_ACLK_MIF1,
+ 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
+ "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
+ 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
+ "div_aclk_drex1", ENABLE_ACLK_MIF1,
+ 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
+ "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
+ 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
+ "div_aclk_drex0", ENABLE_ACLK_MIF1,
+ 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
+ "div_aclk_drex1", ENABLE_ACLK_MIF1,
+ 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
+ "div_aclk_drex1", ENABLE_ACLK_MIF1,
+ 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
+ "div_aclk_drex1", ENABLE_ACLK_MIF1,
+ 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
+ "div_aclk_drex0", ENABLE_ACLK_MIF1,
+ 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
+ "div_aclk_drex0", ENABLE_ACLK_MIF1,
+ 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
+ "div_aclk_drex0", ENABLE_ACLK_MIF1,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
+ ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
+ ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
+ ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
+ ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
+ ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
+ ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
+ ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
+ ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
+ ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_MIF2 */
+ GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
+ ENABLE_ACLK_MIF2, 20, 0, 0),
+ GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
+ ENABLE_ACLK_MIF2, 17, 0, 0),
+ GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
+ ENABLE_ACLK_MIF2, 16, 0, 0),
+ GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
+ ENABLE_ACLK_MIF2, 15, 0, 0),
+ GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
+ ENABLE_ACLK_MIF2, 14, 0, 0),
+ GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
+ ENABLE_ACLK_MIF2, 13, 0, 0),
+ GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
+ ENABLE_ACLK_MIF2, 12, 0, 0),
+ GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
+ "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
+ "div_aclk_mif_400", ENABLE_ACLK_MIF2,
+ 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
+ ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
+ "div_aclk_mif_200", ENABLE_ACLK_MIF2,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
+ "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
+
+ /* ENABLE_ACLK_MIF3 */
+ GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
+ ENABLE_ACLK_MIF3, 4, 0, 0),
+ GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
+ ENABLE_ACLK_MIF3, 1, 0, 0),
+ GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
+ ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MIF */
+ GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
+ ENABLE_PCLK_MIF, 29, 0, 0),
+ GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
+ ENABLE_PCLK_MIF, 28, 0, 0),
+ GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
+ ENABLE_PCLK_MIF, 27, 0, 0),
+ GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
+ ENABLE_PCLK_MIF, 26, 0, 0),
+ GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
+ ENABLE_PCLK_MIF, 25, 0, 0),
+ GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
+ ENABLE_PCLK_MIF, 24, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 19, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 18, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
+ GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 11, 0, 0),
+ GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 7, 0, 0),
+ GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 5, 0, 0),
+ GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 2, 0, 0),
+ GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
+ GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
+
+ /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
+ GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
+
+ /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
+ GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
+
+ /* ENABLE_PCLK_MIF_SECURE_RTC */
+ GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
+
+ /* ENABLE_SCLK_MIF */
+ GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
+ ENABLE_SCLK_MIF, 15, 0, 0),
+ GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
+ "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 14, 0, 0),
+ GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
+ ENABLE_SCLK_MIF, 9, 0, 0),
+ GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
+ ENABLE_SCLK_MIF, 8, 0, 0),
+ GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
+ "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 7, 0, 0),
+ GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
+ "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 6, 0, 0),
+ GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
+ "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 5, 0, 0),
+ GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
+ ENABLE_SCLK_MIF, 4, 0, 0),
+};
+
static struct samsung_cmu_info mif_cmu_info __initdata = {
.pll_clks = mif_pll_clks,
.nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
+ .mux_clks = mif_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
+ .div_clks = mif_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mif_div_clks),
+ .gate_clks = mif_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
+ .fixed_factor_clks = mif_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
.nr_clk_ids = MIF_NR_CLK,
.clk_regs = mif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 054f767..3fb1f32 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -149,8 +149,196 @@
#define CLK_FOUT_MEM1_PLL 2
#define CLK_FOUT_BUS_PLL 3
#define CLK_FOUT_MFC_PLL 4
+#define CLK_DOUT_MFC_PLL 5
+#define CLK_DOUT_BUS_PLL 6
+#define CLK_DOUT_MEM1_PLL 7
+#define CLK_DOUT_MEM0_PLL 8
-#define MIF_NR_CLK 5
+#define CLK_MOUT_MFC_PLL_DIV2 10
+#define CLK_MOUT_BUS_PLL_DIV2 11
+#define CLK_MOUT_MEM1_PLL_DIV2 12
+#define CLK_MOUT_MEM0_PLL_DIV2 13
+#define CLK_MOUT_MFC_PLL 14
+#define CLK_MOUT_BUS_PLL 15
+#define CLK_MOUT_MEM1_PLL 16
+#define CLK_MOUT_MEM0_PLL 17
+#define CLK_MOUT_CLK2X_PHY_C 18
+#define CLK_MOUT_CLK2X_PHY_B 19
+#define CLK_MOUT_CLK2X_PHY_A 20
+#define CLK_MOUT_CLKM_PHY_C 21
+#define CLK_MOUT_CLKM_PHY_B 22
+#define CLK_MOUT_CLKM_PHY_A 23
+#define CLK_MOUT_ACLK_MIFNM_200 24
+#define CLK_MOUT_ACLK_MIFNM_400 25
+#define CLK_MOUT_ACLK_DISP_333_B 26
+#define CLK_MOUT_ACLK_DISP_333_A 27
+#define CLK_MOUT_SCLK_DECON_VCLK_C 28
+#define CLK_MOUT_SCLK_DECON_VCLK_B 29
+#define CLK_MOUT_SCLK_DECON_VCLK_A 30
+#define CLK_MOUT_SCLK_DECON_ECLK_C 31
+#define CLK_MOUT_SCLK_DECON_ECLK_B 32
+#define CLK_MOUT_SCLK_DECON_ECLK_A 33
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
+#define CLK_MOUT_SCLK_DSD_C 37
+#define CLK_MOUT_SCLK_DSD_B 38
+#define CLK_MOUT_SCLK_DSD_A 39
+#define CLK_MOUT_SCLK_DSIM0_C 40
+#define CLK_MOUT_SCLK_DSIM0_B 41
+#define CLK_MOUT_SCLK_DSIM0_A 42
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48
+#define CLK_MOUT_SCLK_DSIM1_C 49
+#define CLK_MOUT_SCLK_DSIM1_B 50
+#define CLK_MOUT_SCLK_DSIM1_A 51
+
+#define CLK_DIV_SCLK_HPM_MIF 55
+#define CLK_DIV_ACLK_DREX1 56
+#define CLK_DIV_ACLK_DREX0 57
+#define CLK_DIV_CLK2XPHY 58
+#define CLK_DIV_ACLK_MIF_266 59
+#define CLK_DIV_ACLK_MIFND_133 60
+#define CLK_DIV_ACLK_MIF_133 61
+#define CLK_DIV_ACLK_MIFNM_200 62
+#define CLK_DIV_ACLK_MIF_200 63
+#define CLK_DIV_ACLK_MIF_400 64
+#define CLK_DIV_ACLK_BUS2_400 65
+#define CLK_DIV_ACLK_DISP_333 66
+#define CLK_DIV_ACLK_CPIF_200 67
+#define CLK_DIV_SCLK_DSIM1 68
+#define CLK_DIV_SCLK_DECON_TV_VCLK 69
+#define CLK_DIV_SCLK_DSIM0 70
+#define CLK_DIV_SCLK_DSD 71
+#define CLK_DIV_SCLK_DECON_TV_ECLK 72
+#define CLK_DIV_SCLK_DECON_VCLK 73
+#define CLK_DIV_SCLK_DECON_ECLK 74
+#define CLK_DIV_MIF_PRE 75
+
+#define CLK_CLK2X_PHY1 80
+#define CLK_CLK2X_PHY0 81
+#define CLK_CLKM_PHY1 82
+#define CLK_CLKM_PHY0 83
+#define CLK_RCLK_DREX1 84
+#define CLK_RCLK_DREX0 85
+#define CLK_ACLK_DREX1_TZ 86
+#define CLK_ACLK_DREX0_TZ 87
+#define CLK_ACLK_DREX1_PEREV 88
+#define CLK_ACLK_DREX0_PEREV 89
+#define CLK_ACLK_DREX1_MEMIF 90
+#define CLK_ACLK_DREX0_MEMIF 91
+#define CLK_ACLK_DREX1_SCH 92
+#define CLK_ACLK_DREX0_SCH 93
+#define CLK_ACLK_DREX1_BUSIF 94
+#define CLK_ACLK_DREX0_BUSIF 95
+#define CLK_ACLK_DREX1_BUSIF_RD 96
+#define CLK_ACLK_DREX0_BUSIF_RD 97
+#define CLK_ACLK_DREX1 98
+#define CLK_ACLK_DREX0 99
+#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100
+#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101
+#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102
+#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103
+#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104
+#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105
+#define CLK_ACLK_ASYNCAXIS_CP1 106
+#define CLK_ACLK_ASYNCAXIM_CP1 107
+#define CLK_ACLK_ASYNCAXIS_CP0 108
+#define CLK_ACLK_ASYNCAXIM_CP0 109
+#define CLK_ACLK_ASYNCAXIS_DREX1_3 110
+#define CLK_ACLK_ASYNCAXIM_DREX1_3 111
+#define CLK_ACLK_ASYNCAXIS_DREX1_1 112
+#define CLK_ACLK_ASYNCAXIM_DREX1_1 113
+#define CLK_ACLK_ASYNCAXIS_DREX1_0 114
+#define CLK_ACLK_ASYNCAXIM_DREX1_0 115
+#define CLK_ACLK_ASYNCAXIS_DREX0_3 116
+#define CLK_ACLK_ASYNCAXIM_DREX0_3 117
+#define CLK_ACLK_ASYNCAXIS_DREX0_1 118
+#define CLK_ACLK_ASYNCAXIM_DREX0_1 119
+#define CLK_ACLK_ASYNCAXIS_DREX0_0 120
+#define CLK_ACLK_ASYNCAXIM_DREX0_0 121
+#define CLK_ACLK_AHB2APB_MIF2P 122
+#define CLK_ACLK_AHB2APB_MIF1P 123
+#define CLK_ACLK_AHB2APB_MIF0P 124
+#define CLK_ACLK_IXIU_CCI 125
+#define CLK_ACLK_XIU_MIFSFRX 126
+#define CLK_ACLK_MIFNP_133 127
+#define CLK_ACLK_MIFNM_200 128
+#define CLK_ACLK_MIFND_133 129
+#define CLK_ACLK_MIFND_400 130
+#define CLK_ACLK_CCI 131
+#define CLK_ACLK_MIFND_266 132
+#define CLK_ACLK_PPMU_DREX1S3 133
+#define CLK_ACLK_PPMU_DREX1S1 134
+#define CLK_ACLK_PPMU_DREX1S0 135
+#define CLK_ACLK_PPMU_DREX0S3 136
+#define CLK_ACLK_PPMU_DREX0S1 137
+#define CLK_ACLK_PPMU_DREX0S0 138
+#define CLK_ACLK_BTS_APOLLO 139
+#define CLK_ACLK_BTS_ATLAS 140
+#define CLK_ACLK_ACE_SEL_APOLL 141
+#define CLK_ACLK_ACE_SEL_ATLAS 142
+#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143
+#define CLK_ACLK_AXIUS_ATLAS_CCI 144
+#define CLK_ACLK_AXISYNCDNS_CCI 145
+#define CLK_ACLK_AXISYNCDN_CCI 146
+#define CLK_ACLK_AXISYNCDN_NOC_D 147
+#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148
+#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149
+#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150
+#define CLK_ACLK_BUS2_400 151
+#define CLK_ACLK_DISP_333 152
+#define CLK_ACLK_CPIF_200 153
+#define CLK_PCLK_PPMU_DREX1S3 154
+#define CLK_PCLK_PPMU_DREX1S1 155
+#define CLK_PCLK_PPMU_DREX1S0 156
+#define CLK_PCLK_PPMU_DREX0S3 157
+#define CLK_PCLK_PPMU_DREX0S1 158
+#define CLK_PCLK_PPMU_DREX0S0 159
+#define CLK_PCLK_BTS_APOLLO 160
+#define CLK_PCLK_BTS_ATLAS 161
+#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162
+#define CLK_PCLK_ASYNCAXI_CP1 163
+#define CLK_PCLK_ASYNCAXI_CP0 164
+#define CLK_PCLK_ASYNCAXI_DREX1_3 165
+#define CLK_PCLK_ASYNCAXI_DREX1_1 166
+#define CLK_PCLK_ASYNCAXI_DREX1_0 167
+#define CLK_PCLK_ASYNCAXI_DREX0_3 168
+#define CLK_PCLK_ASYNCAXI_DREX0_1 169
+#define CLK_PCLK_ASYNCAXI_DREX0_0 170
+#define CLK_PCLK_MIFSRVND_133 171
+#define CLK_PCLK_PMU_MIF 172
+#define CLK_PCLK_SYSREG_MIF 173
+#define CLK_PCLK_GPIO_ALIVE 174
+#define CLK_PCLK_ABB 175
+#define CLK_PCLK_PMU_APBIF 176
+#define CLK_PCLK_DDR_PHY1 177
+#define CLK_PCLK_DREX1 178
+#define CLK_PCLK_DDR_PHY0 179
+#define CLK_PCLK_DREX0 180
+#define CLK_PCLK_DREX0_TZ 181
+#define CLK_PCLK_DREX1_TZ 182
+#define CLK_PCLK_MONOTONIC_CNT 183
+#define CLK_PCLK_RTC 184
+#define CLK_SCLK_DSIM1_DISP 185
+#define CLK_SCLK_DECON_TV_VCLK_DISP 186
+#define CLK_SCLK_FREQ_DET_BUS_PLL 187
+#define CLK_SCLK_FREQ_DET_MFC_PLL 188
+#define CLK_SCLK_FREQ_DET_MEM0_PLL 189
+#define CLK_SCLK_FREQ_DET_MEM1_PLL 190
+#define CLK_SCLK_DSIM0_DISP 191
+#define CLK_SCLK_DSD_DISP 192
+#define CLK_SCLK_DECON_TV_ECLK_DISP 193
+#define CLK_SCLK_DECON_VCLK_DISP 194
+#define CLK_SCLK_DECON_ECLK_DISP 195
+#define CLK_SCLK_HPM_MIF 196
+#define CLK_SCLK_MFC_PLL_MIF 197
+#define CLK_SCLK_BUS_PLL 198
+#define CLK_SCLK_BUS_PLL_APOLLO 199
+#define CLK_SCLK_BUS_PLL_ATLAS 200
+
+#define MIF_NR_CLK 201
/* CMU_PERIC */
#define CLK_PCLK_SPI2 1
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (4 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-09 6:06 ` Pankaj Dubey
2014-12-02 8:49 ` [PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain Chanwoo Choi
` (11 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 9 +
drivers/clk/samsung/clk-exynos5433.c | 465 ++++++++++++++++++++-
include/dt-bindings/clock/exynos5433.h | 114 ++++-
3 files changed, 577 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 27dd77b..8d3dad4 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -21,6 +21,8 @@ Required Properties:
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
which generates clocks for G2D/MDMA IPs.
+ - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
+ which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed below.
#clock-cells = <1>;
};
+ cmu_disp: clock-controller@0x13b90000 {
+ compatible = "samsung,exynos5433-cmu-disp";
+ reg = <0x13b90000 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 10197a1..ec23e97 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "fin_pll",
PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "fin_pll",
"mout_aud_pll_user_t",};
+PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, "sclk_bus_pll", "fout_bus_pll", 1, 1, 0),
FFACTOR(0, "sclk_mfc_pll", "fout_mfc_pll", 1, 1, 0),
@@ -397,6 +399,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
MUX_SEL_TOP_PERIC1, 4, 2),
MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
MUX_SEL_TOP_PERIC1, 0, 2),
+
+ /* MUX_SEL_TOP_DISP */
+ MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
+ mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
};
static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -1256,9 +1262,9 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
/* ENABLE_ACLK_MIF3 */
GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
- ENABLE_ACLK_MIF3, 4, 0, 0),
+ ENABLE_ACLK_MIF3, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
- ENABLE_ACLK_MIF3, 1, 0, 0),
+ ENABLE_ACLK_MIF3, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
@@ -1333,21 +1339,30 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
/* ENABLE_SCLK_MIF */
GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
- ENABLE_SCLK_MIF, 15, 0, 0),
+ ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
- "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 14, 0, 0),
+ "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
+ 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
- ENABLE_SCLK_MIF, 9, 0, 0),
+ ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
- ENABLE_SCLK_MIF, 8, 0, 0),
+ ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
- "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 7, 0, 0),
+ "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
+ 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
- "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 6, 0, 0),
+ "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
+ 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
- "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 5, 0, 0),
+ "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
+ 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
- ENABLE_SCLK_MIF, 4, 0, 0),
+ ENABLE_SCLK_MIF, 4, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_TOP_DISP */
+ GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
+ "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
+ CLK_IGNORE_UNUSED, 0),
};
static struct samsung_cmu_info mif_cmu_info __initdata = {
@@ -2009,3 +2024,433 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
exynos5433_cmu_g2d_init);
+
+/*
+ * Register offset definitions for CMU_DISP
+ */
+#define DISP_PLL_LOCK 0x0000
+#define DISP_PLL_CON0 0x0100
+#define DISP_PLL_CON1 0x0104
+#define DISP_PLL_FREQ_DET 0x0108
+#define MUX_SEL_DISP0 0x0200
+#define MUX_SEL_DISP1 0x0204
+#define MUX_SEL_DISP2 0x0208
+#define MUX_SEL_DISP3 0x020c
+#define MUX_SEL_DISP4 0x0210
+#define MUX_ENABLE_DISP0 0x0300
+#define MUX_ENABLE_DISP1 0x0304
+#define MUX_ENABLE_DISP2 0x0308
+#define MUX_ENABLE_DISP3 0x030c
+#define MUX_ENABLE_DISP4 0x0310
+#define MUX_STAT_DISP0 0x0400
+#define MUX_STAT_DISP1 0x0404
+#define MUX_STAT_DISP2 0x0408
+#define MUX_STAT_DISP3 0x040c
+#define MUX_STAT_DISP4 0x0410
+#define MUX_IGNORE_DISP2 0x0508
+#define DIV_DISP 0x0600
+#define DIV_DISP_PLL_FREQ_DET 0x0604
+#define DIV_STAT_DISP 0x0700
+#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
+#define ENABLE_ACLK_DISP0 0x0800
+#define ENABLE_ACLK_DISP1 0x0804
+#define ENABLE_PCLK_DISP 0x0900
+#define ENABLE_SCLK_DISP 0x0a00
+#define ENABLE_IP_DISP0 0x0b00
+#define ENABLE_IP_DISP1 0x0b04
+#define CLKOUT_CMU_DISP 0x0c00
+#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
+
+static unsigned long disp_clk_regs[] __initdata = {
+ DISP_PLL_LOCK,
+ DISP_PLL_CON0,
+ DISP_PLL_CON1,
+ DISP_PLL_FREQ_DET,
+ MUX_SEL_DISP0,
+ MUX_SEL_DISP1,
+ MUX_SEL_DISP2,
+ MUX_SEL_DISP3,
+ MUX_SEL_DISP4,
+ MUX_ENABLE_DISP0,
+ MUX_ENABLE_DISP1,
+ MUX_ENABLE_DISP2,
+ MUX_ENABLE_DISP3,
+ MUX_ENABLE_DISP4,
+ MUX_STAT_DISP0,
+ MUX_STAT_DISP1,
+ MUX_STAT_DISP2,
+ MUX_STAT_DISP3,
+ MUX_STAT_DISP4,
+ MUX_IGNORE_DISP2,
+ DIV_DISP,
+ DIV_DISP_PLL_FREQ_DET,
+ DIV_STAT_DISP,
+ DIV_STAT_DISP_PLL_FREQ_DET,
+ ENABLE_ACLK_DISP0,
+ ENABLE_ACLK_DISP1,
+ ENABLE_PCLK_DISP,
+ ENABLE_SCLK_DISP,
+ ENABLE_IP_DISP0,
+ ENABLE_IP_DISP1,
+ CLKOUT_CMU_DISP,
+ CLKOUT_CMU_DISP_DIV_STAT,
+};
+
+/* list of all parent clock list */
+PNAME(mout_disp_pll_p) = { "fin_pll", "fout_disp_pll", };
+PNAME(mout_sclk_dsim1_user_p) = { "fin_pll", "sclk_dsim1_disp", };
+PNAME(mout_sclk_dsim0_user_p) = { "fin_pll", "sclk_dsim0_disp", };
+PNAME(mout_sclk_dsd_user_p) = { "fin_pll", "sclk_dsd_disp", };
+PNAME(mout_sclk_decon_tv_eclk_user_p) = { "fin_pll",
+ "sclk_decon_tv_eclk_disp", };
+PNAME(mout_sclk_decon_vclk_user_p) = { "fin_pll",
+ "sclk_decon_vclk_disp", };
+PNAME(mout_sclk_decon_eclk_user_p) = { "fin_pll",
+ "sclk_decon_eclk_disp", };
+PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "fin_pll",
+ "sclk_decon_tv_vclk_disp", };
+PNAME(mout_aclk_disp_333_user_p) = { "fin_pll", "aclk_disp_333", };
+
+PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "fin_pll",
+ "phyclk_mipidphy1_bitclkdiv8_phy", };
+PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "fin_pll",
+ "phyclk_mipidphy1_rxclkesc0_phy", };
+PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "fin_pll",
+ "phyclk_mipidphy0_bitclkdiv8_phy", };
+PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "fin_pll",
+ "phyclk_mipidphy0_rxclkesc0_phy", };
+PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "fin_pll",
+ "phyclk_hdmiphy_tmds_clko_phy", };
+PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "fin_pll",
+ "phyclk_hdmiphy_pixel_clko_phy", };
+
+PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
+ "mout_sclk_dsim0_user", };
+PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
+ "mout_sclk_decon_tv_eclk_user", };
+PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
+ "mout_sclk_decon_vclk_user", };
+PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
+ "mout_sclk_decon_eclk_user", };
+
+PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
+ "mout_sclk_dsim1_user", };
+PNAME(mout_sclk_dsim1_a_disp_p) = { "mout_disp_pll",
+ "mout_sclk_dsim0_user", };
+PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
+ "mout_phyclk_hdmiphy_pixel_clko_user",
+ "mout_sclk_decon_tv_vclk_b_disp", };
+PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
+ "mout_sclk_decon_tv_vclk_user", };
+PNAME(mout_sclk_decon_tv_vclk_a_disp_p) = { "mout_disp_pll",
+ "mout_sclk_decon_vclk_user", };
+
+static struct samsung_pll_clock disp_pll_clks[] __initdata = {
+ PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
+ DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
+ /*
+ * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
+ * The divider has fixed value (2) betwwen sclk_rgb_{vclk|tv_vclk}
+ * and sclk_decon_{vclk|tv_vclk}.
+ */
+ FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
+ 1, 2, 0),
+ FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
+ 1, 2, 0),
+};
+
+static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
+ /* PHY clocks from MIPI_DPHY1 */
+ FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
+ 188000000),
+ FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
+ 100000000),
+ /* PHY clocks from MIPI_DPHY0 */
+ FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
+ 188000000),
+ FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
+ 100000000),
+ /* PHY clocks from HDMI_PHY */
+ FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
+ FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
+};
+
+static struct samsung_mux_clock disp_mux_clks[] __initdata = {
+ /* MUX_SEL_DISP0 */
+ MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
+ 0, 1),
+
+ /* MUX_SEL_DISP1 */
+ MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
+ mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
+ MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
+ mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
+ MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
+ MUX_SEL_DISP1, 20, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
+ mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
+ MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
+ mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
+ mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
+ mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
+ MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
+ mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
+
+ /* MUX_SEL_DISP2 */
+ MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
+ "mout_phyclk_mipidphy1_bitclkdiv8_user",
+ mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
+ 20, 1),
+ MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
+ "mout_phyclk_mipidphy1_rxclkesc0_user",
+ mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
+ 16, 1),
+ MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
+ "mout_phyclk_mipidphy0_bitclkdiv8_user",
+ mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
+ 12, 1),
+ MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
+ "mout_phyclk_mipidphy0_rxclkesc0_user",
+ mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
+ 8, 1),
+ MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
+ "mout_phyclk_hdmiphy_tmds_clko_user",
+ mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
+ 4, 1),
+ MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
+ "mout_phyclk_hdmiphy_pixel_clko_user",
+ mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
+ 0, 1),
+
+ /* MUX_SEL_DISP3 */
+ MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
+ MUX_SEL_DISP3, 12, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
+ mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
+ MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
+ mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
+ mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
+
+ /* MUX_SEL_DISP4 */
+ MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
+ mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
+ MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
+ mout_sclk_dsim1_a_disp_p, MUX_SEL_DISP4, 12, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
+ "mout_sclk_decon_tv_vclk_c_disp",
+ mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
+ "mout_sclk_decon_tv_vclk_b_disp",
+ mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
+ "mout_sclk_decon_tv_vclk_a_disp",
+ mout_sclk_decon_tv_vclk_a_disp_p, MUX_SEL_DISP4, 0, 1),
+};
+
+static struct samsung_div_clock disp_div_clks[] __initdata = {
+ /* DIV_DISP */
+ DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
+ "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
+ DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
+ "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
+ DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
+ DIV_DISP, 16, 3),
+ DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
+ "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
+ DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
+ "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
+ DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
+ "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
+ DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
+ DIV_DISP, 0, 2),
+};
+
+static struct samsung_gate_clock disp_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_DISP0 */
+ GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP0, 2, 0, 0),
+ GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP0, 0, 0, 0),
+
+ /* ENABLE_ACLK_DISP1 */
+ GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 25, 0, 0),
+ GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 24, 0, 0),
+ GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
+ GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
+ "div_pclk_disp", ENABLE_ACLK_DISP1,
+ 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
+ "div_pclk_disp", ENABLE_ACLK_DISP1,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
+ "div_pclk_disp", ENABLE_ACLK_DISP1,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
+ ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 7, 0, 0),
+ GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 6, 0, 0),
+ GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
+ GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
+ GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
+ ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_DISP */
+ GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 23, 0, 0),
+ GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 22, 0, 0),
+ GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 21, 0, 0),
+ GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 20, 0, 0),
+ GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 19, 0, 0),
+ GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 18, 0, 0),
+ GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 17, 0, 0),
+ GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 16, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 15, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 14, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 13, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 12, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 11, 0, 0),
+ GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 10, 0, 0),
+ GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 7, 0, 0),
+ GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 6, 0, 0),
+ GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 5, 0, 0),
+ GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 3, 0, 0),
+ GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 2, 0, 0),
+ GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 1, 0, 0),
+
+ /* ENABLE_SCLK_DISP */
+ GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
+ "mout_phyclk_mipidphy1_bitclkdiv8_user",
+ ENABLE_SCLK_DISP, 26, 0, 0),
+ GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
+ "mout_phyclk_mipidphy1_rxclkesc0_user",
+ ENABLE_SCLK_DISP, 25, 0, 0),
+ GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
+ "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
+ GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
+ "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
+ GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
+ ENABLE_SCLK_DISP, 22, 0, 0),
+ GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
+ "div_sclk_decon_tv_vclk_disp",
+ ENABLE_SCLK_DISP, 21, 0, 0),
+ GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
+ "mout_phyclk_mipidphy0_bitclkdiv8_user",
+ ENABLE_SCLK_DISP, 15, 0, 0),
+ GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
+ "mout_phyclk_mipidphy0_rxclkesc0_user",
+ ENABLE_SCLK_DISP, 14, 0, 0),
+ GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
+ "mout_phyclk_hdmiphy_tmds_clko_user",
+ ENABLE_SCLK_DISP, 13, 0, 0),
+ GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
+ "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
+ GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
+ "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
+ GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
+ "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
+ GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
+ "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
+ GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
+ ENABLE_SCLK_DISP, 7, 0, 0),
+ GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
+ ENABLE_SCLK_DISP, 6, 0, 0),
+ GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
+ ENABLE_SCLK_DISP, 5, 0, 0),
+ GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
+ "div_sclk_decon_tv_eclk_disp",
+ ENABLE_SCLK_DISP, 4, 0, 0),
+ GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
+ "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
+ GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
+ "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
+};
+
+static struct samsung_cmu_info disp_cmu_info __initdata = {
+ .pll_clks = disp_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
+ .mux_clks = disp_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
+ .div_clks = disp_div_clks,
+ .nr_div_clks = ARRAY_SIZE(disp_div_clks),
+ .gate_clks = disp_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
+ .fixed_clks = disp_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
+ .fixed_factor_clks = disp_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
+ .nr_clk_ids = DISP_NR_CLK,
+ .clk_regs = disp_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
+};
+
+static void __init exynos5433_cmu_disp_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &disp_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
+ exynos5433_cmu_disp_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 3fb1f32..9372b77 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -68,6 +68,7 @@
#define CLK_MOUT_SCLK_SPDIF 61
#define CLK_MOUT_SCLK_AUDIO1 62
#define CLK_MOUT_SCLK_AUDIO0 63
+#define CLK_MOUT_SCLK_HDMI_SPDIF 64
#define CLK_DIV_ACLK_FSYS_200 100
#define CLK_DIV_ACLK_IMEM_SSSX 101
@@ -337,8 +338,9 @@
#define CLK_SCLK_BUS_PLL 198
#define CLK_SCLK_BUS_PLL_APOLLO 199
#define CLK_SCLK_BUS_PLL_ATLAS 200
+#define CLK_SCLK_HDMI_SPDIF_DISP 201
-#define MIF_NR_CLK 201
+#define MIF_NR_CLK 202
/* CMU_PERIC */
#define CLK_PCLK_SPI2 1
@@ -514,4 +516,114 @@
#define G2D_NR_CLK 27
+/* CMU_DISP */
+#define CLK_FOUT_DISP_PLL 1
+
+#define CLK_MOUT_DISP_PLL 2
+#define CLK_MOUT_SCLK_DSIM1_USER 3
+#define CLK_MOUT_SCLK_DSIM0_USER 4
+#define CLK_MOUT_SCLK_DSD_USER 5
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6
+#define CLK_MOUT_SCLK_DECON_VCLK_USER 7
+#define CLK_MOUT_SCLK_DECON_ECLK_USER 8
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9
+#define CLK_MOUT_ACLK_DISP_333_USER 10
+#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11
+#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12
+#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13
+#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14
+#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15
+#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16
+#define CLK_MOUT_SCLK_DSIM0 17
+#define CLK_MOUT_SCLK_DECON_TV_ECLK 18
+#define CLK_MOUT_SCLK_DECON_VCLK 19
+#define CLK_MOUT_SCLK_DECON_ECLK 20
+#define CLK_MOUT_SCLK_DSIM1_B_DISP 21
+#define CLK_MOUT_SCLK_DSIM1_A_DISP 22
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
+
+#define CLK_DIV_SCLK_DSIM1_DISP 30
+#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31
+#define CLK_DIV_SCLK_DSIM0_DISP 32
+#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33
+#define CLK_DIV_SCLK_DECON_VCLK_DISP 34
+#define CLK_DIV_SCLK_DECON_ECLK_DISP 35
+#define CLK_DIV_PCLK_DISP 36
+
+#define CLK_ACLK_DECON_TV 40
+#define CLK_ACLK_DECON 41
+#define CLK_ACLK_SMMU_TV1X 42
+#define CLK_ACLK_SMMU_TV0X 43
+#define CLK_ACLK_SMMU_DECON1X 44
+#define CLK_ACLK_SMMU_DECON0X 45
+#define CLK_ACLK_BTS_DECON_TV_M3 46
+#define CLK_ACLK_BTS_DECON_TV_M2 47
+#define CLK_ACLK_BTS_DECON_TV_M1 48
+#define CLK_ACLK_BTS_DECON_TV_M0 49
+#define CLK_ACLK_BTS_DECON_NM4 50
+#define CLK_ACLK_BTS_DECON_NM3 51
+#define CLK_ACLK_BTS_DECON_NM2 52
+#define CLK_ACLK_BTS_DECON_NM1 53
+#define CLK_ACLK_BTS_DECON_NM0 54
+#define CLK_ACLK_AHB2APB_DISPSFR2P 55
+#define CLK_ACLK_AHB2APB_DISPSFR1P 56
+#define CLK_ACLK_AHB2APB_DISPSFR0P 57
+#define CLK_ACLK_AHB_DISPH 58
+#define CLK_ACLK_XIU_TV1X 59
+#define CLK_ACLK_XIU_TV0X 60
+#define CLK_ACLK_XIU_DECON1X 61
+#define CLK_ACLK_XIU_DECON0X 62
+#define CLK_ACLK_XIU_DISP1X 63
+#define CLK_ACLK_XIU_DISPNP_100 64
+#define CLK_ACLK_DISP1ND_333 65
+#define CLK_ACLK_DISP0ND_333 66
+#define CLK_PCLK_SMMU_TV1X 67
+#define CLK_PCLK_SMMU_TV0X 68
+#define CLK_PCLK_SMMU_DECON1X 69
+#define CLK_PCLK_SMMU_DECON0X 70
+#define CLK_PCLK_BTS_DECON_TV_M3 71
+#define CLK_PCLK_BTS_DECON_TV_M2 72
+#define CLK_PCLK_BTS_DECON_TV_M1 73
+#define CLK_PCLK_BTS_DECON_TV_M0 74
+#define CLK_PCLK_BTS_DECONM4 75
+#define CLK_PCLK_BTS_DECONM3 76
+#define CLK_PCLK_BTS_DECONM2 77
+#define CLK_PCLK_BTS_DECONM1 78
+#define CLK_PCLK_BTS_DECONM0 79
+#define CLK_PCLK_MIC1 80
+#define CLK_PCLK_PMU_DISP 81
+#define CLK_PCLK_SYSREG_DISP 82
+#define CLK_PCLK_HDMIPHY 83
+#define CLK_PCLK_HDMI 84
+#define CLK_PCLK_MIC0 85
+#define CLK_PCLK_DSIM1 86
+#define CLK_PCLK_DSIM0 87
+#define CLK_PCLK_DECON_TV 88
+#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89
+#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90
+#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91
+#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92
+#define CLK_SCLK_DSIM1 93
+#define CLK_SCLK_DECON_TV_VCLK 94
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97
+#define CLK_PHYCLK_HDMI_PIXEL 98
+#define CLK_SCLK_RGB_VCLK_TO_SMIES 99
+#define CLK_SCLK_FREQ_DET_DISP_PLL 100
+#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101
+#define CLK_SCLK_RGB_VCLK_TO_MIC0 102
+#define CLK_SCLK_DSD 103
+#define CLK_SCLK_HDMI_SPDIF 104
+#define CLK_SCLK_DSIM0 105
+#define CLK_SCLK_DECON_TV_ECLK 106
+#define CLK_SCLK_DECON_VCLK 107
+#define CLK_SCLK_DECON_ECLK 108
+#define CLK_SCLK_RGB_VCLK 109
+#define CLK_SCLK_RGB_TV_VCLK 110
+
+#define DISP_NR_CLK 111
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
2014-12-02 8:49 ` [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain Chanwoo Choi
@ 2014-12-09 6:06 ` Pankaj Dubey
0 siblings, 0 replies; 44+ messages in thread
From: Pankaj Dubey @ 2014-12-09 6:06 UTC (permalink / raw)
To: Chanwoo Choi, linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, a.kesavan, devicetree, linux-arm-kernel
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
> includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
> is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
> related to CMU_DISP should be always on state.
>
> Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
> from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Inki Dae <inki.dae@samsung.com>
> Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
> ---
> .../devicetree/bindings/clock/exynos5433-clock.txt | 9 +
> drivers/clk/samsung/clk-exynos5433.c | 465 ++++++++++++++++++++-
> include/dt-bindings/clock/exynos5433.h | 114 ++++-
> 3 files changed, 577 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> index 27dd77b..8d3dad4 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> @@ -21,6 +21,8 @@ Required Properties:
> which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
> - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
> which generates clocks for G2D/MDMA IPs.
> + - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
> + which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
>
> - reg: physical base address of the controller and length of memory mapped
> region.
> @@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed below.
> #clock-cells = <1>;
> };
>
> + cmu_disp: clock-controller@0x13b90000 {
> + compatible = "samsung,exynos5433-cmu-disp";
> + reg = <0x13b90000 0x0c04>;
> + #clock-cells = <1>;
> + };
> +
> +
> Example 2: UART controller node that consumes the clock generated by the clock
> controller.
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index 10197a1..ec23e97 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "fin_pll",
> PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "fin_pll",
> "mout_aud_pll_user_t",};
>
> +PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
> +
> static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
> FFACTOR(0, "sclk_bus_pll", "fout_bus_pll", 1, 1, 0),
> FFACTOR(0, "sclk_mfc_pll", "fout_mfc_pll", 1, 1, 0),
> @@ -397,6 +399,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
> MUX_SEL_TOP_PERIC1, 4, 2),
> MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
> MUX_SEL_TOP_PERIC1, 0, 2),
> +
> + /* MUX_SEL_TOP_DISP */
> + MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
> + mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
> };
>
> static struct samsung_div_clock top_div_clks[] __initdata = {
> @@ -1256,9 +1262,9 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
>
> /* ENABLE_ACLK_MIF3 */
> GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
> - ENABLE_ACLK_MIF3, 4, 0, 0),
> + ENABLE_ACLK_MIF3, 4, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
> - ENABLE_ACLK_MIF3, 1, 0, 0),
> + ENABLE_ACLK_MIF3, 1, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
> ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
>
> @@ -1333,21 +1339,30 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
>
> /* ENABLE_SCLK_MIF */
> GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
> - ENABLE_SCLK_MIF, 15, 0, 0),
> + ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
> - "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 14, 0, 0),
> + "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
> + 14, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
> - ENABLE_SCLK_MIF, 9, 0, 0),
> + ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
> - ENABLE_SCLK_MIF, 8, 0, 0),
> + ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
> - "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 7, 0, 0),
> + "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
> + 7, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
> - "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 6, 0, 0),
> + "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
> + 6, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
> - "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 5, 0, 0),
> + "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
> + 5, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
> - ENABLE_SCLK_MIF, 4, 0, 0),
> + ENABLE_SCLK_MIF, 4, CLK_IGNORE_UNUSED, 0),
> +
> + /* ENABLE_SCLK_TOP_DISP */
> + GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
> + "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
> + CLK_IGNORE_UNUSED, 0),
> };
>
> static struct samsung_cmu_info mif_cmu_info __initdata = {
> @@ -2009,3 +2024,433 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np)
>
> CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
> exynos5433_cmu_g2d_init);
> +
> +/*
> + * Register offset definitions for CMU_DISP
> + */
> +#define DISP_PLL_LOCK 0x0000
> +#define DISP_PLL_CON0 0x0100
> +#define DISP_PLL_CON1 0x0104
> +#define DISP_PLL_FREQ_DET 0x0108
> +#define MUX_SEL_DISP0 0x0200
> +#define MUX_SEL_DISP1 0x0204
> +#define MUX_SEL_DISP2 0x0208
> +#define MUX_SEL_DISP3 0x020c
> +#define MUX_SEL_DISP4 0x0210
> +#define MUX_ENABLE_DISP0 0x0300
> +#define MUX_ENABLE_DISP1 0x0304
> +#define MUX_ENABLE_DISP2 0x0308
> +#define MUX_ENABLE_DISP3 0x030c
> +#define MUX_ENABLE_DISP4 0x0310
> +#define MUX_STAT_DISP0 0x0400
> +#define MUX_STAT_DISP1 0x0404
> +#define MUX_STAT_DISP2 0x0408
> +#define MUX_STAT_DISP3 0x040c
> +#define MUX_STAT_DISP4 0x0410
> +#define MUX_IGNORE_DISP2 0x0508
> +#define DIV_DISP 0x0600
> +#define DIV_DISP_PLL_FREQ_DET 0x0604
> +#define DIV_STAT_DISP 0x0700
> +#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
> +#define ENABLE_ACLK_DISP0 0x0800
> +#define ENABLE_ACLK_DISP1 0x0804
> +#define ENABLE_PCLK_DISP 0x0900
> +#define ENABLE_SCLK_DISP 0x0a00
> +#define ENABLE_IP_DISP0 0x0b00
> +#define ENABLE_IP_DISP1 0x0b04
> +#define CLKOUT_CMU_DISP 0x0c00
> +#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
> +
> +static unsigned long disp_clk_regs[] __initdata = {
> + DISP_PLL_LOCK,
> + DISP_PLL_CON0,
> + DISP_PLL_CON1,
> + DISP_PLL_FREQ_DET,
> + MUX_SEL_DISP0,
> + MUX_SEL_DISP1,
> + MUX_SEL_DISP2,
> + MUX_SEL_DISP3,
> + MUX_SEL_DISP4,
> + MUX_ENABLE_DISP0,
> + MUX_ENABLE_DISP1,
> + MUX_ENABLE_DISP2,
> + MUX_ENABLE_DISP3,
> + MUX_ENABLE_DISP4,
> + MUX_STAT_DISP0,
> + MUX_STAT_DISP1,
> + MUX_STAT_DISP2,
> + MUX_STAT_DISP3,
> + MUX_STAT_DISP4,
> + MUX_IGNORE_DISP2,
> + DIV_DISP,
> + DIV_DISP_PLL_FREQ_DET,
> + DIV_STAT_DISP,
> + DIV_STAT_DISP_PLL_FREQ_DET,
> + ENABLE_ACLK_DISP0,
> + ENABLE_ACLK_DISP1,
> + ENABLE_PCLK_DISP,
> + ENABLE_SCLK_DISP,
> + ENABLE_IP_DISP0,
> + ENABLE_IP_DISP1,
> + CLKOUT_CMU_DISP,
> + CLKOUT_CMU_DISP_DIV_STAT,
> +};
> +
> +/* list of all parent clock list */
> +PNAME(mout_disp_pll_p) = { "fin_pll", "fout_disp_pll", };
> +PNAME(mout_sclk_dsim1_user_p) = { "fin_pll", "sclk_dsim1_disp", };
> +PNAME(mout_sclk_dsim0_user_p) = { "fin_pll", "sclk_dsim0_disp", };
> +PNAME(mout_sclk_dsd_user_p) = { "fin_pll", "sclk_dsd_disp", };
> +PNAME(mout_sclk_decon_tv_eclk_user_p) = { "fin_pll",
> + "sclk_decon_tv_eclk_disp", };
> +PNAME(mout_sclk_decon_vclk_user_p) = { "fin_pll",
> + "sclk_decon_vclk_disp", };
> +PNAME(mout_sclk_decon_eclk_user_p) = { "fin_pll",
> + "sclk_decon_eclk_disp", };
> +PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "fin_pll",
> + "sclk_decon_tv_vclk_disp", };
> +PNAME(mout_aclk_disp_333_user_p) = { "fin_pll", "aclk_disp_333", };
> +
> +PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "fin_pll",
> + "phyclk_mipidphy1_bitclkdiv8_phy", };
> +PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "fin_pll",
> + "phyclk_mipidphy1_rxclkesc0_phy", };
> +PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "fin_pll",
> + "phyclk_mipidphy0_bitclkdiv8_phy", };
> +PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "fin_pll",
> + "phyclk_mipidphy0_rxclkesc0_phy", };
> +PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "fin_pll",
> + "phyclk_hdmiphy_tmds_clko_phy", };
> +PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "fin_pll",
> + "phyclk_hdmiphy_pixel_clko_phy", };
> +
> +PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
> + "mout_sclk_dsim0_user", };
> +PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
> + "mout_sclk_decon_tv_eclk_user", };
> +PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
> + "mout_sclk_decon_vclk_user", };
> +PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
> + "mout_sclk_decon_eclk_user", };
> +
> +PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
> + "mout_sclk_dsim1_user", };
> +PNAME(mout_sclk_dsim1_a_disp_p) = { "mout_disp_pll",
> + "mout_sclk_dsim0_user", };
mout_sclk_dsim1_a_disp_p and mout_sclk_dsim0_p has same parent list, so
one can be dropped.
> +PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
> + "mout_phyclk_hdmiphy_pixel_clko_user",
> + "mout_sclk_decon_tv_vclk_b_disp", };
> +PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
> + "mout_sclk_decon_tv_vclk_user", };
> +PNAME(mout_sclk_decon_tv_vclk_a_disp_p) = { "mout_disp_pll",
> + "mout_sclk_decon_vclk_user", };
> +
mout_sclk_decon_tv_vclk_a_disp_p and mout_sclk_decon_vclk_p has same
parent list, so one of them can be dropped.
> +static struct samsung_pll_clock disp_pll_clks[] __initdata = {
> + PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
> + DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
> +};
> +
> +static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
> + /*
> + * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
> + * The divider has fixed value (2) betwwen sclk_rgb_{vclk|tv_vclk}
typo: %s/betwwen/between
> + * and sclk_decon_{vclk|tv_vclk}.
> + */
> + FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
> + 1, 2, 0),
> + FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
> + 1, 2, 0),
> +};
> +
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (5 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
[not found] ` <1417510196-6714-9-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-12-02 8:49 ` [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains Chanwoo Choi
` (10 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 7 +
drivers/clk/samsung/clk-exynos5433.c | 173 +++++++++++++++++++++
include/dt-bindings/clock/exynos5433.h | 53 +++++++
3 files changed, 233 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 8d3dad4..9a6ae75 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -23,6 +23,8 @@ Required Properties:
which generates clocks for G2D/MDMA IPs.
- "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
+ - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
+ which generates clocks for Cortex-A5/BUS/AUDIO clocks.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -86,6 +88,11 @@ Example 1: Examples of clock controller nodes are listed below.
#clock-cells = <1>;
};
+ cmu_aud: clock-controller@0x114c0000 {
+ compatible = "samsung,exynos5433-cmu-aud";
+ reg = <0x114c0000 0x0b04>;
+ #clock-cells = <1>;
+ };
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index ec23e97..99262e0 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2454,3 +2454,176 @@ static void __init exynos5433_cmu_disp_init(struct device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
exynos5433_cmu_disp_init);
+
+/*
+ * Register offset definitions for CMU_AUD
+ */
+#define MUX_SEL_AUD0 0x0200
+#define MUX_SEL_AUD1 0x0204
+#define MUX_ENABLE_AUD0 0x0300
+#define MUX_ENABLE_AUD1 0x0304
+#define MUX_STAT_AUD0 0x0400
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define DIV_STAT_AUD0 0x0700
+#define DIV_STAT_AUD1 0x0704
+#define ENABLE_ACLK_AUD 0x0800
+#define ENABLE_PCLK_AUD 0x0900
+#define ENABLE_SCLK_AUD0 0x0a00
+#define ENABLE_SCLK_AUD1 0x0a04
+#define ENABLE_IP_AUD0 0x0b00
+#define ENABLE_IP_AUD1 0x0b04
+
+static unsigned long aud_clk_regs[] __initdata = {
+ MUX_SEL_AUD0,
+ MUX_SEL_AUD1,
+ MUX_ENABLE_AUD0,
+ MUX_ENABLE_AUD1,
+ MUX_STAT_AUD0,
+ DIV_AUD0,
+ DIV_AUD1,
+ DIV_STAT_AUD0,
+ DIV_STAT_AUD1,
+ ENABLE_ACLK_AUD,
+ ENABLE_PCLK_AUD,
+ ENABLE_SCLK_AUD0,
+ ENABLE_SCLK_AUD1,
+ ENABLE_IP_AUD0,
+ ENABLE_IP_AUD1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_user_aud_p) = { "fin_pll", "fout_aud_pll", };
+PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
+PNAME(mout_sclk_aud_i2s_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
+
+static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
+ FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 188000000),
+ FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 188000000),
+ FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 188000000),
+};
+
+static struct samsung_mux_clock aud_mux_clks[] __initdata = {
+ /* MUX_SEL_AUD0 */
+ MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
+ mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
+
+ /* MUX_SEL_AUD1 */
+ MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
+ MUX_SEL_AUD1, 8, 1),
+ MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
+ MUX_SEL_AUD1, 0, 1),
+};
+
+static struct samsung_div_clock aud_div_clks[] __initdata = {
+ /* DIV_AUD0 */
+ DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
+ 12, 4),
+ DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
+ 8, 4),
+ DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
+ 4, 4),
+ DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
+ 0, 4),
+
+ /* DIV_AUD1 */
+ DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
+ "mout_aud_pll_user", DIV_AUD1, 16, 5),
+ DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
+ DIV_AUD1, 12, 4),
+ DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
+ DIV_AUD1, 4, 8),
+ DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
+ DIV_AUD1, 0, 4),
+};
+
+static struct samsung_gate_clock aud_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_AUD */
+ GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 12, 0, 0),
+ GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 7, 0, 0),
+ GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 0, 4, 0),
+ GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 0, 3, 0),
+ GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 0, 2, 0),
+ GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
+ 0, 1, 0),
+ GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
+ 0, 0, 0),
+
+ /* ENABLE_PCLK_AUD */
+ GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
+ 13, 0, 0),
+ GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
+ 12, 0, 0),
+ GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
+ 11, 0, 0),
+ GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 10, 0, 0),
+ GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 6, 0, 0),
+ GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 5, 0, 0),
+ GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 4, 0, 0),
+ GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 3, 0, 0),
+ GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
+ 2, 0, 0),
+ GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 0, 0, 0),
+
+ /* ENABLE_SCLK_AUD0 */
+ GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
+ 2, 0, 0),
+ GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
+ ENABLE_SCLK_AUD0, 1, 0, 0),
+ GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
+ 0, 0, 0),
+
+ /* ENABLE_SCLK_AUD1 */
+ GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
+ ENABLE_SCLK_AUD1, 6, 0, 0),
+ GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
+ ENABLE_SCLK_AUD1, 5, 0, 0),
+ GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
+ ENABLE_SCLK_AUD1, 4, 0, 0),
+ GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
+ ENABLE_SCLK_AUD1, 3, 0, 0),
+ GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
+ ENABLE_SCLK_AUD1, 2, 0, 0),
+ GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
+ ENABLE_SCLK_AUD1, 1, 0, 0),
+ GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
+ ENABLE_SCLK_AUD1, 0, 0, 0),
+};
+
+static struct samsung_cmu_info aud_cmu_info __initdata = {
+ .mux_clks = aud_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
+ .div_clks = aud_div_clks,
+ .nr_div_clks = ARRAY_SIZE(aud_div_clks),
+ .gate_clks = aud_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
+ .fixed_clks = aud_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
+ .nr_clk_ids = AUD_NR_CLK,
+ .clk_regs = aud_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
+};
+
+static void __init exynos5433_cmu_aud_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &aud_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
+ exynos5433_cmu_aud_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 9372b77..52a4024 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -626,4 +626,57 @@
#define DISP_NR_CLK 111
+/* CMU_AUD */
+#define CLK_MOUT_AUD_PLL_USER 1
+#define CLK_MOUT_SCLK_AUD_PCM 2
+#define CLK_MOUT_SCLK_AUD_I2S 3
+
+#define CLK_DIV_ATCLK_AUD 4
+#define CLK_DIV_PCLK_DBG_AUD 5
+#define CLK_DIV_ACLK_AUD 6
+#define CLK_DIV_AUD_CA5 7
+#define CLK_DIV_SCLK_AUD_SLIMBUS 8
+#define CLK_DIV_SCLK_AUD_UART 9
+#define CLK_DIV_SCLK_AUD_PCM 10
+#define CLK_DIV_SCLK_AUD_I2S 11
+
+#define CLK_ACLK_INTR_CTRL 12
+#define CLK_ACLK_AXIDS2_LPASSP 13
+#define CLK_ACLK_AXIDS1_LPASSP 14
+#define CLK_ACLK_AXI2APB1_LPASSP 15
+#define CLK_ACLK_AXI2APH_LPASSP 16
+#define CLK_ACLK_SMMU_LPASSX 17
+#define CLK_ACLK_AXIDS0_LPASSP 18
+#define CLK_ACLK_AXI2APB0_LPASSP 19
+#define CLK_ACLK_XIU_LPASSX 20
+#define CLK_ACLK_AUDNP_133 21
+#define CLK_ACLK_AUDND_133 22
+#define CLK_ACLK_SRAMC 23
+#define CLK_ACLK_DMAC 24
+#define CLK_PCLK_WDT1 25
+#define CLK_PCLK_WDT0 26
+#define CLK_PCLK_SFR1 27
+#define CLK_PCLK_SMMU_LPASSX 28
+#define CLK_PCLK_GPIO_AUD 29
+#define CLK_PCLK_PMU_AUD 30
+#define CLK_PCLK_SYSREG_AUD 31
+#define CLK_PCLK_AUD_SLIMBUS 32
+#define CLK_PCLK_AUD_UART 33
+#define CLK_PCLK_AUD_PCM 34
+#define CLK_PCLK_AUD_I2S 35
+#define CLK_PCLK_TIMER 36
+#define CLK_PCLK_SFR0_CTRL 37
+#define CLK_ATCLK_AUD 38
+#define CLK_PCLK_DBG_AUD 39
+#define CLK_SCLK_AUD_CA5 40
+#define CLK_SCLK_JTAG_TCK 41
+#define CLK_SCLK_SLIMBUS_CLKIN 42
+#define CLK_SCLK_AUD_SLIMBUS 43
+#define CLK_SCLK_AUD_UART 44
+#define CLK_SCLK_AUD_PCM 45
+#define CLK_SCLK_I2S_BCLK 46
+#define CLK_SCLK_AUD_I2S 47
+
+#define AUD_NR_CLK 48
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (6 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-09 6:05 ` Pankaj Dubey
2014-12-02 8:49 ` [PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain Chanwoo Choi
` (9 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for regiser accesses.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 21 +++
drivers/clk/samsung/clk-exynos5433.c | 185 ++++++++++++++++++++-
include/dt-bindings/clock/exynos5433.h | 29 +++-
3 files changed, 232 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 9a6ae75..03ae40a 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -25,6 +25,9 @@ Required Properties:
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
which generates clocks for Cortex-A5/BUS/AUDIO clocks.
+ - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
+ and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
+ which generates global data buses clock and global peripheral buses clock.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed below.
#clock-cells = <1>;
};
+ cmu_bus0: clock-controller@0x13600000 {
+ compatible = "samsung,exynos5433-cmu-bus0";
+ reg = <0x13600000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus1: clock-controller@0x14800000 {
+ compatible = "samsung,exynos5433-cmu-bus1";
+ reg = <0x14800000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus2: clock-controller@0x13400000 {
+ compatible = "samsung,exynos5433-cmu-bus2";
+ reg = <0x13400000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 99262e0..5b4ec83 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -425,7 +425,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
DIV_TOP2, 0, 3),
/* DIV_TOP3 */
- DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx",
+ DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
"mout_bus_pll_user", DIV_TOP3, 24, 3),
DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
"mout_bus_pll_user", DIV_TOP3, 20, 3),
@@ -440,6 +440,14 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
"mout_bus_pll_user", DIV_TOP3, 0, 3),
+ /* DIV_TOP4 */
+ DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
+ DIV_TOP4, 8, 3),
+ DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
+ DIV_TOP4, 4, 3),
+ DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
+ DIV_TOP4, 0, 3),
+
/* DIV_TOP_FSYS0 */
DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
DIV_TOP_FSYS0, 16, 8),
@@ -503,6 +511,19 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
static struct samsung_gate_clock top_gate_clks[] __initdata = {
/* ENABLE_ACLK_TOP */
+ GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
+ ENABLE_ACLK_TOP, 30, 0, 0),
+ GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
+ "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
+ 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
+ ENABLE_ACLK_TOP, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
+ ENABLE_ACLK_TOP, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
+ ENABLE_ACLK_TOP, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
+ ENABLE_ACLK_TOP, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
ENABLE_ACLK_TOP, 22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
@@ -2627,3 +2648,165 @@ static void __init exynos5433_cmu_aud_init(struct device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
exynos5433_cmu_aud_init);
+
+
+/*
+ * Register offset definitions for CMU_BUS{0|1|2}
+ */
+#define DIV_BUS 0x0600
+#define DIV_STAT_BUS 0x0700
+#define ENABLE_ACLK_BUS 0x0800
+#define ENABLE_PCLK_BUS 0x0900
+#define ENABLE_IP_BUS0 0x0b00
+#define ENABLE_IP_BUS1 0x0b04
+
+#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
+#define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
+#define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
+
+/* list of all parent clock list */
+PNAME(mout_aclk_bus2_400_p) = { "fin_pll", "aclk_bus2_400", };
+
+#define CMU_BUS_COMMON_CLK_REGS \
+ DIV_BUS, \
+ DIV_STAT_BUS, \
+ ENABLE_ACLK_BUS, \
+ ENABLE_PCLK_BUS, \
+ ENABLE_IP_BUS0, \
+ ENABLE_IP_BUS1
+
+static unsigned long bus01_clk_regs[] __initdata = {
+ CMU_BUS_COMMON_CLK_REGS,
+};
+
+static unsigned long bus2_clk_regs[] __initdata = {
+ MUX_SEL_BUS2,
+ MUX_ENABLE_BUS2,
+ MUX_STAT_BUS2,
+ CMU_BUS_COMMON_CLK_REGS,
+};
+
+static struct samsung_div_clock bus0_div_clks[] __initdata = {
+ /* DIV_BUS0 */
+ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
+ DIV_BUS, 0, 3),
+};
+
+/* CMU_BUS0 clocks */
+static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_BUS0 */
+ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
+ ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
+ ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
+ ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS0 */
+ GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+/* CMU_BUS1 clocks */
+static struct samsung_div_clock bus1_div_clks[] __initdata = {
+ /* DIV_BUS1 */
+ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
+ DIV_BUS, 0, 3),
+};
+
+static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_BUS1 */
+ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
+ ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
+ ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
+ ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS1 */
+ GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+/* CMU_BUS2 clocks */
+static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
+ /* MUX_SEL_BUS2 */
+ MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
+ mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
+};
+
+static struct samsung_div_clock bus2_div_clks[] __initdata = {
+ /* DIV_BUS2 */
+ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
+ "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
+};
+
+static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_BUS2 */
+ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
+ ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
+ ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
+ "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
+ "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS2 */
+ GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+#define CMU_BUS_INFO_CLKS(id) \
+ .div_clks = bus##id##_div_clks, \
+ .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
+ .gate_clks = bus##id##_gate_clks, \
+ .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
+ .nr_clk_ids = BUSx_NR_CLK
+
+static struct samsung_cmu_info bus0_cmu_info __initdata = {
+ CMU_BUS_INFO_CLKS(0),
+ .clk_regs = bus01_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
+};
+
+static struct samsung_cmu_info bus1_cmu_info __initdata = {
+ CMU_BUS_INFO_CLKS(1),
+ .clk_regs = bus01_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
+};
+
+static struct samsung_cmu_info bus2_cmu_info __initdata = {
+ CMU_BUS_INFO_CLKS(2),
+ .mux_clks = bus2_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
+ .clk_regs = bus2_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
+};
+
+#define exynos5433_cmu_bus_init(id) \
+static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
+{ \
+ samsung_cmu_register_one(np, &bus##id##_cmu_info); \
+} \
+CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
+ "samsung,exynos5433-cmu-bus"#id, \
+ exynos5433_cmu_bus##id##_init)
+
+exynos5433_cmu_bus_init(0);
+exynos5433_cmu_bus_init(1);
+exynos5433_cmu_bus_init(2);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 52a4024..8c44674 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -71,7 +71,7 @@
#define CLK_MOUT_SCLK_HDMI_SPDIF 64
#define CLK_DIV_ACLK_FSYS_200 100
-#define CLK_DIV_ACLK_IMEM_SSSX 101
+#define CLK_DIV_ACLK_IMEM_SSSX_266 101
#define CLK_DIV_ACLK_IMEM_200 102
#define CLK_DIV_ACLK_IMEM_266 103
#define CLK_DIV_ACLK_PERIC_66_B 104
@@ -107,6 +107,9 @@
#define CLK_DIV_ACLK_MFC_400 134
#define CLK_DIV_ACLK_G2D_266 135
#define CLK_DIV_ACLK_G2D_400 136
+#define CLK_DIV_ACLK_G3D_400 137
+#define CLK_DIV_ACLK_BUS0_400 138
+#define CLK_DIV_ACLK_BUS1_400 139
#define CLK_ACLK_PERIC_66 200
#define CLK_ACLK_PERIS_66 201
@@ -130,8 +133,14 @@
#define CLK_SCLK_AUDIO0 219
#define CLK_ACLK_G2D_266 220
#define CLK_ACLK_G2D_400 221
+#define CLK_ACLK_G3D_400 222
+#define CLK_ACLK_IMEM_SSX_266 223
+#define CLK_ACLK_BUS0_400 224
+#define CLK_ACLK_BUS1_400 225
+#define CLK_ACLK_IMEM_200 226
+#define CLK_ACLK_IMEM_266 227
-#define TOP_NR_CLK 222
+#define TOP_NR_CLK 228
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -679,4 +688,20 @@
#define AUD_NR_CLK 48
+/* CMU_BUS{0|1|2} */
+#define CLK_DIV_PCLK_BUS_133 1
+
+#define CLK_ACLK_AHB2APB_BUSP 2
+#define CLK_ACLK_BUSNP_133 3
+#define CLK_ACLK_BUSND_400 4
+#define CLK_PCLK_BUSSRVND_133 5
+#define CLK_PCLK_PMU_BUS 6
+#define CLK_PCLK_SYSREG_BUS 7
+
+#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */
+#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
+#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
+
+#define BUSx_NR_CLK 11
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
2014-12-02 8:49 ` [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains Chanwoo Choi
@ 2014-12-09 6:05 ` Pankaj Dubey
0 siblings, 0 replies; 44+ messages in thread
From: Pankaj Dubey @ 2014-12-09 6:05 UTC (permalink / raw)
To: Chanwoo Choi, linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, a.kesavan, devicetree, linux-arm-kernel
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
> which contain global data buses clocked at up the 400MHz. These blocks
> transfer data between DRAM and various sub-blocks. These clock domains
> also contain global peripheral buses clocked at 67/111/200/222/266/333/400
> MHz and used for regiser accesses.
typo: %s/regiser/register
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Inki Dae <inki.dae@samsung.com>
> Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
> ---
> .../devicetree/bindings/clock/exynos5433-clock.txt | 21 +++
> drivers/clk/samsung/clk-exynos5433.c | 185 ++++++++++++++++++++-
> include/dt-bindings/clock/exynos5433.h | 29 +++-
> 3 files changed, 232 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> index 9a6ae75..03ae40a 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> @@ -25,6 +25,9 @@ Required Properties:
> which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
> - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
> which generates clocks for Cortex-A5/BUS/AUDIO clocks.
> + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
> + and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
> + which generates global data buses clock and global peripheral buses clock.
>
> - reg: physical base address of the controller and length of memory mapped
> region.
> @@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed below.
> #clock-cells = <1>;
> };
>
> + cmu_bus0: clock-controller@0x13600000 {
> + compatible = "samsung,exynos5433-cmu-bus0";
> + reg = <0x13600000 0x0b04>;
> + #clock-cells = <1>;
> + };
> +
> + cmu_bus1: clock-controller@0x14800000 {
> + compatible = "samsung,exynos5433-cmu-bus1";
> + reg = <0x14800000 0x0b04>;
> + #clock-cells = <1>;
> + };
> +
> + cmu_bus2: clock-controller@0x13400000 {
> + compatible = "samsung,exynos5433-cmu-bus2";
> + reg = <0x13400000 0x0b04>;
> + #clock-cells = <1>;
> + };
> +
> Example 2: UART controller node that consumes the clock generated by the clock
> controller.
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index 99262e0..5b4ec83 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -425,7 +425,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
> DIV_TOP2, 0, 3),
>
> /* DIV_TOP3 */
> - DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx",
> + DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
This change can be moved to patch 1/19 itself.
> "mout_bus_pll_user", DIV_TOP3, 24, 3),
> DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
> "mout_bus_pll_user", DIV_TOP3, 20, 3),
> @@ -440,6 +440,14 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
> DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
> "mout_bus_pll_user", DIV_TOP3, 0, 3),
>
> + /* DIV_TOP4 */
> + DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
> + DIV_TOP4, 8, 3),
> + DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
> + DIV_TOP4, 4, 3),
> + DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
> + DIV_TOP4, 0, 3),
> +
With these changes you can have:
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (7 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-09 6:03 ` Pankaj Dubey
2014-12-02 8:49 ` [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain Chanwoo Choi
` (8 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: mark.rutland, jh80.chung, geunsik.lim, kgene.kim, arnd, cw00.choi,
marc.zyngier, catalin.marinas, will.deacon, tomasz.figa,
a.kesavan, inki.dae, sw0312.kim, kyungmin.park, linux-arm-kernel,
s.nawrocki, pankaj.dubey, olof, chanho61.park, devicetree
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
drivers/clk/samsung/clk-exynos5433.c | 286 +++++++++++++++++++++++++++++++++
include/dt-bindings/clock/exynos5433.h | 82 +++++++++-
2 files changed, 365 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 5b4ec83..e2b7ea6 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -464,6 +464,16 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
DIV_TOP_FSYS1, 0, 4),
+ /* DIV_TOP_FSYS2 */
+ DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
+ DIV_TOP_FSYS2, 12, 3),
+ DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
+ "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
+ DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
+ "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
+ DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
+ DIV_TOP_FSYS2, 0, 4),
+
/* DIV_TOP_PERIC0 */
DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
DIV_TOP_PERIC0, 16, 8),
@@ -536,12 +546,20 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
+ GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
+ ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
+ GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
+ "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
+ "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
+ "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
/* ENABLE_SCLK_TOP_PERIC */
GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
@@ -1819,10 +1837,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
#define ENABLE_IP_FSYS1 0x0b04
/* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p) = { "fin_pll", "sclk_ufs_mphy", };
PNAME(mout_aclk_fsys_200_user_p) = { "fin_pll", "aclk_fsys_200", };
+PNAME(mout_sclk_pcie_100_user_p) = { "fin_pll", "sclk_ufsunipro_fsys",};
+PNAME(mout_sclk_ufsunipro_user_p) = { "fin_pll", "sclk_ufsunipro_fsys",};
PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2_fsys", };
PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1_fsys", };
PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0_fsys", };
+PNAME(mout_sclk_usbhost30_user_p) = { "fin_pll", "sclk_usbhost30_fsys",};
+PNAME(mout_sclk_usbdrd30_user_p) = { "fin_pll", "sclk_usbdrd30_fsys", };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+ = { "fin_pll", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+ = { "fin_pll", "phyclk_usbhost30_uhost30_phyclock_phy", };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+ = { "fin_pll", "phyclk_usbhost20_phy_hsic1_phy", };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+ = { "fin_pll", "phyclk_usbhost20_phy_clk48mohci_phy", };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+ = { "fin_pll", "phyclk_usbhost20_phy_phyclock_phy", };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+ = { "fin_pll", "phyclk_usbhost20_phy_freeclk_phy", };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+ = { "fin_pll", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+ = { "fin_pll", "phyclk_usbhost30_uhost30_phyclock_phy", };
+PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
+ = { "fin_pll", "phyclk_ufs_rx1_symbol_phy", };
+PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
+ = { "fin_pll", "phyclk_ufs_rx0_symbol_phy", };
+PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
+ = { "fin_pll", "phyclk_ufs_tx1_symbol_phy", };
+PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
+ = { "fin_pll", "phyclk_ufs_tx0_symbol_phy", };
+PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
+ = { "fin_pll", "phyclk_lli_mphy_to_ufs_phy", };
+PNAME(mout_sclk_mphy_p)
+ = { "mout_sclk_ufs_mphy_user",
+ "mout_phyclk_lli_mphy_to_ufs_user", };
static unsigned long fsys_clk_regs[] __initdata = {
MUX_SEL_FSYS0,
@@ -1850,18 +1903,117 @@ static unsigned long fsys_clk_regs[] __initdata = {
ENABLE_IP_FSYS1,
};
+static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
+ /* PHY clocks from USBDRD30_PHY */
+ FRATE(0, "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, CLK_IS_ROOT,
+ 60000000),
+ FRATE(0, "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, CLK_IS_ROOT,
+ 125000000),
+ /* PHY clocks from USBHOST30_PHY */
+ FRATE(0, "phyclk_usbhost30_uhost30_phyclock_phy", NULL, CLK_IS_ROOT,
+ 60000000),
+ FRATE(0, "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, CLK_IS_ROOT,
+ 125000000),
+ /* PHY clocks from USBHOST20_PHY */
+ FRATE(0, "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
+ 60000000),
+ FRATE(0, "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
+ 60000000),
+ FRATE(0, "phyclk_usbhost20_phy_clk48mohci_phy", NULL, CLK_IS_ROOT,
+ 48000000),
+ FRATE(0, "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
+ 60000000),
+ /* PHY clocks from UFS_PHY */
+ FRATE(0, "phyclk_ufs_tx0_symbol_phy", NULL, CLK_IS_ROOT, 300000000),
+ FRATE(0, "phyclk_ufs_rx0_symbol_phy", NULL, CLK_IS_ROOT, 300000000),
+ FRATE(0, "phyclk_ufs_tx1_symbol_phy", NULL, CLK_IS_ROOT, 300000000),
+ FRATE(0, "phyclk_ufs_rx1_symbol_phy", NULL, CLK_IS_ROOT, 300000000),
+ /* PHY clocks from LLI_PHY */
+ FRATE(0, "phyclk_lli_mphy_to_ufs_phy", NULL, CLK_IS_ROOT, 260000000),
+};
+
static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
/* MUX_SEL_FSYS0 */
+ MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
+ mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
/* MUX_SEL_FSYS1 */
+ MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
+ mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
+ MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
+ mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
+ MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
+ mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
+ MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
+ mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
+
+ /* MUX_SEL_FSYS2 */
+ MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
+ "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
+ mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
+ MUX_SEL_FSYS2, 28, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
+ "mout_phyclk_usbhost30_uhost30_phyclock_user",
+ mout_phyclk_usbhost30_uhost30_phyclock_user_p,
+ MUX_SEL_FSYS2, 24, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
+ "mout_phyclk_usbhost20_phy_hsic1",
+ mout_phyclk_usbhost20_phy_hsic1_p,
+ MUX_SEL_FSYS2, 20, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
+ "mout_phyclk_usbhost20_phy_clk48mohci_user",
+ mout_phyclk_usbhost20_phy_clk48mohci_user_p,
+ MUX_SEL_FSYS2, 16, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
+ "mout_phyclk_usbhost20_phy_phyclock_user",
+ mout_phyclk_usbhost20_phy_phyclock_user_p,
+ MUX_SEL_FSYS2, 12, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
+ "mout_phyclk_usbhost20_phy_freeclk_user",
+ mout_phyclk_usbhost20_phy_freeclk_user_p,
+ MUX_SEL_FSYS2, 8, 1),
+ MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
+ "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
+ mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
+ MUX_SEL_FSYS2, 4, 1),
+ MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
+ "mout_phyclk_usbdrd30_udrd30_phyclock_user",
+ mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
+ MUX_SEL_FSYS2, 0, 1),
+
+ /* MUX_SEL_FSYS3 */
+ MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
+ "mout_phyclk_ufs_rx1_symbol_user",
+ mout_phyclk_ufs_rx1_symbol_user_p,
+ MUX_SEL_FSYS3, 16, 1),
+ MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
+ "mout_phyclk_ufs_rx0_symbol_user",
+ mout_phyclk_ufs_rx0_symbol_user_p,
+ MUX_SEL_FSYS3, 12, 1),
+ MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
+ "mout_phyclk_ufs_tx1_symbol_user",
+ mout_phyclk_ufs_tx1_symbol_user_p,
+ MUX_SEL_FSYS3, 8, 1),
+ MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
+ "mout_phyclk_ufs_tx0_symbol_user",
+ mout_phyclk_ufs_tx0_symbol_user_p,
+ MUX_SEL_FSYS3, 4, 1),
+ MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
+ "mout_phyclk_lli_mphy_to_ufs_user",
+ mout_phyclk_lli_mphy_to_ufs_user_p,
+ MUX_SEL_FSYS4, 0, 1),
+
+ /* MUX_SEL_FSYS4 */
+ MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
+ MUX_SEL_FSYS4, 0, 1),
};
static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
@@ -1889,13 +2041,145 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
+ /* ENABLE_ACLK_FSYS1 */
+ GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 24, 0, 0),
+ GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 13, 0, 0),
+ GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 12, 0, 0),
+ GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_FSYS */
+ GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 17, 0, 0),
+ GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 14, 0, 0),
+ GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 13, 0, 0),
+ GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 5, 0, 0),
+ GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
+ "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
+ GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
+ "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
+ GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
+ "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
+ 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_SCLK_FSYS */
+ GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
+ ENABLE_SCLK_FSYS, 21, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
+ "phyclk_usbhost30_uhost30_pipe_pclk",
+ "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
+ ENABLE_SCLK_FSYS, 18, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
+ "phyclk_usbhost30_uhost30_phyclock",
+ "mout_phyclk_usbhost30_uhost30_phyclock_user",
+ ENABLE_SCLK_FSYS, 17, 0, 0),
+ GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
+ "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
+ 16, 0, 0),
+ GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
+ "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
+ 15, 0, 0),
+ GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
+ "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
+ 14, 0, 0),
+ GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
+ "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
+ 13, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
+ "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
+ 12, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
+ "phyclk_usbhost20_phy_clk48mohci",
+ "mout_phyclk_usbhost20_phy_clk48mohci_user",
+ ENABLE_SCLK_FSYS, 11, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
+ "phyclk_usbhost20_phy_phyclock",
+ "mout_phyclk_usbhost20_phy_phyclock_user",
+ ENABLE_SCLK_FSYS, 10, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
+ "phyclk_usbhost20_phy_freeclk",
+ "mout_phyclk_usbhost20_phy_freeclk_user",
+ ENABLE_SCLK_FSYS, 9, 0, 0),
+ GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
+ "phyclk_usbdrd30_udrd30_pipe_pclk",
+ "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
+ ENABLE_SCLK_FSYS, 8, 0, 0),
+ GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
+ "phyclk_usbdrd30_udrd30_phyclock",
+ "mout_phyclk_usbdrd30_udrd30_phyclock_user",
+ ENABLE_SCLK_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
+ ENABLE_SCLK_FSYS, 6, 0, 0),
+ GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
+ ENABLE_SCLK_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
+ ENABLE_SCLK_FSYS, 1, 0, 0),
+ GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
+ ENABLE_SCLK_FSYS, 0, 0, 0),
/* ENABLE_IP_FSYS0 */
GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
@@ -1907,6 +2191,8 @@ static struct samsung_cmu_info fsys_cmu_info __initdata = {
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
+ .fixed_clks = fsys_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
.nr_clk_ids = FSYS_NR_CLK,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 8c44674..e76300a 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -110,6 +110,10 @@
#define CLK_DIV_ACLK_G3D_400 137
#define CLK_DIV_ACLK_BUS0_400 138
#define CLK_DIV_ACLK_BUS1_400 139
+#define CLK_DIV_SCLK_PCIE_100 140
+#define CLK_DIV_SCLK_USBHOST30 141
+#define CLK_DIV_SCLK_UFSUNIPRO 142
+#define CLK_DIV_SCLK_USBDRD30 143
#define CLK_ACLK_PERIC_66 200
#define CLK_ACLK_PERIS_66 201
@@ -139,8 +143,12 @@
#define CLK_ACLK_BUS1_400 225
#define CLK_ACLK_IMEM_200 226
#define CLK_ACLK_IMEM_266 227
+#define CLK_SCLK_PCIE_100_FSYS 228
+#define CLK_SCLK_UFSUNIPRO_FSYS 229
+#define CLK_SCLK_USBHOST30_FSYS 230
+#define CLK_SCLK_USBDRD30_FSYS 231
-#define TOP_NR_CLK 228
+#define TOP_NR_CLK 232
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -473,6 +481,25 @@
#define CLK_MOUT_SCLK_MMC2_USER 2
#define CLK_MOUT_SCLK_MMC1_USER 3
#define CLK_MOUT_SCLK_MMC0_USER 4
+#define CLK_MOUT_SCLK_UFS_MPHY_USER 5
+#define CLK_MOUT_SCLK_PCIE_100_USER 6
+#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7
+#define CLK_MOUT_SCLK_USBHOST30_USER 8
+#define CLK_MOUT_SCLK_USBDRD30_USER 9
+#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10
+#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15
+#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16
+#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17
+#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
+#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19
+#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20
+#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21
+#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22
+#define CLK_MOUT_SCLK_MPHY 23
#define CLK_ACLK_PCIE 50
#define CLK_ACLK_PDMA1 51
@@ -490,8 +517,57 @@
#define CLK_SCLK_MMC0 63
#define CLK_PDMA1 64
#define CLK_PDMA0 65
-
-#define FSYS_NR_CLK 66
+#define CLK_ACLK_XIU_FSYSPX 66
+#define CLK_ACLK_AHB_USBLINKH1 67
+#define CLK_ACLK_SMMU_PDMA1 68
+#define CLK_ACLK_BTS_PCIE 69
+#define CLK_ACLK_AXIUS_PDMA1 70
+#define CLK_ACLK_SMMU_PDMA0 71
+#define CLK_ACLK_BTS_UFS 72
+#define CLK_ACLK_BTS_USBHOST30 73
+#define CLK_ACLK_BTS_USBDRD30 74
+#define CLK_ACLK_AXIUS_PDMA0 75
+#define CLK_ACLK_AXIUS_USBHS 76
+#define CLK_ACLK_AXIUS_FSYSSX 77
+#define CLK_ACLK_AHB2APB_FSYSP 78
+#define CLK_ACLK_AHB2AXI_USBHS 79
+#define CLK_ACLK_AHB_USBLINKH0 80
+#define CLK_ACLK_AHB_USBHS 81
+#define CLK_ACLK_AHB_FSYSH 82
+#define CLK_ACLK_XIU_FSYSX 83
+#define CLK_ACLK_XIU_FSYSSX 84
+#define CLK_ACLK_FSYSNP_200 85
+#define CLK_ACLK_FSYSND_200 86
+#define CLK_PCLK_PCIE_CTRL 87
+#define CLK_PCLK_SMMU_PDMA1 88
+#define CLK_PCLK_PCIE_PHY 89
+#define CLK_PCLK_BTS_PCIE 90
+#define CLK_PCLK_SMMU_PDMA0 91
+#define CLK_PCLK_BTS_UFS 92
+#define CLK_PCLK_BTS_USBHOST30 93
+#define CLK_PCLK_BTS_USBDRD30 94
+#define CLK_PCLK_GPIO_FSYS 95
+#define CLK_PCLK_PMU_FSYS 96
+#define CLK_PCLK_SYSREG_FSYS 97
+#define CLK_SCLK_PCIE_100 98
+#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99
+#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100
+#define CLK_PHYCLK_UFS_RX1_SYMBOL 101
+#define CLK_PHYCLK_UFS_RX0_SYMBOL 102
+#define CLK_PHYCLK_UFS_TX1_SYMBOL 103
+#define CLK_PHYCLK_UFS_TX0_SYMBOL 104
+#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105
+#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106
+#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107
+#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108
+#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109
+#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110
+#define CLK_SCLK_MPHY 111
+#define CLK_SCLK_UFSUNIPRO 112
+#define CLK_SCLK_USBHOST30 113
+#define CLK_SCLK_USBDRD30 114
+
+#define FSYS_NR_CLK 115
/* CMU_G2D */
#define CLK_MUX_ACLK_G2D_266_USER 1
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
2014-12-02 8:49 ` [PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain Chanwoo Choi
@ 2014-12-09 6:03 ` Pankaj Dubey
0 siblings, 0 replies; 44+ messages in thread
From: Pankaj Dubey @ 2014-12-09 6:03 UTC (permalink / raw)
To: Chanwoo Choi, linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, a.kesavan, devicetree, linux-arm-kernel
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
> contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Inki Dae <inki.dae@samsung.com>
> Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos5433.c | 286 +++++++++++++++++++++++++++++++++
> include/dt-bindings/clock/exynos5433.h | 82 +++++++++-
> 2 files changed, 365 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index 5b4ec83..e2b7ea6 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -464,6 +464,16 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
> DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
> DIV_TOP_FSYS1, 0, 4),
>
> + /* DIV_TOP_FSYS2 */
> + DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
> + DIV_TOP_FSYS2, 12, 3),
> + DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
> + "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
> + DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
> + "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
> + DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
> + DIV_TOP_FSYS2, 0, 4),
> +
> /* DIV_TOP_PERIC0 */
> DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
> DIV_TOP_PERIC0, 16, 8),
> @@ -536,12 +546,20 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
> ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
>
> /* ENABLE_SCLK_TOP_FSYS */
> + GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
> + ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
> GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
> ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
> GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
> ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
> GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
> ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
> + GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
> + "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_ufsunipro_fsys is '3'.
> + GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
> + "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_usbhost30_fsys is '1'.
> + GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
> + "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_usbdrd30_fsys is '0'.
>
> /* ENABLE_SCLK_TOP_PERIC */
> GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
> @@ -1819,10 +1837,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
> #define ENABLE_IP_FSYS1 0x0b04
>
> /* list of all parent clock list */
> +PNAME(mout_sclk_ufs_mphy_user_p) = { "fin_pll", "sclk_ufs_mphy", };
> PNAME(mout_aclk_fsys_200_user_p) = { "fin_pll", "aclk_fsys_200", };
> +PNAME(mout_sclk_pcie_100_user_p) = { "fin_pll", "sclk_ufsunipro_fsys",};
This parent list looks wrong.
As per UM, it should be: { "fin_pll", "sclk_pcie_100_fsys",};
> +PNAME(mout_sclk_ufsunipro_user_p) = { "fin_pll", "sclk_ufsunipro_fsys",};
> PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2_fsys", };
> PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1_fsys", };
> PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0_fsys", };
> +PNAME(mout_sclk_usbhost30_user_p) = { "fin_pll", "sclk_usbhost30_fsys",};
> +PNAME(mout_sclk_usbdrd30_user_p) = { "fin_pll", "sclk_usbdrd30_fsys", };
> +
> +PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
> + = { "fin_pll", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
> +PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
> + = { "fin_pll", "phyclk_usbhost30_uhost30_phyclock_phy", };
> +PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
> + = { "fin_pll", "phyclk_usbhost20_phy_hsic1_phy", };
> +PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
> + = { "fin_pll", "phyclk_usbhost20_phy_clk48mohci_phy", };
> +PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
> + = { "fin_pll", "phyclk_usbhost20_phy_phyclock_phy", };
> +PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
> + = { "fin_pll", "phyclk_usbhost20_phy_freeclk_phy", };
> +PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
> + = { "fin_pll", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
Here second parent should be 'phyclk_usbdrd30_udrd30_pipe_pclk_phy'.
> +PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
> + = { "fin_pll", "phyclk_usbhost30_uhost30_phyclock_phy", };
Here second parent should be 'phyclk_usbdrd30_udrd30_phyclock_phy'.
> +PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
> + = { "fin_pll", "phyclk_ufs_rx1_symbol_phy", };
> +PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
> + = { "fin_pll", "phyclk_ufs_rx0_symbol_phy", };
> +PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
> + = { "fin_pll", "phyclk_ufs_tx1_symbol_phy", };
> +PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
> + = { "fin_pll", "phyclk_ufs_tx0_symbol_phy", };
> +PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
> + = { "fin_pll", "phyclk_lli_mphy_to_ufs_phy", };
> +PNAME(mout_sclk_mphy_p)
> + = { "mout_sclk_ufs_mphy_user",
> + "mout_phyclk_lli_mphy_to_ufs_user", };
>
> static unsigned long fsys_clk_regs[] __initdata = {
> MUX_SEL_FSYS0,
> @@ -1850,18 +1903,117 @@ static unsigned long fsys_clk_regs[] __initdata = {
> ENABLE_IP_FSYS1,
> };
>
> +static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
> + /* PHY clocks from USBDRD30_PHY */
> + FRATE(0, "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, CLK_IS_ROOT,
> + 60000000),
> + FRATE(0, "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, CLK_IS_ROOT,
> + 125000000),
> + /* PHY clocks from USBHOST30_PHY */
> + FRATE(0, "phyclk_usbhost30_uhost30_phyclock_phy", NULL, CLK_IS_ROOT,
> + 60000000),
> + FRATE(0, "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, CLK_IS_ROOT,
> + 125000000),
> + /* PHY clocks from USBHOST20_PHY */
> + FRATE(0, "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
> + 60000000),
> + FRATE(0, "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
> + 60000000),
> + FRATE(0, "phyclk_usbhost20_phy_clk48mohci_phy", NULL, CLK_IS_ROOT,
> + 48000000),
> + FRATE(0, "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
> + 60000000),
> + /* PHY clocks from UFS_PHY */
> + FRATE(0, "phyclk_ufs_tx0_symbol_phy", NULL, CLK_IS_ROOT, 300000000),
> + FRATE(0, "phyclk_ufs_rx0_symbol_phy", NULL, CLK_IS_ROOT, 300000000),
> + FRATE(0, "phyclk_ufs_tx1_symbol_phy", NULL, CLK_IS_ROOT, 300000000),
> + FRATE(0, "phyclk_ufs_rx1_symbol_phy", NULL, CLK_IS_ROOT, 300000000),
> + /* PHY clocks from LLI_PHY */
> + FRATE(0, "phyclk_lli_mphy_to_ufs_phy", NULL, CLK_IS_ROOT, 260000000),
This should be 26 MHz or 260 MHz? Please cross verify.
> +};
> +
> static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
> /* MUX_SEL_FSYS0 */
> + MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
> + mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
> MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
> mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
>
> /* MUX_SEL_FSYS1 */
> + MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
> + mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
> + MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
> + mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
> MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
> mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
> MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
> mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
> MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
> mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
> + MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
> + mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
> + MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
> + mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
> +
> + /* MUX_SEL_FSYS2 */
> + MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
> + "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
> + mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
> + MUX_SEL_FSYS2, 28, 1),
> + MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
> + "mout_phyclk_usbhost30_uhost30_phyclock_user",
> + mout_phyclk_usbhost30_uhost30_phyclock_user_p,
> + MUX_SEL_FSYS2, 24, 1),
> + MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
> + "mout_phyclk_usbhost20_phy_hsic1",
> + mout_phyclk_usbhost20_phy_hsic1_p,
> + MUX_SEL_FSYS2, 20, 1),
> + MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
> + "mout_phyclk_usbhost20_phy_clk48mohci_user",
> + mout_phyclk_usbhost20_phy_clk48mohci_user_p,
> + MUX_SEL_FSYS2, 16, 1),
> + MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
> + "mout_phyclk_usbhost20_phy_phyclock_user",
> + mout_phyclk_usbhost20_phy_phyclock_user_p,
> + MUX_SEL_FSYS2, 12, 1),
> + MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
> + "mout_phyclk_usbhost20_phy_freeclk_user",
> + mout_phyclk_usbhost20_phy_freeclk_user_p,
> + MUX_SEL_FSYS2, 8, 1),
> + MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
> + "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
> + mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
> + MUX_SEL_FSYS2, 4, 1),
> + MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
> + "mout_phyclk_usbdrd30_udrd30_phyclock_user",
> + mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
> + MUX_SEL_FSYS2, 0, 1),
> +
> + /* MUX_SEL_FSYS3 */
> + MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
> + "mout_phyclk_ufs_rx1_symbol_user",
> + mout_phyclk_ufs_rx1_symbol_user_p,
> + MUX_SEL_FSYS3, 16, 1),
> + MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
> + "mout_phyclk_ufs_rx0_symbol_user",
> + mout_phyclk_ufs_rx0_symbol_user_p,
> + MUX_SEL_FSYS3, 12, 1),
> + MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
> + "mout_phyclk_ufs_tx1_symbol_user",
> + mout_phyclk_ufs_tx1_symbol_user_p,
> + MUX_SEL_FSYS3, 8, 1),
> + MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
> + "mout_phyclk_ufs_tx0_symbol_user",
> + mout_phyclk_ufs_tx0_symbol_user_p,
> + MUX_SEL_FSYS3, 4, 1),
> + MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
> + "mout_phyclk_lli_mphy_to_ufs_user",
> + mout_phyclk_lli_mphy_to_ufs_user_p,
> + MUX_SEL_FSYS4, 0, 1),
Please change MUX_SEL_FSYS4 -> MUX_SEL_FSYS3
> +
> + /* MUX_SEL_FSYS4 */
> + MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
> + MUX_SEL_FSYS4, 0, 1),
> };
>
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (8 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-09 6:28 ` Pankaj Dubey
2014-12-02 8:49 ` [PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain Chanwoo Choi
` (7 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: mark.rutland, jh80.chung, geunsik.lim, kgene.kim, arnd, cw00.choi,
marc.zyngier, catalin.marinas, will.deacon, tomasz.figa,
a.kesavan, inki.dae, sw0312.kim, kyungmin.park, linux-arm-kernel,
s.nawrocki, pankaj.dubey, olof, chanho61.park, devicetree
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 127 +++++++++++++++++++++
include/dt-bindings/clock/exynos5433.h | 25 ++++
3 files changed, 160 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 03ae40a..589ed93 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -28,6 +28,8 @@ Required Properties:
- "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
which generates global data buses clock and global peripheral buses clock.
+ - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
+ which generates clocks for 3D Graphics Engine IP.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -115,6 +117,12 @@ Example 1: Examples of clock controller nodes are listed below.
#clock-cells = <1>;
};
+ cmu_g3d: clock-controller@0x14aa0000 {
+ compatible = "samsung,exynos5433-cmu-g3d";
+ reg = <0x14aa0000 0x1000>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index e2b7ea6..a7f5feb 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3096,3 +3096,130 @@ CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
exynos5433_cmu_bus_init(0);
exynos5433_cmu_bus_init(1);
exynos5433_cmu_bus_init(2);
+
+/*
+ * Register offset definitions for CMU_G3D
+ */
+#define G3D_PLL_LOCK 0x0000
+#define G3D_PLL_CON0 0x0100
+#define G3D_PLL_CON1 0x0104
+#define G3D_PLL_FREQ_DET 0x010c
+#define MUX_SEL_G3D 0x0200
+#define MUX_ENABLE_G3D 0x0300
+#define MUX_STAT_G3D 0x0400
+#define DIV_G3D 0x0600
+#define DIV_G3D_PLL_FREQ_DET 0x0604
+#define DIV_STAT_G3D 0x0700
+#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
+#define ENABLE_ACLK_G3D 0x0800
+#define ENABLE_PCLK_G3D 0x0900
+#define ENABLE_SCLK_G3D 0x0a00
+#define ENABLE_IP_G3D0 0x0b00
+#define ENABLE_IP_G3D1 0x0b04
+#define CLKOUT_CMU_G3D 0x0c00
+#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
+#define CLK_STOPCTRL 0x1000
+
+static unsigned long g3d_clk_regs[] __initdata = {
+ G3D_PLL_LOCK,
+ G3D_PLL_CON0,
+ G3D_PLL_CON1,
+ G3D_PLL_FREQ_DET,
+ MUX_SEL_G3D,
+ MUX_ENABLE_G3D,
+ MUX_STAT_G3D,
+ DIV_G3D,
+ DIV_G3D_PLL_FREQ_DET,
+ DIV_STAT_G3D,
+ DIV_STAT_G3D_PLL_FREQ_DET,
+ ENABLE_ACLK_G3D,
+ ENABLE_PCLK_G3D,
+ ENABLE_SCLK_G3D,
+ ENABLE_IP_G3D0,
+ ENABLE_IP_G3D1,
+ CLKOUT_CMU_G3D,
+ CLKOUT_CMU_G3D_DIV_STAT,
+ CLK_STOPCTRL,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
+PNAME(mout_g3d_pll_p) = { "fin_pll", "fout_g3d_pll", };
+
+static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
+ PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
+ G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
+ /* MUX_SEL_G3D */
+ MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
+ MUX_SEL_G3D, 8, 1),
+ MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+ MUX_SEL_G3D, 0, 1),
+};
+
+static struct samsung_div_clock g3d_div_clks[] __initdata = {
+ /* DIV_G3D */
+ DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
+ 8, 2),
+ DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
+ 4, 3),
+ DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
+ 0, 3),
+};
+
+static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_G3D */
+ GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 7, 0, 0),
+ GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 6, 0, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
+ ENABLE_ACLK_G3D, 5, 0, 0),
+ GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 4, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
+ ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
+ ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 0, 0, 0),
+
+ /* ENABLE_PCLK_G3D */
+ GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
+ ENABLE_PCLK_G3D, 3, 0, 0),
+ GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
+ ENABLE_PCLK_G3D, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
+ ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
+ ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_G3D */
+ GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
+ ENABLE_SCLK_G3D, 0, 0, 0),
+};
+
+static struct samsung_cmu_info g3d_cmu_info __initdata = {
+ .pll_clks = g3d_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
+ .mux_clks = g3d_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
+ .div_clks = g3d_div_clks,
+ .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
+ .gate_clks = g3d_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
+ .nr_clk_ids = G3D_NR_CLK,
+ .clk_regs = g3d_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
+};
+
+static void __init exynos5433_cmu_g3d_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &g3d_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
+ exynos5433_cmu_g3d_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index e76300a..04d4dbf 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -780,4 +780,29 @@
#define BUSx_NR_CLK 11
+/* CMU_G3D */
+#define CLK_FOUT_G3D_PLL 1
+
+#define CLK_MOUT_ACLK_G3D_400 2
+#define CLK_MOUT_G3D_PLL 3
+
+#define CLK_DIV_SCLK_HPM_G3D 4
+#define CLK_DIV_PCLK_G3D 5
+#define CLK_DIV_ACLK_G3D 6
+#define CLK_ACLK_BTS_G3D1 7
+#define CLK_ACLK_BTS_G3D0 8
+#define CLK_ACLK_ASYNCAPBS_G3D 9
+#define CLK_ACLK_ASYNCAPBM_G3D 10
+#define CLK_ACLK_AHB2APB_G3DP 11
+#define CLK_ACLK_G3DNP_150 12
+#define CLK_ACLK_G3DND_600 13
+#define CLK_ACLK_G3D 14
+#define CLK_PCLK_BTS_G3D1 15
+#define CLK_PCLK_BTS_G3D0 16
+#define CLK_PCLK_PMU_G3D 17
+#define CLK_PCLK_SYSREG_G3D 18
+#define CLK_SCLK_HPM_G3D 19
+
+#define G3D_NR_CLK 20
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain
2014-12-02 8:49 ` [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain Chanwoo Choi
@ 2014-12-09 6:28 ` Pankaj Dubey
0 siblings, 0 replies; 44+ messages in thread
From: Pankaj Dubey @ 2014-12-09 6:28 UTC (permalink / raw)
To: Chanwoo Choi, linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, a.kesavan, devicetree, linux-arm-kernel
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
> the clocks for GPU(3D Graphics Engine).
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Inki Dae <inki.dae@samsung.com>
> Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (9 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-09 7:48 ` Pankaj Dubey
2014-12-02 8:49 ` [PATCH 13/19] arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support Chanwoo Choi
` (6 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++
include/dt-bindings/clock/exynos5433.h | 37 +++++-
3 files changed, 188 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 589ed93..bf72817 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -30,6 +30,8 @@ Required Properties:
which generates global data buses clock and global peripheral buses clock.
- "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
which generates clocks for 3D Graphics Engine IP.
+ - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
+ which generates clocks for GSCALER IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -123,6 +125,12 @@ Example 1: Examples of clock controller nodes are listed below.
#clock-cells = <1>;
};
+ cmu_gscl: clock-controller@0x13cf0000 {
+ compatible = "samsung,exynos5433-cmu-gscl";
+ reg = <0x13cf0000 0x0b10>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index a7f5feb..00dcac3 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -540,6 +540,10 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
+ ENABLE_ACLK_TOP, 15, 0, 0),
+ GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
+ ENABLE_ACLK_TOP, 14, 0, 0),
GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
@@ -3223,3 +3227,143 @@ static void __init exynos5433_cmu_g3d_init(struct device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
exynos5433_cmu_g3d_init);
+
+/*
+ * Register offset definitions for CMU_GSCL
+ */
+#define MUX_SEL_GSCL 0x0200
+#define MUX_ENABLE_GSCL 0x0300
+#define MUX_STAT_GSCL 0x0400
+#define ENABLE_ACLK_GSCL 0x0800
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
+#define ENABLE_PCLK_GSCL 0x0900
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
+#define ENABLE_IP_GSCL0 0x0b00
+#define ENABLE_IP_GSCL1 0x0b04
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
+
+static unsigned long gscl_clk_regs[] __initdata = {
+ MUX_SEL_GSCL,
+ MUX_ENABLE_GSCL,
+ MUX_STAT_GSCL,
+ ENABLE_ACLK_GSCL,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_PCLK_GSCL,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_IP_GSCL0,
+ ENABLE_IP_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
+};
+
+/* list of all parent clock list */
+PNAME(aclk_gscl_111_user_p) = { "fin_pll", "aclk_gscl_111", };
+PNAME(aclk_gscl_333_user_p) = { "fin_pll", "aclk_gscl_333", };
+
+static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
+ /* MUX_SEL_GSCL */
+ MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
+ aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
+ aclk_gscl_333_user_p, MUX_SEL_GSCL, 4, 1),
+};
+
+static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_GSCL */
+ GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 11, 0, 0),
+ GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 10, 0, 0),
+ GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 9, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
+ "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
+ 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 7, 0, 0),
+ GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
+ ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
+ "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
+ GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
+ "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
+ GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 3, 0, 0),
+ GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 2, 0, 0),
+ GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 1, 0, 0),
+ GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 0, 0, 0),
+
+ /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
+ GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+
+ /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
+ GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
+
+ /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
+ GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
+
+ /* ENABLE_PCLK_GSCL */
+ GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 7, 0, 0),
+ GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 6, 0, 0),
+ GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 5, 0, 0),
+ GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
+ "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 2, 0, 0),
+ GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 1, 0, 0),
+ GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 0, 0, 0),
+
+ /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
+ GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+
+ /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
+ GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+
+ /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
+ GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+};
+
+static struct samsung_cmu_info gscl_cmu_info __initdata = {
+ .mux_clks = gscl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
+ .gate_clks = gscl_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
+ .nr_clk_ids = GSCL_NR_CLK,
+ .clk_regs = gscl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
+};
+
+static void __init exynos5433_cmu_gscl_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &gscl_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
+ exynos5433_cmu_gscl_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 04d4dbf..15d51b8 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -147,8 +147,10 @@
#define CLK_SCLK_UFSUNIPRO_FSYS 229
#define CLK_SCLK_USBHOST30_FSYS 230
#define CLK_SCLK_USBDRD30_FSYS 231
+#define CLK_ACLK_GSCL_111 232
+#define CLK_ACLK_GSCL_333 233
-#define TOP_NR_CLK 232
+#define TOP_NR_CLK 234
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -805,4 +807,37 @@
#define G3D_NR_CLK 20
+/* CMU_GSCL */
+#define CLK_MOUT_ACLK_GSCL_111_USER 1
+#define CLK_MOUT_ACLK_GSCL_333_USER 2
+
+#define CLK_ACLK_BTS_GSCL2 3
+#define CLK_ACLK_BTS_GSCL1 4
+#define CLK_ACLK_BTS_GSCL0 5
+#define CLK_ACLK_AHB2APB_GSCLP 6
+#define CLK_ACLK_XIU_GSCLX 7
+#define CLK_ACLK_GSCLNP_111 8
+#define CLK_ACLK_GSCLRTND_333 9
+#define CLK_ACLK_GSCLBEND_333 10
+#define CLK_ACLK_GSD 11
+#define CLK_ACLK_GSCL2 12
+#define CLK_ACLK_GSCL1 13
+#define CLK_ACLK_GSCL0 14
+#define CLK_ACLK_SMMU_GSCL0 15
+#define CLK_ACLK_SMMU_GSCL1 16
+#define CLK_ACLK_SMMU_GSCL2 17
+#define CLK_PCLK_BTS_GSCL2 18
+#define CLK_PCLK_BTS_GSCL1 19
+#define CLK_PCLK_BTS_GSCL0 20
+#define CLK_PCLK_PMU_GSCL 21
+#define CLK_PCLK_SYSREG_GSCL 22
+#define CLK_PCLK_GSCL2 23
+#define CLK_PCLK_GSCL1 24
+#define CLK_PCLK_GSCL0 25
+#define CLK_PCLK_SMMU_GSCL0 26
+#define CLK_PCLK_SMMU_GSCL1 27
+#define CLK_PCLK_SMMU_GSCL2 28
+
+#define GSCL_NR_CLK 29
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
2014-12-02 8:49 ` [PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain Chanwoo Choi
@ 2014-12-09 7:48 ` Pankaj Dubey
0 siblings, 0 replies; 44+ messages in thread
From: Pankaj Dubey @ 2014-12-09 7:48 UTC (permalink / raw)
To: Chanwoo Choi, linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, a.kesavan, devicetree, linux-arm-kernel
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
> clocks.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Inki Dae <inki.dae@samsung.com>
> Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
> ---
> .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
> drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++
> include/dt-bindings/clock/exynos5433.h | 37 +++++-
> 3 files changed, 188 insertions(+), 1 deletion(-)
>
[snip]
> }
> CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
> exynos5433_cmu_g3d_init);
> +
> +/*
> + * Register offset definitions for CMU_GSCL
> + */
> +#define MUX_SEL_GSCL 0x0200
> +#define MUX_ENABLE_GSCL 0x0300
> +#define MUX_STAT_GSCL 0x0400
> +#define ENABLE_ACLK_GSCL 0x0800
> +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
> +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
> +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
> +#define ENABLE_PCLK_GSCL 0x0900
> +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
> +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
> +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
> +#define ENABLE_IP_GSCL0 0x0b00
> +#define ENABLE_IP_GSCL1 0x0b04
> +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
> +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
> +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
> +
nit: tabspace after #define should be changed to one whitespace.
> +static unsigned long gscl_clk_regs[] __initdata = {
> + MUX_SEL_GSCL,
> + MUX_ENABLE_GSCL,
> + MUX_STAT_GSCL,
> + ENABLE_ACLK_GSCL,
> + ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
> + ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
> + ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
> + ENABLE_PCLK_GSCL,
> + ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
> + ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
> + ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
> + ENABLE_IP_GSCL0,
> + ENABLE_IP_GSCL1,
> + ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
> + ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
> + ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
> +};
> +
> +/* list of all parent clock list */
> +PNAME(aclk_gscl_111_user_p) = { "fin_pll", "aclk_gscl_111", };
> +PNAME(aclk_gscl_333_user_p) = { "fin_pll", "aclk_gscl_333", };
> +
> +static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
> + /* MUX_SEL_GSCL */
> + MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
> + aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
> + MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
> + aclk_gscl_333_user_p, MUX_SEL_GSCL, 4, 1),
aclk_gscl_333_user mux clock has a shift of '0'.
> +};
> +
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 13/19] arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (10 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-02 8:49 ` [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC Chanwoo Choi
` (5 subsequent siblings)
17 siblings, 0 replies; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds the necessary Kconfig entries to enable
support for the ARMv8 based Exynos5433 SoC.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
---
arch/arm64/Kconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index fa708a0..3fa5d91 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -146,6 +146,16 @@ config ARCH_EXYNOS
help
This enables support for Samsung Exynos SoC family
+config ARCH_EXYNOS5433
+ bool "ARMv8 based Samsung Exynos5433"
+ select ARCH_EXYNOS
+ select COMMON_CLK_SAMSUNG
+ select PINCTRL
+ select PINCTRL_EXYNOS
+
+ help
+ This enables support for Samsung Exynos5433 SoC family
+
config ARCH_EXYNOS7
bool "ARMv8 based Samsung Exynos7"
select ARCH_EXYNOS
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (11 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 13/19] arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
[not found] ` <1417510196-6714-15-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-12-02 8:49 ` [PATCH 15/19] arm64: dts: exynos: Add MSHC dt node for Exynos5433 Chanwoo Choi
` (4 subsequent siblings)
17 siblings, 1 reply; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++++++++++++++
2 files changed, 1213 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 0000000..81fe925
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,698 @@
+/*
+ * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
+ "gpz0-4", "gpz0-5", "gpz0-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&pinctrl_cpif {
+ gpv6: gpv6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_ese {
+ gpj2: gpj2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_finger {
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ hs_i2c6_bus: hs-i2c6-bus {
+ samsung,pins = "gpd5-3", "gpd5-2";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+};
+
+&pinctrl_fsys {
+ gph1: gph1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpr4: gpr4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpr0: gpr0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpr1: gpr1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpr2: gpr2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpr3: gpr3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ sd0_clk: sd0-clk {
+ samsung,pins = "gpr0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_cmd: sd0-cmd {
+ samsung,pins = "gpr0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_rdqs: sd0-rdqs {
+ samsung,pins = "gpr0-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_qrdy: sd0-qrdy {
+ samsung,pins = "gpr0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = "gpr1-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_clk: sd1-clk {
+ samsung,pins = "gpr2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pins = "gpr2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pins = "gpr3-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus8: sd1-bus-width8 {
+ samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ pcie_bus: pcie_bus {
+ samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ };
+
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpr4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpr4-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpr4-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpr4-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_clk_output: sd2-clk-output {
+ samsung,pins = "gpr4-0";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_cmd_output: sd2-cmd-output {
+ samsung,pins = "gpr4-1";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+};
+
+&pinctrl_imem {
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_nfc {
+ gpj0: gpj0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ hs_i2c4_bus: hs-i2c4-bus {
+ samsung,pins = "gpj0-1", "gpj0-0";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+};
+
+&pinctrl_peric {
+ gpv7: gpv7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ hs_i2c8_bus: hs-i2c8-bus {
+ samsung,pins = "gpb0-1", "gpb0-0";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ hs_i2c9_bus: hs-i2c9-bus {
+ samsung,pins = "gpb0-3", "gpb0-2";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
+ "gpd4-3", "gpd4-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
+ "gpd4-3", "gpd4-4";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+
+ spdif_bus: spdif-bus {
+ samsung,pins = "gpd4-3", "gpd4-4";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_spi_pin0: fimc-is-spi-pin0 {
+ samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_spi_pin1: fimc-is-spi-pin1 {
+ samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart0_bus: uart0-bus {
+ samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ hs_i2c2_bus: hs-i2c2-bus {
+ samsung,pins = "gpd0-3", "gpd0-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_bus: uart2-bus {
+ samsung,pins = "gpd1-5", "gpd1-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ uart1_bus: uart1-bus {
+ samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ hs_i2c3_bus: hs-i2c3-bus {
+ samsung,pins = "gpd1-3", "gpd1-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+
+ hs_i2c0_bus: hs-i2c0-bus {
+ samsung,pins = "gpd2-1", "gpd2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ hs_i2c1_bus: hs-i2c1-bus {
+ samsung,pins = "gpd2-3", "gpd2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ hs_i2c7_bus: hs-i2c7-bus {
+ samsung,pins = "gpd2-7", "gpd2-6";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ hs_i2c10_bus: hs-i2c10-bus {
+ samsung,pins = "gpg3-1", "gpg3-0";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ hs_i2c11_bus: hs-i2c11-bus {
+ samsung,pins = "gpg3-3", "gpg3-2";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi3_bus: spi3-bus {
+ samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi4_bus: spi4-bus {
+ samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_uart: fimc-is-uart {
+ samsung,pins = "gpc1-1", "gpc0-7";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_ch0_i2c: fimc-is-ch0_i2c {
+ samsung,pins = "gpc2-1", "gpc2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_ch0_mclk: fimc-is-ch0_mclk {
+ samsung,pins = "gpd7-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_ch1_i2c: fimc-is-ch1-i2c {
+ samsung,pins = "gpc2-3", "gpc2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_ch1_mclk: fimc-is-ch1-mclk {
+ samsung,pins = "gpd7-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_ch2_i2c: fimc-is-ch2-i2c {
+ samsung,pins = "gpc2-5", "gpc2-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ fimc_is_ch2_mclk: fimc-is-ch2-mclk {
+ samsung,pins = "gpd7-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&pinctrl_touch {
+ gpj1: gpj1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ hs_i2c5_bus: hs-i2c5-bus {
+ samsung,pins = "gpj1-1", "gpj1-0";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
new file mode 100644
index 0000000..5637086
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -0,0 +1,515 @@
+/*
+ * Samsung's Exynos5433 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5433 SoC device nodes are listed in this file. Exynos5433
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/exynos5433.h>
+
+/ {
+ compatible = "samsung,exynos5433";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_aud;
+ pinctrl2 = &pinctrl_cpif;
+ pinctrl3 = &pinctrl_ese;
+ pinctrl4 = &pinctrl_finger;
+ pinctrl5 = &pinctrl_fsys;
+ pinctrl6 = &pinctrl_imem;
+ pinctrl7 = &pinctrl_nfc;
+ pinctrl8 = &pinctrl_peric;
+ pinctrl9 = &pinctrl_touch;
+ serial0 = &serial_0;
+ serial1 = &serial_1;
+ serial2 = &serial_2;
+ i2c0 = &hsi2c_0;
+ i2c1 = &hsi2c_1;
+ i2c2 = &hsi2c_2;
+ i2c3 = &hsi2c_3;
+ i2c4 = &hsi2c_4;
+ i2c5 = &hsi2c_5;
+ i2c6 = &hsi2c_6;
+ i2c7 = &hsi2c_7;
+ i2c8 = &hsi2c_8;
+ i2c9 = &hsi2c_9;
+ i2c10 = &hsi2c_10;
+ i2c11 = &hsi2c_11;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x101>;
+ };
+
+ cpu2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x0 0x102>;
+ };
+
+ cpu3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x103>;
+ };
+
+ cpu4: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu5: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu6: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu7: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_off = <0x84000002>;
+ cpu_on = <0xC4000003>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ fin_pll: xxti {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ cmu_top: clock-controller@10030000{
+ compatible = "samsung,exynos5433-cmu-top";
+ reg = <0x10030000 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_cpif: clock-controller@10fc0000{
+ compatible = "samsung,exynos5433-cmu-cpif";
+ reg = <0x10fc0000 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_mif: clock-controller@105b0000{
+ compatible = "samsung,exynos5433-cmu-mif";
+ reg = <0x105b0000 0x100c>;
+ #clock-cells = <1>;
+ };
+
+ cmu_peric: clock-controller@14c80000{
+ compatible = "samsung,exynos5433-cmu-peric";
+ reg = <0x14c80000 0x0b08>;
+ #clock-cells = <1>;
+ };
+
+ cmu_peris: clock-controller@10040000{
+ compatible = "samsung,exynos5433-cmu-peris";
+ reg = <0x10040000 0x0b20>;
+ #clock-cells = <1>;
+ };
+
+ cmu_fsys: clock-controller@156e0000{
+ compatible = "samsung,exynos5433-cmu-fsys";
+ reg = <0x156e0000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_g2d: clock-controller@12460000{
+ compatible = "samsung,exynos5433-cmu-g2d";
+ reg = <0x12460000 0x0b08>;
+ #clock-cells = <1>;
+ };
+
+ cmu_disp: clock-controller@13b90000{
+ compatible = "samsung,exynos5433-cmu-disp";
+ reg = <0x13b90000 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_aud: clock-controller@114c0000{
+ compatible = "samsung,exynos5433-cmu-aud";
+ reg = <0x114c0000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus0: clock-controller@13600000 {
+ compatible = "samsung,exynos5433-cmu-bus0";
+ reg = <0x13600000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus1: clock-controller@14800000 {
+ compatible = "samsung,exynos5433-cmu-bus1";
+ reg = <0x14800000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus2: clock-controller@13400000 {
+ compatible = "samsung,exynos5433-cmu-bus2";
+ reg = <0x13400000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_g3d: clock-controller@14aa0000 {
+ compatible = "samsung,exynos5433-cmu-g3d";
+ reg = <0x14aa0000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_gscl: clock-controller@13cf0000 {
+ compatible = "samsung,exynos5433-cmu-gscl";
+ reg = <0x13cf0000 0x0b10>;
+ #clock-cells = <1>;
+ };
+
+ mct@101c0000 {
+ compatible = "samsung,exynos5433-mct",
+ "samsung,exynos4210-mct";
+ reg = <0x101c0000 0x800>;
+ interrupts = <0 102 0>, <0 103 0>, <0 104 0>, <0 105 0>,
+ <0 106 0>, <0 107 0>, <0 108 0>, <0 109 0>,
+ <0 110 0>, <0 111 0>, <0 112 0>, <0 113 0>;
+ clocks = <&fin_pll>,
+ <&cmu_peris CLK_PCLK_MCT>;
+ clock-names = "fin_pll", "mct";
+ };
+
+ gic:interrupt-controller@11001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x11001000 0x1000>,
+ <0x11002000 0x1000>,
+ <0x11004000 0x2000>,
+ <0x11006000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ serial_0: serial@14c10000 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x14c10000 0x100>;
+ interrupts = <0 421 0>;
+ clocks = <&cmu_peric CLK_PCLK_UART0>,
+ <&cmu_peric CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+ status = "disabled";
+ };
+
+ serial_1: serial@14c20000 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x14c20000 0x100>;
+ interrupts = <0 422 0>;
+ clocks = <&cmu_peric CLK_PCLK_UART1>,
+ <&cmu_peric CLK_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_bus>;
+ status = "disabled";
+ };
+
+ serial_2: serial@14c30000 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x14c30000 0x100>;
+ interrupts = <0 423 0>;
+ clocks = <&cmu_peric CLK_PCLK_UART2>,
+ <&cmu_peric CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_bus>;
+ status = "disabled";
+ };
+
+ pinctrl_alive: pinctrl@10580000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x10580000 0x1000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos7-wakeup-eint";
+ interrupts = <0 16 0>;
+ };
+ };
+
+ pinctrl_aud: pinctrl@114b0000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x114b0000 0x1000>;
+ interrupts = <0 68 0>;
+ };
+
+ pinctrl_cpif: pinctrl@10fe0000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x10fe0000 0x1000>;
+ interrupts = <0 179 0>;
+ };
+
+ pinctrl_ese: pinctrl@14ca0000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x14ca0000 0x1000>;
+ interrupts = <0 413 0>;
+ };
+
+ pinctrl_finger: pinctrl@14cb0000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x14cb0000 0x1000>;
+ interrupts = <0 414 0>;
+ };
+
+ pinctrl_fsys: pinctrl@15690000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x15690000 0x1000>;
+ interrupts = <0 229 0>;
+ };
+
+ pinctrl_imem: pinctrl@11090000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x11090000 0x1000>;
+ interrupts = <0 325 0>;
+ };
+
+ pinctrl_nfc: pinctrl@14cd0000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x14cd0000 0x1000>;
+ interrupts = <0 441 0>;
+ };
+
+ pinctrl_peric: pinctrl@14cc0000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x14cc0000 0x1100>;
+ interrupts = <0 440 0>;
+ };
+
+ pinctrl_touch: pinctrl@14ce0000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x14ce0000 0x1100>;
+ interrupts = <0 442 0>;
+ };
+
+ hsi2c_0: hsi2c@14e40000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14e40000 0x1000>;
+ interrupts = <0 428 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c0_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_1: hsi2c@14e50000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14e50000 0x1000>;
+ interrupts = <0 429 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c1_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_2: hsi2c@14e60000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14e60000 0x1000>;
+ interrupts = <0 430 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c2_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_3: hsi2c@14e70000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14e70000 0x1000>;
+ interrupts = <0 431 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c3_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_4: hsi2c@14ec0000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14ec0000 0x1000>;
+ interrupts = <0 424 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c4_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_5: hsi2c@14ed0000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14ed0000 0x1000>;
+ interrupts = <0 425 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c5_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_6: hsi2c@14ee0000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14ee0000 0x1000>;
+ interrupts = <0 426 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c6_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_7: hsi2c@14ef0000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14ef0000 0x1000>;
+ interrupts = <0 427 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c7_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_8: hsi2c@14d90000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14d90000 0x1000>;
+ interrupts = <0 443 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c8_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_9: hsi2c@14da0000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14da0000 0x1000>;
+ interrupts = <0 444 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c9_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_10: hsi2c@14de0000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14de0000 0x1000>;
+ interrupts = <0 445 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c10_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_11: hsi2c@14df0000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x14df0000 0x1000>;
+ interrupts = <0 446 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c11_bus>;
+ clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <4 13 0xff01>,
+ <4 14 0xff01>,
+ <4 11 0xff01>,
+ <4 10 0xff01>;
+ };
+ };
+};
+
+#include "exynos5433-pinctrl.dtsi"
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 15/19] arm64: dts: exynos: Add MSHC dt node for Exynos5433
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (12 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-02 8:49 ` [PATCH 16/19] arm64: dts: exynos: Add SPI/PDMA " Chanwoo Choi
` (3 subsequent siblings)
17 siblings, 0 replies; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
From: Jaehoon Chung <jh80.chung@samsung.com>
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 5637086..fef9bbc 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -52,6 +52,9 @@
i2c9 = &hsi2c_9;
i2c10 = &hsi2c_10;
i2c11 = &hsi2c_11;
+ mshc0 = &mshc_0;
+ mshc1 = &mshc_1;
+ mshc2 = &mshc_2;
};
cpus {
@@ -502,6 +505,45 @@
status = "disabled";
};
+ mshc_0: mshc@15540000 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 225 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x15540000 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC0>,
+ <&cmu_fsys CLK_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ mshc_1: mshc@15550000 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 226 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x15550000 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC1>,
+ <&cmu_fsys CLK_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ mshc_2: mshc@15560000 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 227 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x15560000 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC2>,
+ <&cmu_fsys CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <4 13 0xff01>,
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 16/19] arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (13 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 15/19] arm64: dts: exynos: Add MSHC dt node for Exynos5433 Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-02 8:49 ` [PATCH 17/19] serial: samsung: Add the support for Exynos5433 SoC Chanwoo Choi
` (2 subsequent siblings)
17 siblings, 0 replies; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 118 +++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index fef9bbc..22f2df8 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -55,6 +55,11 @@
mshc0 = &mshc_0;
mshc1 = &mshc_1;
mshc2 = &mshc_2;
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ spi3 = &spi_3;
+ spi4 = &spi_4;
};
cpus {
@@ -249,6 +254,34 @@
interrupts = <1 9 0xf04>;
};
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pdma0: pdma@15610000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x15610000 0x1000>;
+ interrupts = <0 228 0>;
+ clocks = <&cmu_fsys CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@15600000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x15600000 0x1000>;
+ interrupts = <0 246 0>;
+ clocks = <&cmu_fsys CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+ };
+
serial_0: serial@14c10000 {
compatible = "samsung,exynos5433-uart";
reg = <0x14c10000 0x100>;
@@ -349,6 +382,91 @@
interrupts = <0 442 0>;
};
+ spi_0: spi@14d20000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d20000 0x100>;
+ interrupts = <0 432 0>;
+ dmas = <&pdma0 9>, <&pdma0 8>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI0>,
+ <&cmu_top CLK_SCLK_SPI0_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ status = "disabled";
+ };
+
+ spi_1: spi@14d30000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d30000 0x100>;
+ interrupts = <0 433 0>;
+ dmas = <&pdma0 11>, <&pdma0 10>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI1>,
+ <&cmu_top CLK_SCLK_SPI1_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ status = "disabled";
+ };
+
+ spi_2: spi@14d40000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d40000 0x100>;
+ interrupts = <0 434 0>;
+ dmas = <&pdma0 13>, <&pdma0 12>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI2>,
+ <&cmu_top CLK_SCLK_SPI2_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_bus>;
+ status = "disabled";
+ };
+
+ spi_3: spi@14d50000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d50000 0x100>;
+ interrupts = <0 447 0>;
+ dmas = <&pdma0 23>, <&pdma0 22>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI3>,
+ <&cmu_top CLK_SCLK_SPI3_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_bus>;
+ status = "disabled";
+ };
+
+ spi_4: spi@14d00000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d00000 0x100>;
+ interrupts = <0 412 0>;
+ dmas = <&pdma0 25>, <&pdma0 24>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI4>,
+ <&cmu_top CLK_SCLK_SPI4_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4_bus>;
+ status = "disabled";
+ };
+
hsi2c_0: hsi2c@14e40000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e40000 0x1000>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 17/19] serial: samsung: Add the support for Exynos5433 SoC
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (14 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 16/19] arm64: dts: exynos: Add SPI/PDMA " Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-02 8:49 ` [PATCH 18/19] clocksource: exynos_mct: Add the support for Exynos 64bit SoC Chanwoo Choi
2014-12-02 8:49 ` [PATCH 19/19] arm64: Enable Exynos5433 SoC in the defconfig Chanwoo Choi
17 siblings, 0 replies; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: mark.rutland, catalin.marinas, will.deacon, tomasz.figa,
s.nawrocki, Jiri Slaby, kgene.kim, pankaj.dubey, jh80.chung,
cw00.choi, linux-serial, a.kesavan, devicetree, geunsik.lim, arnd,
marc.zyngier, inki.dae, linux-arm-kernel, Greg Kroah-Hartman,
sw0312.kim, kyungmin.park, olof, chanho61.park
This patch adds new s3c24xx_serial_drv_data structure for Exynos5433 SoC
because Exynos5433 has different fifo size from existing Exynos4 SoC.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: linux-serial@vger.kernel.org
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
drivers/tty/serial/samsung.c | 56 ++++++++++++++++++++++++++++----------------
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index c78f43a..1747fdc 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1771,32 +1771,43 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
#endif
#if defined(CONFIG_ARCH_EXYNOS)
+#define EXYNOS_COMMON_SERIAL_DRV_DATA \
+ .info = &(struct s3c24xx_uart_info) { \
+ .name = "Samsung Exynos UART", \
+ .type = PORT_S3C6400, \
+ .has_divslot = 1, \
+ .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
+ .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
+ .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
+ .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
+ .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
+ .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
+ .def_clk_sel = S3C2410_UCON_CLKSEL0, \
+ .num_clks = 1, \
+ .clksel_mask = 0, \
+ .clksel_shift = 0, \
+ }, \
+ .def_cfg = &(struct s3c2410_uartcfg) { \
+ .ucon = S5PV210_UCON_DEFAULT, \
+ .ufcon = S5PV210_UFCON_DEFAULT, \
+ .has_fracval = 1, \
+ } \
+
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
- .info = &(struct s3c24xx_uart_info) {
- .name = "Samsung Exynos4 UART",
- .type = PORT_S3C6400,
- .has_divslot = 1,
- .rx_fifomask = S5PV210_UFSTAT_RXMASK,
- .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
- .rx_fifofull = S5PV210_UFSTAT_RXFULL,
- .tx_fifofull = S5PV210_UFSTAT_TXFULL,
- .tx_fifomask = S5PV210_UFSTAT_TXMASK,
- .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
- .def_clk_sel = S3C2410_UCON_CLKSEL0,
- .num_clks = 1,
- .clksel_mask = 0,
- .clksel_shift = 0,
- },
- .def_cfg = &(struct s3c2410_uartcfg) {
- .ucon = S5PV210_UCON_DEFAULT,
- .ufcon = S5PV210_UFCON_DEFAULT,
- .has_fracval = 1,
- },
+ EXYNOS_COMMON_SERIAL_DRV_DATA,
.fifosize = { 256, 64, 16, 16 },
};
+
+static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
+ EXYNOS_COMMON_SERIAL_DRV_DATA,
+ .fifosize = { 64, 256, 16, 256 },
+};
+
#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
+#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
#else
#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
+#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
#endif
static struct platform_device_id s3c24xx_serial_driver_ids[] = {
@@ -1818,6 +1829,9 @@ static struct platform_device_id s3c24xx_serial_driver_ids[] = {
}, {
.name = "exynos4210-uart",
.driver_data = EXYNOS4210_SERIAL_DRV_DATA,
+ }, {
+ .name = "exynos5433-uart",
+ .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
},
{ },
};
@@ -1837,6 +1851,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
.data = (void *)S5PV210_SERIAL_DRV_DATA },
{ .compatible = "samsung,exynos4210-uart",
.data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
+ { .compatible = "samsung,exynos5433-uart",
+ .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
{},
};
MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 18/19] clocksource: exynos_mct: Add the support for Exynos 64bit SoC
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (15 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 17/19] serial: samsung: Add the support for Exynos5433 SoC Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
2014-12-02 8:49 ` [PATCH 19/19] arm64: Enable Exynos5433 SoC in the defconfig Chanwoo Choi
17 siblings, 0 replies; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel, Daniel Lezcano, Thomas Gleixner
This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
for Exynos 32bit SoC.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/clocksource/Kconfig | 1 -
drivers/clocksource/exynos_mct.c | 4 ++++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 9042060..27ef3fa 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -134,7 +134,6 @@ config CLKSRC_METAG_GENERIC
config CLKSRC_EXYNOS_MCT
def_bool y if ARCH_EXYNOS
- depends on !ARM64
help
Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9403061..b840ea1 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)
return exynos4_read_count_32();
}
+#if defined(CONFIG_ARM)
static struct delay_timer exynos4_delay_timer;
static cycles_t exynos4_read_current_timer(void)
@@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void)
"cycles_t needs to move to 32-bit for ARM64 usage");
return exynos4_read_count_32();
}
+#endif
static void __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start();
+#if defined(CONFIG_ARM)
exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
exynos4_delay_timer.freq = clk_rate;
register_current_timer_delay(&exynos4_delay_timer);
+#endif
if (clocksource_register_hz(&mct_frc, clk_rate))
panic("%s: can't register clocksource\n", mct_frc.name);
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 19/19] arm64: Enable Exynos5433 SoC in the defconfig
2014-12-02 8:49 [PATCHv2 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
` (16 preceding siblings ...)
2014-12-02 8:49 ` [PATCH 18/19] clocksource: exynos_mct: Add the support for Exynos 64bit SoC Chanwoo Choi
@ 2014-12-02 8:49 ` Chanwoo Choi
17 siblings, 0 replies; 44+ messages in thread
From: Chanwoo Choi @ 2014-12-02 8:49 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene.kim, mark.rutland, marc.zyngier, arnd, olof,
catalin.marinas, will.deacon, s.nawrocki, tomasz.figa,
kyungmin.park, inki.dae, chanho61.park, geunsik.lim, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, pankaj.dubey, devicetree,
linux-arm-kernel
This patch enable Exynos5433 SoC in the arm64 defconfig.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c7ae5ac..7551a50 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -33,6 +33,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5433=y
CONFIG_ARCH_EXYNOS7=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_VEXPRESS=y
--
1.8.5.5
^ permalink raw reply related [flat|nested] 44+ messages in thread