From: Kishon Vijay Abraham I <kishon@ti.com>
To: Yunzhi Li <lyz@rock-chips.com>,
heiko@sntech.de, jwerner@chromium.org, dianders@chromium.org
Cc: huangtao@rock-chips.com, devicetree@vger.kernel.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
zyw@rock-chips.com, Rob Herring <robh+dt@kernel.org>,
olof@lixom.net, cf@rock-chips.com,
linux-arm-kernel@lists.infradead.org,
Grant Likely <grant.likely@linaro.org>
Subject: Re: [PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Date: Thu, 11 Dec 2014 14:06:21 +0530 [thread overview]
Message-ID: <54895785.104@ti.com> (raw)
In-Reply-To: <54894B52.3060105@rock-chips.com>
Hi,
On Thursday 11 December 2014 01:14 PM, Yunzhi Li wrote:
> Hi Kishon:
>
> On 2014/12/11 14:02, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote:
>>> This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
>>> currently this driver can support RK3288. The RK3288 SoC have
>>> three independent USB PHY IPs which are all configured through a
>>> set of registers located in the GRF (general register files)
>>> module.
>>>
>>> Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
>>>
>>> +
>>> +#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
>>> +
>>> +/*
>>> + * The higher 16-bit of this register is used for write protection
>>> + * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
>>> + */
>>> +#define SIDDQ_MSK BIT(13 + 16)
>> I think here the "MSK" is misleading. it should be something that refers write
>> protection?
> So, #define SIDDQ_WRITE_ENA BIT(29) , could be ok ?
yeah. should be fine.
>>> +#define SIDDQ_ON BIT(13)
>>> +#define SIDDQ_OFF (0 << 13)
>>> +
>>> +struct rockchip_usb_phy {
>>> + struct regmap *reg_base;
>>> + unsigned int reg_offset;
>>> + struct clk *clk;
>>> + struct phy *phy;
>>> + unsigned index;
>>> +};
>>> +
>>> +struct rockchip_usb_phy_priv {
>>> + struct rockchip_usb_phy *phys;
>>> + unsigned nphys;
>>> +};
>>> +
>>> +static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
>>> + bool siddq)
>>> +{
>>> + return regmap_write(phy->reg_base, phy->reg_offset,
>>> + SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF));
>> Shouldn't we actually reset the bit for power off?
> Sorry, which bit you refer to here and why should it be reset? could you give
> more infomation.
Never mind. Initially was thinking it might affect bits other than siddq but
anyway you have write lock. So should be fine.
Thanks
Kishon
next prev parent reply other threads:[~2014-12-11 8:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-10 10:46 [PATCH v5 0/5] Patches to add support for Rockchip usb PHYs Yunzhi Li
2014-12-10 10:46 ` [PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY Yunzhi Li
2014-12-11 6:02 ` Kishon Vijay Abraham I
2014-12-11 6:12 ` Joe Perches
2014-12-11 6:27 ` Kishon Vijay Abraham I
[not found] ` <54893963.7060304-l0cyMroinI0@public.gmane.org>
2014-12-11 6:37 ` Joe Perches
[not found] ` <1418279847.18092.32.camel-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>
2014-12-11 6:52 ` Yunzhi Li
[not found] ` <54893F26.5050304-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2014-12-11 7:06 ` Joe Perches
[not found] ` <1418281568.18092.34.camel-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>
2014-12-11 7:16 ` Chris Zhong
[not found] ` <5489338C.1030109-l0cyMroinI0@public.gmane.org>
2014-12-11 7:44 ` Yunzhi Li
2014-12-11 8:36 ` Kishon Vijay Abraham I [this message]
[not found] ` <1418208371-18851-1-git-send-email-lyz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2014-12-10 10:46 ` [PATCH v5 2/5] Documentation: bindings: add dt documentation for Rockchip usb PHY Yunzhi Li
2014-12-10 10:46 ` [PATCH v5 4/5] ARM: dts: rockchip: add rk3288 " Yunzhi Li
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