From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEC9A302CDA for ; Thu, 4 Sep 2025 14:56:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756997801; cv=none; b=rwM8FaOPcrfeqzDTGmen0o+yp7iOAKYdXbrr5BfYjSGaUh84qiY0SOAf6YHCjtT1Epm/kCcliChxYXwjPavCOqcm0j9U6JNj/zWrZDg6xZFnkwS2KUfF8HICcBp+ibTfarWkWFftBIdXU1NK/HjnOhEQM5qhQ29hbx8TN6JLjy4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756997801; c=relaxed/simple; bh=ZgJ9kzqD0PMG1LADlO6mUBMdemIt/OfOhX0BVt61tn0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=uY+Bun1/gbQKEuP1cQeuYffA6j6JqyAMkNDWVEXUspD8a/qr5Y9I1mLOkQNmMSOm5su1t8YQTm+g/56h3Mu6JciJ5Mv2SvKMlionV4le17thq8YAIYWsk8AwNFvJWEOA/90Jj52wcqmv8zWG6ZVMqmgxDrq6+SGMFk9DUuK++po= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=KEjJOXZh; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KEjJOXZh" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-45b8b8d45b3so10662545e9.1 for ; Thu, 04 Sep 2025 07:56:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756997798; x=1757602598; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:content-language:from :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=mAvtMvbpag1P1t5n4MNNRTUhp+vNJydkntuVQmj0g54=; b=KEjJOXZhtJGHKiCVFnIlIfcaaIajagQ0K1BXsGM2b1adrLGdadq/8bkXNdulXEZOoX 9YjEnwk2JwYei8kMbu4D8mt4wdZoMV1IbkVziZgJo4rWl4vtp3WidtgQL2NNbBlJLnJu H10Z0PMsuBvUxcJKVYQP5xt9/IxYdH3IxI/fUqnrV61aCjvi/OIRozT8rYhyVG6saVEN XlXUsDyVFManETZ7Q4vxnj0dWGORDoTvQKL9Akfiewnw/yG+HTQTEQms4XmPzIRqdodR /wBnJkGa4MYhll8V0V1qmcxVUKKob24zalmQG8ixgFTlYCQm80q05xKvQ1LxlXVDAFpU N0EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756997798; x=1757602598; h=content-transfer-encoding:in-reply-to:content-language:from :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=mAvtMvbpag1P1t5n4MNNRTUhp+vNJydkntuVQmj0g54=; b=fxbn+lq1CjNklVnLPwB76yxsJ7/KvIGnuQ8k0Wi8h6g7hAtiDd915/DWfF2SfuRGgh 9/pf4UycP/1vokw+baltnVsLjz0snJI1nOOUNRp6ja7FwWyn7A6sDwc42RItzuqjvOM5 5F6RTskRGvMMtVsdckK2bcSKWPLLQYrlandJUZki6u+QZPIkAGLBGc04JLLMo68VX1vg 2AkG0rRrZLf6ZCrmCRou3mYgIV6XTFcZYdw7C/zK+KXN+p+xToY4NbA7RVLRGpes7xhg ZxC3DNGQGWtFmzLXZ9F8fuqoi/IKMOUAb/gcpfZGKKRIzK0FONTcuJzO5AtyBZva2Noy oPjQ== X-Forwarded-Encrypted: i=1; AJvYcCWBBIRTxUteOJgAm6dxb1xZce3guekmMZbc7jAviDiA3zha3Ltqffv9XQOSwKP58Ev1gfB11a5T2eT4@vger.kernel.org X-Gm-Message-State: AOJu0Yx5Y+eBW6kFxhK1xwqIjjlXTvfifm3MpSwkFnsfcLPStC2HNZlr qHTEpKbQ+UcGmg2dLHLy/ndy67Wo3vGG26OrTtxIKiT7jTU8eT2d76CPx4BeZMl6uA4= X-Gm-Gg: ASbGncvGH0WkhiIqR1TGEs36vTYAIslNPdzqXrWPCitoavLbasXXlrc1jfQZdBV2DvJ +uS0POybBkowPgngSPXjsBfomoLa1Ie4JOVVOvSXA8kkhvYsoZfeRv/FzfyYRHbzziTexgPa0cg emWTa3CfTjwrI+8ka7kSFkTfTx87f1DKMflIog0wsVxQzMc2fHIwvKf/n04Ko0UmZ1YX71xkVR4 lPt0HDYnxLD8q73XvugupcdDwjPiYPnyXBZ+yfBNFpYZbTiH+0FsgZLml6zq5466utSFfepd9DH 2gTeRbzTBGOHzJ2QIZlDJZiVukAoNqwyUxvxjdhfF/fSf4dMAg9miwa/KbR0Z2v625IWs3cjio3 sXGf7qRo7+YtM6vD5kMX8SUWyz4On1ZZ966lOKNKPVEkNuWz11vKwCXSZIBJPbyAGLHiw4cjI5J LPlTv7LBAeHPZQ80wfEwU= X-Google-Smtp-Source: AGHT+IHsQzqLy0ydpxrwsgY1FqsNJlfNwe1T2aG2lvDjkIzbpWCbYkB2877CRZ3PURf2lYrkGFbnLw== X-Received: by 2002:a05:600c:c4b8:b0:45d:d403:332a with SMTP id 5b1f17b1804b1-45dd53df7e4mr5247225e9.32.1756997797960; Thu, 04 Sep 2025 07:56:37 -0700 (PDT) Received: from [192.168.0.19] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45dd3aadbcesm15507775e9.17.2025.09.04.07.56.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 07:56:37 -0700 (PDT) Message-ID: <548b3a0d-01c0-46c3-aad0-a820447f86dc@linaro.org> Date: Thu, 4 Sep 2025 15:56:33 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] arm64: dts: qcom: sc8280xp: Add OPP table for CCI hosts To: Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> <20250904-topic-cci_updates-v1-5-d38559692703@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20250904-topic-cci_updates-v1-5-d38559692703@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 04/09/2025 15:31, Konrad Dybcio wrote: > From: Konrad Dybcio > > The CCI hosts have both frequency and voltage requirements (which > happen to be common across instances on a given SoC, at least so far). > > Express them by introducing an OPP table and linking it to the hosts. > > Signed-off-by: Konrad Dybcio > --- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 18b5cb441f955f7a91204376e05536b203f3e28b..c396186317d49f411d7162771a358563329a02a4 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -391,6 +391,15 @@ memory@80000000 { > reg = <0x0 0x80000000 0x0 0x0>; > }; > > + cci_opp_table: opp-table-cci { > + compatible = "operating-points-v2"; > + > + opp-37500000 { > + opp-hz = /bits/ 64 <37500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + }; > + > cpu0_opp_table: opp-table-cpu0 { > compatible = "operating-points-v2"; > opp-shared; > @@ -4181,6 +4190,7 @@ cci0: cci@ac4a000 { > "cpas_ahb", > "cci"; > > + operating-points-v2 = <&cci_opp_table>; > power-domains = <&camcc TITAN_TOP_GDSC>; > > pinctrl-0 = <&cci0_default>; > @@ -4222,6 +4232,7 @@ cci1: cci@ac4b000 { > "cpas_ahb", > "cci"; > > + operating-points-v2 = <&cci_opp_table>; > power-domains = <&camcc TITAN_TOP_GDSC>; > > pinctrl-0 = <&cci1_default>; > @@ -4262,6 +4273,8 @@ cci2: cci@ac4c000 { > "slow_ahb_src", > "cpas_ahb", > "cci"; > + > + operating-points-v2 = <&cci_opp_table>; > power-domains = <&camcc TITAN_TOP_GDSC>; > > pinctrl-0 = <&cci2_default>; > @@ -4303,6 +4316,7 @@ cci3: cci@ac4d000 { > "cpas_ahb", > "cci"; > > + operating-points-v2 = <&cci_opp_table>; > power-domains = <&camcc TITAN_TOP_GDSC>; > > pinctrl-0 = <&cci3_default>; > Reviewed-by: Bryan O'Donoghue