[PATCH v2 00/13] sun6i: Add A31s and ir support

[PATCH v2 00/13] sun6i: Add A31s and ir support

[Hans de Goede]

Hi All,

Here is v2 of my patch series to add sun6i A31s and ir support.

Changes in v2:

-"pinctrl: sun6i: Add some missing functions, fix i2c3 muxing":
 -Drop the changes to the muxing of i2c3 this was based on                 
  "A31s Datasheet v1.40.pdf", but all other A31 related info puts them at the
  pins where we already have them, so leave this as is
-"pinctrl: sun6i: Add A31s pinctrl support"
 -Sync i2c3 muxing with v2 of "pinctrl: sun6i: Add some missing functions"
 -Add myself to the copyright header
-"clk: sunxi: Make the mod0 clk driver also a platform driver"
 -New patch in v2 of the set
-"mfd: sun6i-prcm: Add support for the ir-clk"
 -New patch in v2 of the set
-"ARM: dts: sun6i: Add sun6i-a31s.dtsi"
 -include sun6i-a31.dtsi and override the pinctrl compatible, rather then
  copying everything
-"ARM: dts: sun6i: Add ir_clk node"
 -Use allwinner,sun4i-a10-mod0-clk as compatible, rather then a prcm
  specific compatible

Please queue this up for 3.20 .

Thanks,

Hans

[PATCH v2 01/13] pinctrl: sun6i: Add some missing functions

[Hans de Goede]

While working on pinctrl for the A31s, I noticed that function 4 of
PA15 - PA18 was missing, add these.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
Changes in v2:
-Drop the changes to the muxing of i2c3 this was based on
 "A31s Datasheet v1.40.pdf", but all other A31 related info puts them at the
 pins where we already have them, so leave this as is
---
 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index f42858e..18038f0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD4 */
 		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D15 */
+		  SUNXI_FUNCTION(0x4, "clk_out_a"),
 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),	/* PA_EINT15 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD5 */
 		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D16 */
+		  SUNXI_FUNCTION(0x4, "dmic"),		/* CLK */
 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),	/* PA_EINT16 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD6 */
 		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D17 */
+		  SUNXI_FUNCTION(0x4, "dmic"),		/* DIN */
 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),	/* PA_EINT17 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD7 */
 		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D18 */
+		  SUNXI_FUNCTION(0x4, "clk_out_b"),
 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),	/* PA_EINT18 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "gmac"),		/* MDC */
 		  SUNXI_FUNCTION(0x3, "lcd1"),		/* HSYNC */
+		  SUNXI_FUNCTION(0x4, "clk_out_c"),
 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)),	/* PA_EINT26 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
-- 
2.1.0

[PATCH v2 02/13] pinctrl: sun6i: Add A31s pinctrl support

[Hans de Goede]

The A31s is a stripped down version of the A31, as such it is missing some
pins and some functions on some pins.

The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
with the missing pins and functions removed.

Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
prcm pins are identical between the A31 and the A31s.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
Changes in v2:
-Sync i2c3 muxing with v2 of "pinctrl: sun6i: Add some missing functions"
-Add myself to the copyright header
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c         | 815 +++++++++++++++++++++
 4 files changed, 821 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 93ce12e..fdd8046 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -11,6 +11,7 @@ Required properties:
   "allwinner,sun5i-a10s-pinctrl"
   "allwinner,sun5i-a13-pinctrl"
   "allwinner,sun6i-a31-pinctrl"
+  "allwinner,sun6i-a31s-pinctrl"
   "allwinner,sun6i-a31-r-pinctrl"
   "allwinner,sun7i-a20-pinctrl"
   "allwinner,sun8i-a23-pinctrl"
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 230a952..2eb893e 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
 	def_bool MACH_SUN6I
 	select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN6I_A31S
+	def_bool MACH_SUN6I
+	select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN6I_A31_R
 	def_bool MACH_SUN6I
 	depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index c7d92e4..b796d57 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10)		+= pinctrl-sun4i-a10.o
 obj-$(CONFIG_PINCTRL_SUN5I_A10S)	+= pinctrl-sun5i-a10s.o
 obj-$(CONFIG_PINCTRL_SUN5I_A13)		+= pinctrl-sun5i-a13.o
 obj-$(CONFIG_PINCTRL_SUN6I_A31)		+= pinctrl-sun6i-a31.o
+obj-$(CONFIG_PINCTRL_SUN6I_A31S)	+= pinctrl-sun6i-a31s.o
 obj-$(CONFIG_PINCTRL_SUN6I_A31_R)	+= pinctrl-sun6i-a31-r.o
 obj-$(CONFIG_PINCTRL_SUN7I_A20)		+= pinctrl-sun7i-a20.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
new file mode 100644
index 0000000..9b5a91f
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
@@ -0,0 +1,815 @@
+/*
+ * Allwinner A31s SoCs pinctrl driver.
+ *
+ * Copyright (C) 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
+ *
+ * Based on pinctrl-sun6i-a31.c, which is:
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD0 */
+		  SUNXI_FUNCTION(0x4, "uart1"),		/* DTR */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PA_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD1 */
+		  SUNXI_FUNCTION(0x4, "uart1"),		/* DSR */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PA_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD2 */
+		  SUNXI_FUNCTION(0x4, "uart1"),		/* DCD */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PA_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD3 */
+		  SUNXI_FUNCTION(0x4, "uart1"),		/* RING */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PA_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD4 */
+		  SUNXI_FUNCTION(0x4, "uart1"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PA_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD5 */
+		  SUNXI_FUNCTION(0x4, "uart1"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PA_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD6 */
+		  SUNXI_FUNCTION(0x4, "uart1"),		/* RTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PA_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD7 */
+		  SUNXI_FUNCTION(0x4, "uart1"),		/* CTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PA_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXCLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PA_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXEN */
+		  SUNXI_FUNCTION(0x4, "mmc3"),		/* CMD */
+		  SUNXI_FUNCTION(0x5, "mmc2"),		/* CMD */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PA_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* GTXCLK */
+		  SUNXI_FUNCTION(0x4, "mmc3"),		/* CLK */
+		  SUNXI_FUNCTION(0x5, "mmc2"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PA_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD0 */
+		  SUNXI_FUNCTION(0x4, "mmc3"),		/* D0 */
+		  SUNXI_FUNCTION(0x5, "mmc2"),		/* D0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PA_EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD1 */
+		  SUNXI_FUNCTION(0x4, "mmc3"),		/* D1 */
+		  SUNXI_FUNCTION(0x5, "mmc2"),		/* D1 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),	/* PA_EINT12 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD2 */
+		  SUNXI_FUNCTION(0x4, "mmc3"),		/* D2 */
+		  SUNXI_FUNCTION(0x5, "mmc2"),		/* D2 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),	/* PA_EINT13 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD3 */
+		  SUNXI_FUNCTION(0x4, "mmc3"),		/* D3 */
+		  SUNXI_FUNCTION(0x5, "mmc2"),		/* D3 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),	/* PA_EINT14 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD4 */
+		  SUNXI_FUNCTION(0x4, "clk_out_a"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),	/* PA_EINT15 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD5 */
+		  SUNXI_FUNCTION(0x4, "dmic"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),	/* PA_EINT16 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD6 */
+		  SUNXI_FUNCTION(0x4, "dmic"),		/* DIN */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),	/* PA_EINT17 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD7 */
+		  SUNXI_FUNCTION(0x4, "clk_out_b"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),	/* PA_EINT18 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXDV */
+		  SUNXI_FUNCTION(0x4, "pwm3"),		/* Positive */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),	/* PA_EINT19 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXCLK */
+		  SUNXI_FUNCTION(0x4, "pwm3"),		/* Negative */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),	/* PA_EINT20 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXERR */
+		  SUNXI_FUNCTION(0x4, "spi3"),		/* CS0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),	/* PA_EINT21 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXERR */
+		  SUNXI_FUNCTION(0x4, "spi3"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)),	/* PA_EINT22 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* COL */
+		  SUNXI_FUNCTION(0x4, "spi3"),		/* MOSI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)),	/* PA_EINT23 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* CRS */
+		  SUNXI_FUNCTION(0x4, "spi3"),		/* MISO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)),	/* PA_EINT24 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* CLKIN */
+		  SUNXI_FUNCTION(0x4, "spi3"),		/* CS1 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)),	/* PA_EINT25 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* MDC */
+		  SUNXI_FUNCTION(0x4, "clk_out_c"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)),	/* PA_EINT26 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "gmac"),		/* MDIO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)),	/* PA_EINT27 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* MCLK */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* CTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* PB_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* BCLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* PB_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* LRCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* PB_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* PB_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO1 */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* RTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* PB_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO2 */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* TX */
+		  SUNXI_FUNCTION(0x4, "i2c3"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),	/* PB_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO3 */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* RX */
+		  SUNXI_FUNCTION(0x4, "i2c3"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),	/* PB_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "i2s0"),		/* DI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),	/* PB_EINT7 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* WE */
+		  SUNXI_FUNCTION(0x3, "spi0")),		/* MOSI */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* ALE */
+		  SUNXI_FUNCTION(0x3, "spi0")),		/* MISO */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* CLE */
+		  SUNXI_FUNCTION(0x3, "spi0")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* RE */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* RB0 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* CMD */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* CMD */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* RB1 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* CLK */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ0 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D0 */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* D0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ1 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D1 */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* D1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ2 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D2 */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* D2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ3 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D3 */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* D3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ4 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D4 */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* D4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ5 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D5 */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* D5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D6 */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* D6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D7 */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* D7 */
+	/* Hole in pin numbering ! */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* RST */
+		  SUNXI_FUNCTION(0x4, "mmc3")),		/* RST */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "spi0")),		/* CS0 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D0 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D1 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D2 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D3 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D4 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D5 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D6 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VPC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D7 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VNC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D8 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D9 */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D12 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D13 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D14 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D15 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D16 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D17 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D18 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D19 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D20 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D21 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D22 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D23 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* DE */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* HSYNC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0")),		/* VSYNC */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* PCLK */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),	/* PE_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* MCLK */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* ERR */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),	/* PE_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* HSYNC */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* SYNC */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),	/* PE_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* VSYNC */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* DVLD */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),	/* PE_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D0 */
+		  SUNXI_FUNCTION(0x3, "uart5"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),	/* PE_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D1 */
+		  SUNXI_FUNCTION(0x3, "uart5"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),	/* PE_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D2 */
+		  SUNXI_FUNCTION(0x3, "uart5"),		/* RTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),	/* PE_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D3 */
+		  SUNXI_FUNCTION(0x3, "uart5"),		/* CTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),	/* PE_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D4 */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* D0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),	/* PE_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D5 */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* D1 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),	/* PE_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D6 */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* D2 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),	/* PE_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D7 */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* D3 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),	/* PE_EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D8 */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* D4 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),	/* PE_EINT12 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D9 */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* D5 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),	/* PE_EINT13 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D10 */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* D6 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),	/* PE_EINT14 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D11 */
+		  SUNXI_FUNCTION(0x3, "ts"),		/* D7 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),	/* PE_EINT15 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
+		  SUNXI_FUNCTION(0x4, "jtag")),		/* MS1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
+		  SUNXI_FUNCTION(0x4, "jtag")),		/* DI1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
+		  SUNXI_FUNCTION(0x4, "uart0")),	/* TX */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
+		  SUNXI_FUNCTION(0x4, "jtag")),		/* DO1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
+		  SUNXI_FUNCTION(0x4, "uart0")),	/* RX */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
+		  SUNXI_FUNCTION(0x4, "jtag")),		/* CK1 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),	/* PG_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),	/* PG_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),	/* PG_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D1 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),	/* PG_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D2 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),	/* PG_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D3 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),	/* PG_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),	/* PG_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),	/* PG_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),	/* PG_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),	/* PG_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c3"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)),	/* PG_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c3"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)),	/* PG_EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS1 */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* MCLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)),	/* PG_EINT12 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS0 */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* BCLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)),	/* PG_EINT13 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi1"),		/* CLK */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* LRCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)),	/* PG_EINT14 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi1"),		/* MOSI */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DIN */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)),	/* PG_EINT15 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi1"),		/* MISO */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DOUT */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)),	/* PG_EINT16 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart4"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)),	/* PG_EINT17 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart4"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)),	/* PG_EINT18 */
+	/* Hole, note H starts at pin 9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi2"),		/* CS0 */
+		  SUNXI_FUNCTION(0x3, "jtag"),		/* MS0 */
+		  SUNXI_FUNCTION(0x4, "pwm1")),		/* Positive */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi2"),		/* CLK */
+		  SUNXI_FUNCTION(0x3, "jtag"),		/* CK0 */
+		  SUNXI_FUNCTION(0x4, "pwm1")),		/* Negative */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi2"),		/* MOSI */
+		  SUNXI_FUNCTION(0x3, "jtag"),		/* DO0 */
+		  SUNXI_FUNCTION(0x4, "pwm2")),		/* Positive */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "spi2"),		/* MISO */
+		  SUNXI_FUNCTION(0x3, "jtag"),		/* DI0 */
+		  SUNXI_FUNCTION(0x4, "pwm2")),		/* Negative */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "pwm0")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c0")),		/* SCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c0")),		/* SDA */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c1")),		/* SCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c1")),		/* SDA */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c2")),		/* SCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c2")),		/* SDA */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart0")),	/* TX */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart0")),	/* RX */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+};
+
+static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = {
+	.pins = sun6i_a31s_pins,
+	.npins = ARRAY_SIZE(sun6i_a31s_pins),
+	.irq_banks = 4,
+};
+
+static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_init(pdev,
+				  &sun6i_a31s_pinctrl_data);
+}
+
+static struct of_device_id sun6i_a31s_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun6i-a31s-pinctrl", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match);
+
+static struct platform_driver sun6i_a31s_pinctrl_driver = {
+	.probe	= sun6i_a31s_pinctrl_probe,
+	.driver	= {
+		.name		= "sun6i-a31s-pinctrl",
+		.owner		= THIS_MODULE,
+		.of_match_table	= sun6i_a31s_pinctrl_match,
+	},
+};
+module_platform_driver(sun6i_a31s_pinctrl_driver);
+
+MODULE_AUTHOR("Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("Allwinner A31s pinctrl driver");
+MODULE_LICENSE("GPL");
-- 
2.1.0

[PATCH v2 03/13] ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi

[Hans de Goede]

So far the A31s is 100% compatible with the A31, still lets do the same
as what we've done for the A13 / A10s and give it its own compatible string,
in case we need to differentiate later.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 Documentation/arm/sunxi/README | 1 -
 arch/arm/mach-sunxi/platsmp.c  | 3 ++-
 arch/arm/mach-sunxi/sunxi.c    | 1 +
 drivers/clk/sunxi/clk-sunxi.c  | 1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index e68d163..1fe2d7f 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -50,7 +50,6 @@ SunXi family
           http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20user%20manual%20V1.1%2020130630.pdf
 
       - Allwinner A31s (sun6i)
-        + Not Supported
         + Datasheet
           http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20datasheet%20V1.3%2020131106.pdf
         + User Manual
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index e44d028..b1b5b7c 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -120,4 +120,5 @@ static struct smp_operations sun6i_smp_ops __initdata = {
 	.smp_prepare_cpus	= sun6i_smp_prepare_cpus,
 	.smp_boot_secondary	= sun6i_smp_boot_secondary,
 };
-CPU_METHOD_OF_DECLARE(sun6i_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun6i_a31s_smp, "allwinner,sun6i-a31s", &sun6i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 1f98675..d4bb239 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -29,6 +29,7 @@ MACHINE_END
 
 static const char * const sun6i_board_dt_compat[] = {
 	"allwinner,sun6i-a31",
+	"allwinner,sun6i-a31s",
 	NULL,
 };
 
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index a9d10b9..ee9d7f2 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1235,6 +1235,7 @@ static void __init sun6i_init_clocks(struct device_node *node)
 			  ARRAY_SIZE(sun6i_critical_clocks));
 }
 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
+CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
 
 static void __init sun9i_init_clocks(struct device_node *node)
-- 
2.1.0

[PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller

[Hans de Goede]

On sun6i the cir block is attached to the reset controller, add support
for de-asserting the reset if a reset controller is specified in dt.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
 drivers/media/rc/sunxi-cir.c                       | 25 ++++++++++++++++++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 23dd5ad..6b70b9b 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -10,6 +10,7 @@ Required properties:
 
 Optional properties:
 - linux,rc-map-name : Remote control map name.
+- resets : phandle + reset specifier pair
 
 Example:
 
@@ -17,6 +18,7 @@ ir0: ir@01c21800 {
 	compatible = "allwinner,sun4i-a10-ir";
 	clocks = <&apb0_gates 6>, <&ir0_clk>;
 	clock-names = "apb", "ir";
+	resets = <&apb0_rst 1>;
 	interrupts = <0 5 1>;
 	reg = <0x01C21800 0x40>;
 	linux,rc-map-name = "rc-rc6-mce";
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 340f7f5..06170e0 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -23,6 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/of_platform.h>
+#include <linux/reset.h>
 #include <media/rc-core.h>
 
 #define SUNXI_IR_DEV "sunxi-ir"
@@ -95,6 +96,7 @@ struct sunxi_ir {
 	int             irq;
 	struct clk      *clk;
 	struct clk      *apb_clk;
+	struct reset_control *rst;
 	const char      *map_name;
 };
 
@@ -166,15 +168,29 @@ static int sunxi_ir_probe(struct platform_device *pdev)
 		return PTR_ERR(ir->clk);
 	}
 
+	/* Reset (optional) */
+	ir->rst = devm_reset_control_get_optional(dev, NULL);
+	if (IS_ERR(ir->rst)) {
+		ret = PTR_ERR(ir->rst);
+		if (ret == -EPROBE_DEFER)
+			return ret;
+		ir->rst = NULL;
+	} else {
+		ret = reset_control_deassert(ir->rst);
+		if (ret)
+			return ret;
+	}
+
 	ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
 	if (ret) {
 		dev_err(dev, "set ir base clock failed!\n");
-		return ret;
+		goto exit_reset_assert;
 	}
 
 	if (clk_prepare_enable(ir->apb_clk)) {
 		dev_err(dev, "try to enable apb_ir_clk failed\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		goto exit_reset_assert;
 	}
 
 	if (clk_prepare_enable(ir->clk)) {
@@ -271,6 +287,9 @@ exit_clkdisable_clk:
 	clk_disable_unprepare(ir->clk);
 exit_clkdisable_apb_clk:
 	clk_disable_unprepare(ir->apb_clk);
+exit_reset_assert:
+	if (ir->rst)
+		reset_control_assert(ir->rst);
 
 	return ret;
 }
@@ -282,6 +301,8 @@ static int sunxi_ir_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(ir->clk);
 	clk_disable_unprepare(ir->apb_clk);
+	if (ir->rst)
+		reset_control_assert(ir->rst);
 
 	spin_lock_irqsave(&ir->ir_lock, flags);
 	/* disable IR IRQ */
-- 
2.1.0

[PATCH v2 05/13] rc: sunxi-cir: Add support for the larger fifo found on sun5i and sun6i

[Hans de Goede]

Add support for the larger fifo found on sun5i and sun6i, having a separate
compatible for the ir found on sun5i & sun6i also is useful if we ever want
to add ir transmit support, because the sun5i & sun6i version do not have
transmit support.

Note this commits also adds checking for the end-of-packet interrupt flag
(which was already enabled), as the fifo-data-available interrupt flag only
gets set when the trigger-level is exceeded. So far we've been getting away
with not doing this because of the low trigger-level, but this is something
which we should have done since day one.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 .../devicetree/bindings/media/sunxi-ir.txt          |  2 +-
 drivers/media/rc/sunxi-cir.c                        | 21 ++++++++++++---------
 2 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 6b70b9b..1811a06 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -1,7 +1,7 @@
 Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
 
 Required properties:
-- compatible	    : should be "allwinner,sun4i-a10-ir";
+- compatible	    : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
 - clocks	    : list of clock specifiers, corresponding to
 		      entries in clock-names property;
 - clock-names	    : should contain "apb" and "ir" entries;
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 06170e0..7830aef 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -56,12 +56,12 @@
 #define REG_RXINT_RAI_EN		BIT(4)
 
 /* Rx FIFO available byte level */
-#define REG_RXINT_RAL(val)    (((val) << 8) & (GENMASK(11, 8)))
+#define REG_RXINT_RAL(val)    ((val) << 8)
 
 /* Rx Interrupt Status */
 #define SUNXI_IR_RXSTA_REG    0x30
 /* RX FIFO Get Available Counter */
-#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (GENMASK(5, 0)))
+#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
 /* Clear all interrupt status value */
 #define REG_RXSTA_CLEARALL    0xff
 
@@ -72,10 +72,6 @@
 /* CIR_REG register idle threshold */
 #define REG_CIR_ITHR(val)    (((val) << 8) & (GENMASK(15, 8)))
 
-/* Hardware supported fifo size */
-#define SUNXI_IR_FIFO_SIZE    16
-/* How many messages in FIFO trigger IRQ */
-#define TRIGGER_LEVEL         8
 /* Required frequency for IR0 or IR1 clock in CIR mode */
 #define SUNXI_IR_BASE_CLK     8000000
 /* Frequency after IR internal divider  */
@@ -94,6 +90,7 @@ struct sunxi_ir {
 	struct rc_dev   *rc;
 	void __iomem    *base;
 	int             irq;
+	int		fifo_size;
 	struct clk      *clk;
 	struct clk      *apb_clk;
 	struct reset_control *rst;
@@ -115,11 +112,11 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
 	/* clean all pending statuses */
 	writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
 
-	if (status & REG_RXINT_RAI_EN) {
+	if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
 		/* How many messages in fifo */
 		rc  = REG_RXSTA_GET_AC(status);
 		/* Sanity check */
-		rc = rc > SUNXI_IR_FIFO_SIZE ? SUNXI_IR_FIFO_SIZE : rc;
+		rc = rc > ir->fifo_size ? ir->fifo_size : rc;
 		/* If we have data */
 		for (cnt = 0; cnt < rc; cnt++) {
 			/* for each bit in fifo */
@@ -156,6 +153,11 @@ static int sunxi_ir_probe(struct platform_device *pdev)
 	if (!ir)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
+		ir->fifo_size = 64;
+	else
+		ir->fifo_size = 16;
+
 	/* Clock */
 	ir->apb_clk = devm_clk_get(dev, "apb");
 	if (IS_ERR(ir->apb_clk)) {
@@ -271,7 +273,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
 	 * level
 	 */
 	writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
-	       REG_RXINT_RAI_EN | REG_RXINT_RAL(TRIGGER_LEVEL - 1),
+	       REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
 	       ir->base + SUNXI_IR_RXINT_REG);
 
 	/* Enable IR Module */
@@ -319,6 +321,7 @@ static int sunxi_ir_remove(struct platform_device *pdev)
 
 static const struct of_device_id sunxi_ir_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-ir", },
+	{ .compatible = "allwinner,sun5i-a13-ir", },
 	{},
 };
 
-- 
2.1.0

[PATCH v2 06/13] clk: sunxi: Make the mod0 clk driver also a platform driver

[Hans de Goede]

With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
through the mfd framework, and as such do not work with of_clk_declare, since
they do not have registers assigned to them yet at of_clk_declare init time.

Silence the error on not finding registers in the of_clk_declare mod0 clk
setup method, and also register mod0-clk support as a platform driver to work
properly with mfd instantiated mod0 clocks.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/sunxi/clk-mod0.c | 41 ++++++++++++++++++++++++++++++++++++-----
 1 file changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 658d74f..7ddab6f 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -17,6 +17,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/of_address.h>
+#include <linux/platform_device.h>
 
 #include "clk-factors.h"
 
@@ -67,7 +68,7 @@ static struct clk_factors_config sun4i_a10_mod0_config = {
 	.pwidth = 2,
 };
 
-static const struct factors_data sun4i_a10_mod0_data __initconst = {
+static const struct factors_data sun4i_a10_mod0_data = {
 	.enable = 31,
 	.mux = 24,
 	.muxmask = BIT(1) | BIT(0),
@@ -82,17 +83,47 @@ static void __init sun4i_a10_mod0_setup(struct device_node *node)
 	void __iomem *reg;
 
 	reg = of_iomap(node, 0);
-	if (!reg) {
-		pr_err("Could not get registers for mod0-clk: %s\n",
-		       node->name);
+	if (!reg)
 		return;
-	}
 
 	sunxi_factors_register(node, &sun4i_a10_mod0_data,
 			       &sun4i_a10_mod0_lock, reg);
 }
 CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
 
+static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *r;
+	void __iomem *reg;
+
+	if (!np)
+		return -ENODEV;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	reg = devm_ioremap_resource(&pdev->dev, r);
+	if (IS_ERR(reg))
+		return PTR_ERR(reg);
+
+	sunxi_factors_register(np, &sun4i_a10_mod0_data,
+			       &sun4i_a10_mod0_lock, reg);
+	return 0;
+}
+
+static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = {
+	{ .compatible = "allwinner,sun4i-a10-mod0-clk" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver sun4i_a10_mod0_clk_driver = {
+	.driver = {
+		.name = "sun4i-a10-mod0-clk",
+		.of_match_table = sun4i_a10_mod0_clk_dt_ids,
+	},
+	.probe = sun4i_a10_mod0_clk_probe,
+};
+module_platform_driver(sun4i_a10_mod0_clk_driver);
+
 static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
 
 static void __init sun5i_a13_mbus_setup(struct device_node *node)
-- 
2.1.0

[PATCH v2 07/13] mfd: sun6i-prcm: Add support for the ir-clk

[Hans de Goede]

Add support for the ir-clk which is part of the sun6i SoC prcm module.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 drivers/mfd/sun6i-prcm.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
index 2f2e9f0..1911731 100644
--- a/drivers/mfd/sun6i-prcm.c
+++ b/drivers/mfd/sun6i-prcm.c
@@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
 	},
 };
 
+static const struct resource sun6i_a31_ir_clk_res[] = {
+	{
+		.start = 0x54,
+		.end = 0x57,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
 static const struct resource sun6i_a31_apb0_rstc_res[] = {
 	{
 		.start = 0xb0,
@@ -69,6 +77,12 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
 		.resources = sun6i_a31_apb0_gates_clk_res,
 	},
 	{
+		.name = "sun6i-a31-ir-clk",
+		.of_compatible = "allwinner,sun4i-a10-mod0-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
+		.resources = sun6i_a31_ir_clk_res,
+	},
+	{
 		.name = "sun6i-a31-apb0-clock-reset",
 		.of_compatible = "allwinner,sun6i-a31-clock-reset",
 		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
-- 
2.1.0

[PATCH v2 08/13] ARM: dts: sun6i: Add ir_clk node

[Hans de Goede]

Add an ir_clk sub-node to the prcm node.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
Changes in v2:
-Use allwinner,sun4i-a10-mod0-clk as compatible, rather then a prcm specific
 compatible
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index f47156b..1c1d255 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -878,6 +878,13 @@
 						"apb0_i2c";
 			};
 
+			ir_clk: ir_clk {
+				#clock-cells = <0>;
+				compatible = "allwinner,sun4i-a10-mod0-clk";
+				clocks = <&osc32k>, <&osc24M>;
+				clock-output-names = "ir";
+			};
+
 			apb0_rst: apb0_rst {
 				compatible = "allwinner,sun6i-a31-clock-reset";
 				#reset-cells = <1>;
-- 
2.1.0

[PATCH v2 09/13] ARM: dts: sun6i: Add ir node

[Hans de Goede]

Add a node for the ir receiver found on the A31.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 1c1d255..85c6365 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -896,6 +896,16 @@
 			reg = <0x01f01c00 0x300>;
 		};
 
+		ir@01f02000 {
+			compatible = "allwinner,sun5i-a13-ir";
+			clocks = <&apb0_gates 1>, <&ir_clk>;
+			clock-names = "apb", "ir";
+			resets = <&apb0_rst 1>;
+			interrupts = <0 37 4>;
+			reg = <0x01f02000 0x40>;
+			status = "disabled";
+		};
+
 		r_pio: pinctrl@01f02c00 {
 			compatible = "allwinner,sun6i-a31-r-pinctrl";
 			reg = <0x01f02c00 0x400>;
-- 
2.1.0

[PATCH v2 10/13] ARM: dts: sun6i: Add pinmux settings for the ir pins

[Hans de Goede]

Add pinmux settings for the ir receive pin of the A31.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 85c6365..9e9504c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -918,6 +918,13 @@
 			#interrupt-cells = <2>;
 			#size-cells = <0>;
 			#gpio-cells = <3>;
+
+			ir_pins_a: ir@0 {
+				allwinner,pins = "PL4";
+				allwinner,function = "s_ir";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 	};
 };
-- 
2.1.0

[PATCH v2 11/13] ARM: dts: sun6i: Enable ir receiver on the Mele M9

[Hans de Goede]

The Mele M9 has an ir receiver, enable it.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/sun6i-a31-m9.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 3ab544f..fccf709 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -121,6 +121,12 @@
 				reg = <1>;
 			};
 		};
+
+		ir@01f02000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&ir_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
2.1.0

[PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi

[Hans de Goede]

Add a dtsi file for A31s based boards.

Since the  A31s is the same die as the A31 in a different package, this dtsi
simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to
reflect the different package, everything else is identical.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
Changes in v2:
-include sun6i-a31.dtsi and override the pinctrl compatible, rather then
 copying everything
---
 arch/arm/boot/dts/sun6i-a31s.dtsi | 62 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi

diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
new file mode 100644
index 0000000..d0bd2b9
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The A31s is the same die as the A31 in a different package, this is
+ * reflected by it having different pinctrl compatible everything else is
+ * identical.
+ */
+
+/include/ "sun6i-a31.dtsi"
+
+/ {
+	soc@01c00000 {
+		pio: pinctrl@01c20800 {
+			compatible = "allwinner,sun6i-a31s-pinctrl";
+		};
+	};
+};
-- 
2.1.0

[PATCH v2 13/13] ARM: dts: sun6i: Add dts file for CSQ CS908 board

[Hans de Goede]

The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
controller), ethernet, 3.5 mm jack with a/v out and hdmi out.

Note it has no sdcard slot and therefore can only be fel booted.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/Makefile             |   3 +-
 arch/arm/boot/dts/sun6i-a31s-cs908.dts | 109 +++++++++++++++++++++++++++++++++
 2 files changed, 111 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun6i-a31s-cs908.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bc58ac3..28506ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -459,7 +459,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
 	sun6i-a31-app4-evb1.dtb \
 	sun6i-a31-colombus.dtb \
 	sun6i-a31-hummingbird.dtb \
-	sun6i-a31-m9.dtb
+	sun6i-a31-m9.dtb \
+	sun6i-a31s-cs908.dtb
 dtb-$(CONFIG_MACH_SUN7I) += \
 	sun7i-a20-bananapi.dtb \
 	sun7i-a20-cubieboard2.dtb \
diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
new file mode 100644
index 0000000..48d3a70
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun6i-a31s.dtsi"
+
+/ {
+	model = "CSQ CS908 top set box";
+	compatible = "csq,cs908", "allwinner,sun6i-a31s";
+
+	chosen {
+		bootargs = "earlyprintk console=ttyS0,115200";
+	};
+
+	soc@01c00000 {
+		usbphy: phy@01c19400 {
+			status = "okay";
+		};
+
+		ehci0: usb@01c1a000 {
+			status = "okay";
+		};
+
+		ehci1: usb@01c1b000 {
+			status = "okay";
+		};
+
+		ohci1: usb@01c1b400 {
+			status = "okay";
+		};
+
+		pio: pinctrl@01c20800 {
+			usb1_vbus_pin_csq908: usb1_vbus_pin@0 {
+				allwinner,pins = "PC27";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+		};
+
+		uart0: serial@01c28000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins_a>;
+			status = "okay";
+		};
+
+		gmac: ethernet@01c30000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&gmac_pins_mii_a>;
+			phy = <&phy1>;
+			phy-mode = "mii";
+			status = "okay";
+
+			phy1: ethernet-phy@1 {
+				reg = <1>;
+			};
+		};
+
+		ir@01f02000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&ir_pins_a>;
+			status = "okay";
+		};
+	};
+};
-- 
2.1.0

Re: [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller

[Chen-Yu Tsai]

Hi,

On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
> On sun6i the cir block is attached to the reset controller, add support
> for de-asserting the reset if a reset controller is specified in dt.
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
>  .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
>  drivers/media/rc/sunxi-cir.c                       | 25 ++++++++++++++++++++--
>  2 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
> index 23dd5ad..6b70b9b 100644
> --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
> +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
> @@ -10,6 +10,7 @@ Required properties:
>
>  Optional properties:
>  - linux,rc-map-name : Remote control map name.
> +- resets : phandle + reset specifier pair

Should it be optional? Or should we use a sun6i compatible with
a mandatory reset phandle? I mean, the driver/hardware is not
going to work with the reset missing on sun6i.

Seems we are doing it one way for some of our drivers, and
the other (optional) way for more generic ones, like USB.

ChenYu

>  Example:
>
> @@ -17,6 +18,7 @@ ir0: ir@01c21800 {
>         compatible = "allwinner,sun4i-a10-ir";
>         clocks = <&apb0_gates 6>, <&ir0_clk>;
>         clock-names = "apb", "ir";
> +       resets = <&apb0_rst 1>;
>         interrupts = <0 5 1>;
>         reg = <0x01C21800 0x40>;
>         linux,rc-map-name = "rc-rc6-mce";
> diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> index 340f7f5..06170e0 100644
> --- a/drivers/media/rc/sunxi-cir.c
> +++ b/drivers/media/rc/sunxi-cir.c
> @@ -23,6 +23,7 @@
>  #include <linux/interrupt.h>
>  #include <linux/module.h>
>  #include <linux/of_platform.h>
> +#include <linux/reset.h>
>  #include <media/rc-core.h>
>
>  #define SUNXI_IR_DEV "sunxi-ir"
> @@ -95,6 +96,7 @@ struct sunxi_ir {
>         int             irq;
>         struct clk      *clk;
>         struct clk      *apb_clk;
> +       struct reset_control *rst;
>         const char      *map_name;
>  };
>
> @@ -166,15 +168,29 @@ static int sunxi_ir_probe(struct platform_device *pdev)
>                 return PTR_ERR(ir->clk);
>         }
>
> +       /* Reset (optional) */
> +       ir->rst = devm_reset_control_get_optional(dev, NULL);
> +       if (IS_ERR(ir->rst)) {
> +               ret = PTR_ERR(ir->rst);
> +               if (ret == -EPROBE_DEFER)
> +                       return ret;
> +               ir->rst = NULL;
> +       } else {
> +               ret = reset_control_deassert(ir->rst);
> +               if (ret)
> +                       return ret;
> +       }
> +
>         ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
>         if (ret) {
>                 dev_err(dev, "set ir base clock failed!\n");
> -               return ret;
> +               goto exit_reset_assert;
>         }
>
>         if (clk_prepare_enable(ir->apb_clk)) {
>                 dev_err(dev, "try to enable apb_ir_clk failed\n");
> -               return -EINVAL;
> +               ret = -EINVAL;
> +               goto exit_reset_assert;
>         }
>
>         if (clk_prepare_enable(ir->clk)) {
> @@ -271,6 +287,9 @@ exit_clkdisable_clk:
>         clk_disable_unprepare(ir->clk);
>  exit_clkdisable_apb_clk:
>         clk_disable_unprepare(ir->apb_clk);
> +exit_reset_assert:
> +       if (ir->rst)
> +               reset_control_assert(ir->rst);
>
>         return ret;
>  }
> @@ -282,6 +301,8 @@ static int sunxi_ir_remove(struct platform_device *pdev)
>
>         clk_disable_unprepare(ir->clk);
>         clk_disable_unprepare(ir->apb_clk);
> +       if (ir->rst)
> +               reset_control_assert(ir->rst);
>
>         spin_lock_irqsave(&ir->ir_lock, flags);
>         /* disable IR IRQ */
> --
> 2.1.0
>
> --
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Re: [PATCH v2 07/13] mfd: sun6i-prcm: Add support for the ir-clk

[Lee Jones]

On Wed, 17 Dec 2014, Hans de Goede wrote:

> Add support for the ir-clk which is part of the sun6i SoC prcm module.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
>  drivers/mfd/sun6i-prcm.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)

Pretty standard stuff (

> diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
> index 2f2e9f0..1911731 100644
> --- a/drivers/mfd/sun6i-prcm.c
> +++ b/drivers/mfd/sun6i-prcm.c
> @@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
>  	},
>  };
>  
> +static const struct resource sun6i_a31_ir_clk_res[] = {
> +	{
> +		.start = 0x54,
> +		.end = 0x57,
> +		.flags = IORESOURCE_MEM,
> +	},
> +};

I'm still unkeen on this registers not being defined -- but whateveer!

>  static const struct resource sun6i_a31_apb0_rstc_res[] = {
>  	{
>  		.start = 0xb0,
> @@ -69,6 +77,12 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
>  		.resources = sun6i_a31_apb0_gates_clk_res,
>  	},
>  	{
> +		.name = "sun6i-a31-ir-clk",
> +		.of_compatible = "allwinner,sun4i-a10-mod0-clk",
> +		.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
> +		.resources = sun6i_a31_ir_clk_res,
> +	},
> +	{
>  		.name = "sun6i-a31-apb0-clock-reset",
>  		.of_compatible = "allwinner,sun6i-a31-clock-reset",
>  		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),

This is all pretty standard stuff:

For my own reference:

Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Do you do  you expect this patch to be handled?

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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Re: [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller

[Hans de Goede]

Hi,

On 18-12-14 03:48, Chen-Yu Tsai wrote:
> Hi,
>
> On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
>> On sun6i the cir block is attached to the reset controller, add support
>> for de-asserting the reset if a reset controller is specified in dt.
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
>> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> ---
>>   .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
>>   drivers/media/rc/sunxi-cir.c                       | 25 ++++++++++++++++++++--
>>   2 files changed, 25 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>> index 23dd5ad..6b70b9b 100644
>> --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
>> +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>> @@ -10,6 +10,7 @@ Required properties:
>>
>>   Optional properties:
>>   - linux,rc-map-name : Remote control map name.
>> +- resets : phandle + reset specifier pair
>
> Should it be optional? Or should we use a sun6i compatible with
> a mandatory reset phandle? I mean, the driver/hardware is not
> going to work with the reset missing on sun6i.
>
> Seems we are doing it one way for some of our drivers, and
> the other (optional) way for more generic ones, like USB.

I do not believe that we should add a new compatible just because
the reset line of a block is hooked up differently. It is the
exact same ip-block. Only now the reset is not controlled
through the apb-gate, but controlled separately.

Regards,

Hans

Re: [PATCH v2 07/13] mfd: sun6i-prcm: Add support for the ir-clk

[Hans de Goede]

Hi,

On 18-12-14 09:41, Lee Jones wrote:
> On Wed, 17 Dec 2014, Hans de Goede wrote:
>
>> Add support for the ir-clk which is part of the sun6i SoC prcm module.
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>>   drivers/mfd/sun6i-prcm.c | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>
> Pretty standard stuff (
>
>> diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
>> index 2f2e9f0..1911731 100644
>> --- a/drivers/mfd/sun6i-prcm.c
>> +++ b/drivers/mfd/sun6i-prcm.c
>> @@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
>>   	},
>>   };
>>
>> +static const struct resource sun6i_a31_ir_clk_res[] = {
>> +	{
>> +		.start = 0x54,
>> +		.end = 0x57,
>> +		.flags = IORESOURCE_MEM,
>> +	},
>> +};
>
> I'm still unkeen on this registers not being defined -- but whateveer!
>
>>   static const struct resource sun6i_a31_apb0_rstc_res[] = {
>>   	{
>>   		.start = 0xb0,
>> @@ -69,6 +77,12 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
>>   		.resources = sun6i_a31_apb0_gates_clk_res,
>>   	},
>>   	{
>> +		.name = "sun6i-a31-ir-clk",
>> +		.of_compatible = "allwinner,sun4i-a10-mod0-clk",
>> +		.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
>> +		.resources = sun6i_a31_ir_clk_res,
>> +	},
>> +	{
>>   		.name = "sun6i-a31-apb0-clock-reset",
>>   		.of_compatible = "allwinner,sun6i-a31-clock-reset",
>>   		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
>
> This is all pretty standard stuff:
>
> For my own reference:
>
> Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> Do you do  you expect this patch to be handled?

I've no preference for how this goes upstream. There are no compile time deps
and runtime the ir will not work (but not explode) until all the bits are
in place.

Regards,

Hans


>

Re: [PATCH v2 07/13] mfd: sun6i-prcm: Add support for the ir-clk

[Lee Jones]

On Thu, 18 Dec 2014, Hans de Goede wrote:

> Hi,
> 
> On 18-12-14 09:41, Lee Jones wrote:
> >On Wed, 17 Dec 2014, Hans de Goede wrote:
> >
> >>Add support for the ir-clk which is part of the sun6i SoC prcm module.
> >>
> >>Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>---
> >>  drivers/mfd/sun6i-prcm.c | 14 ++++++++++++++
> >>  1 file changed, 14 insertions(+)
> >
> >Pretty standard stuff (
> >
> >>diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
> >>index 2f2e9f0..1911731 100644
> >>--- a/drivers/mfd/sun6i-prcm.c
> >>+++ b/drivers/mfd/sun6i-prcm.c
> >>@@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
> >>  	},
> >>  };
> >>
> >>+static const struct resource sun6i_a31_ir_clk_res[] = {
> >>+	{
> >>+		.start = 0x54,
> >>+		.end = 0x57,
> >>+		.flags = IORESOURCE_MEM,
> >>+	},
> >>+};
> >
> >I'm still unkeen on this registers not being defined -- but whateveer!
> >
> >>  static const struct resource sun6i_a31_apb0_rstc_res[] = {
> >>  	{
> >>  		.start = 0xb0,
> >>@@ -69,6 +77,12 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
> >>  		.resources = sun6i_a31_apb0_gates_clk_res,
> >>  	},
> >>  	{
> >>+		.name = "sun6i-a31-ir-clk",
> >>+		.of_compatible = "allwinner,sun4i-a10-mod0-clk",
> >>+		.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
> >>+		.resources = sun6i_a31_ir_clk_res,
> >>+	},
> >>+	{
> >>  		.name = "sun6i-a31-apb0-clock-reset",
> >>  		.of_compatible = "allwinner,sun6i-a31-clock-reset",
> >>  		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
> >
> >This is all pretty standard stuff:
> >
> >For my own reference:
> >
> >Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >
> >Do you do  you expect this patch to be handled?
> 
> I've no preference for how this goes upstream. There are no compile time deps
> and runtime the ir will not work (but not explode) until all the bits are
> in place.

Great, this is my kind of patch.  Applied, thanks.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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Re: [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2676 bytes --]

Hi,

On Thu, Dec 18, 2014 at 09:50:26AM +0100, Hans de Goede wrote:
> Hi,
> 
> On 18-12-14 03:48, Chen-Yu Tsai wrote:
> >Hi,
> >
> >On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
> >>On sun6i the cir block is attached to the reset controller, add support
> >>for de-asserting the reset if a reset controller is specified in dt.
> >>
> >>Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
> >>Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >>---
> >>  .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
> >>  drivers/media/rc/sunxi-cir.c                       | 25 ++++++++++++++++++++--
> >>  2 files changed, 25 insertions(+), 2 deletions(-)
> >>
> >>diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
> >>index 23dd5ad..6b70b9b 100644
> >>--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
> >>+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
> >>@@ -10,6 +10,7 @@ Required properties:
> >>
> >>  Optional properties:
> >>  - linux,rc-map-name : Remote control map name.
> >>+- resets : phandle + reset specifier pair
> >
> >Should it be optional? Or should we use a sun6i compatible with
> >a mandatory reset phandle? I mean, the driver/hardware is not
> >going to work with the reset missing on sun6i.
> >
> >Seems we are doing it one way for some of our drivers, and
> >the other (optional) way for more generic ones, like USB.
> 
> I do not believe that we should add a new compatible just because
> the reset line of a block is hooked up differently. It is the
> exact same ip-block. Only now the reset is not controlled
> through the apb-gate, but controlled separately.

He has a point though. Your driver might very well probe nicely and
everything, but still wouldn't be functional at all because the reset
line wouldn't have been specified in the DT.

The easiest way to deal with that would be in the bindings doc to
update it with a compatible for the A31, and mentionning that the
reset property is mandatory there.

Note that the code itself might not change at all though. I'd just
like to avoid any potential breaking of the DT bindings themselves. If
we further want to refine the code, we can do that however we want.

I have a slight preference for a clean error if reset is missing, but
I won't get in the way just for that.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 01/13] pinctrl: sun6i: Add some missing functions

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 462 bytes --]

On Wed, Dec 17, 2014 at 06:18:12PM +0100, Hans de Goede wrote:
> While working on pinctrl for the A31s, I noticed that function 4 of
> PA15 - PA18 was missing, add these.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>

Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 02/13] pinctrl: sun6i: Add A31s pinctrl support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 925 bytes --]

On Wed, Dec 17, 2014 at 06:18:13PM +0100, Hans de Goede wrote:
> The A31s is a stripped down version of the A31, as such it is missing some
> pins and some functions on some pins.
> 
> The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c

I guess you meant pinctrl-sun6i-a31.c for the second one, right?

> with the missing pins and functions removed.
> 
> Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
> prcm pins are identical between the A31 and the A31s.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>

Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

We should probably refactor it at some point like mvebu does though to
deal with similar pin sets like this and the A31.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 03/13] ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 476 bytes --]

On Wed, Dec 17, 2014 at 06:18:14PM +0100, Hans de Goede wrote:
> So far the A31s is 100% compatible with the A31, still lets do the same
> as what we've done for the A13 / A10s and give it its own compatible string,
> in case we need to differentiate later.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 06/13] clk: sunxi: Make the mod0 clk driver also a platform driver

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1905 bytes --]

Hi,

On Wed, Dec 17, 2014 at 06:18:17PM +0100, Hans de Goede wrote:
> With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
> through the mfd framework, and as such do not work with of_clk_declare, since
> they do not have registers assigned to them yet at of_clk_declare init time.
> 
> Silence the error on not finding registers in the of_clk_declare mod0 clk
> setup method, and also register mod0-clk support as a platform driver to work
> properly with mfd instantiated mod0 clocks.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
>  drivers/clk/sunxi/clk-mod0.c | 41 ++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 36 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
> index 658d74f..7ddab6f 100644
> --- a/drivers/clk/sunxi/clk-mod0.c
> +++ b/drivers/clk/sunxi/clk-mod0.c
> @@ -17,6 +17,7 @@
>  #include <linux/clk-provider.h>
>  #include <linux/clkdev.h>
>  #include <linux/of_address.h>
> +#include <linux/platform_device.h>
>  
>  #include "clk-factors.h"
>  
> @@ -67,7 +68,7 @@ static struct clk_factors_config sun4i_a10_mod0_config = {
>  	.pwidth = 2,
>  };
>  
> -static const struct factors_data sun4i_a10_mod0_data __initconst = {
> +static const struct factors_data sun4i_a10_mod0_data = {
>  	.enable = 31,
>  	.mux = 24,
>  	.muxmask = BIT(1) | BIT(0),
> @@ -82,17 +83,47 @@ static void __init sun4i_a10_mod0_setup(struct device_node *node)
>  	void __iomem *reg;
>  
>  	reg = of_iomap(node, 0);
> -	if (!reg) {
> -		pr_err("Could not get registers for mod0-clk: %s\n",
> -		       node->name);
> +	if (!reg)
>  		return;
> -	}

A comment here would be nice to mention that this is intentional.

It looks good otherwise, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 08/13] ARM: dts: sun6i: Add ir_clk node

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 324 bytes --]

On Wed, Dec 17, 2014 at 06:18:19PM +0100, Hans de Goede wrote:
> Add an ir_clk sub-node to the prcm node.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 09/13] ARM: dts: sun6i: Add ir node

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 332 bytes --]

On Wed, Dec 17, 2014 at 06:18:20PM +0100, Hans de Goede wrote:
> Add a node for the ir receiver found on the A31.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 11/13] ARM: dts: sun6i: Enable ir receiver on the Mele M9

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 326 bytes --]

On Wed, Dec 17, 2014 at 06:18:22PM +0100, Hans de Goede wrote:
> The Mele M9 has an ir receiver, enable it.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 4174 bytes --]

On Wed, Dec 17, 2014 at 06:18:23PM +0100, Hans de Goede wrote:
> Add a dtsi file for A31s based boards.
> 
> Since the  A31s is the same die as the A31 in a different package, this dtsi
> simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to
> reflect the different package, everything else is identical.
> 
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> Changes in v2:
> -include sun6i-a31.dtsi and override the pinctrl compatible, rather then
>  copying everything
> ---
>  arch/arm/boot/dts/sun6i-a31s.dtsi | 62 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
> new file mode 100644
> index 0000000..d0bd2b9
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
> @@ -0,0 +1,62 @@
> +/*
> + * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + *     You should have received a copy of the GNU General Public
> + *     License along with this library; if not, write to the Free
> + *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> + *     MA 02110-1301 USA
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/*
> + * The A31s is the same die as the A31 in a different package, this is
> + * reflected by it having different pinctrl compatible everything else is
> + * identical.
> + */
> +
> +/include/ "sun6i-a31.dtsi"
> +
> +/ {
> +	soc@01c00000 {
> +		pio: pinctrl@01c20800 {
> +			compatible = "allwinner,sun6i-a31s-pinctrl";
> +		};
> +	};
> +};

Given your previous changes, you should also update the enable-method.

Also, for this patch and the next one, Arnd just warned me that we
shouldn't duplicate the DT path, and that we should switch to the new
trend on using label references (like what TI or Amlogic does for
example).

I'll take care on converting the existing users, but could you repost
these patches with this ?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller

[Hans de Goede]

Hi,

On 19-12-14 19:17, Maxime Ripard wrote:
> Hi,
>
> On Thu, Dec 18, 2014 at 09:50:26AM +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 18-12-14 03:48, Chen-Yu Tsai wrote:
>>> Hi,
>>>
>>> On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
>>>> On sun6i the cir block is attached to the reset controller, add support
>>>> for de-asserting the reset if a reset controller is specified in dt.
>>>>
>>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>> Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
>>>> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>>> ---
>>>>   .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
>>>>   drivers/media/rc/sunxi-cir.c                       | 25 ++++++++++++++++++++--
>>>>   2 files changed, 25 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>> index 23dd5ad..6b70b9b 100644
>>>> --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>> +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>> @@ -10,6 +10,7 @@ Required properties:
>>>>
>>>>   Optional properties:
>>>>   - linux,rc-map-name : Remote control map name.
>>>> +- resets : phandle + reset specifier pair
>>>
>>> Should it be optional? Or should we use a sun6i compatible with
>>> a mandatory reset phandle? I mean, the driver/hardware is not
>>> going to work with the reset missing on sun6i.
>>>
>>> Seems we are doing it one way for some of our drivers, and
>>> the other (optional) way for more generic ones, like USB.
>>
>> I do not believe that we should add a new compatible just because
>> the reset line of a block is hooked up differently. It is the
>> exact same ip-block. Only now the reset is not controlled
>> through the apb-gate, but controlled separately.
>
> He has a point though. Your driver might very well probe nicely and
> everything, but still wouldn't be functional at all because the reset
> line wouldn't have been specified in the DT.

Right, just like other drivers we've, see e.g.:

Documentation/devicetree/bindings/mmc/sunxi-mmc.txt

Which is dealing with this in the same way.

> The easiest way to deal with that would be in the bindings doc to
> update it with a compatible for the A31, and mentionning that the
> reset property is mandatory there.

No the easiest way to deal with this is to expect people writing
the dts to know what they are doing, just like we do for a lot
of the other blocks in sun6i.

Maybe put a generic note somewhere that sun6i has a reset controller,
and that for all the blocks with optional resets property it should
be considered mandatory on sun6i ?

I'm sorry but I'm not going to make this change for the ir bindings
given that we've the same situation in a lot of other places.

Consistency is important. Moreover I believe that having a sun6i
specific compatible string is just wrong, since it is the exact
same hardware block as on sun5i, just with its reset line routed
differently, just like e.g. the mmc controller, the uarts or the gmac
all of which also do not have a sun6i specific compatible to enforce
reset controller usage.

Regards,

Hans



> Note that the code itself might not change at all though. I'd just
> like to avoid any potential breaking of the DT bindings themselves. If
> we further want to refine the code, we can do that however we want.
>
> I have a slight preference for a clean error if reset is missing, but
> I won't get in the way just for that.
>
> Maxime
>

Re: [PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi

[Hans de Goede]

Hi,

On 19-12-14 19:34, Maxime Ripard wrote:
> On Wed, Dec 17, 2014 at 06:18:23PM +0100, Hans de Goede wrote:
>> Add a dtsi file for A31s based boards.
>>
>> Since the  A31s is the same die as the A31 in a different package, this dtsi
>> simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to
>> reflect the different package, everything else is identical.
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>> Changes in v2:
>> -include sun6i-a31.dtsi and override the pinctrl compatible, rather then
>>   copying everything
>> ---
>>   arch/arm/boot/dts/sun6i-a31s.dtsi | 62 +++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 62 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> new file mode 100644
>> index 0000000..d0bd2b9
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> @@ -0,0 +1,62 @@
>> +/*
>> + * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This library is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This library is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + *     You should have received a copy of the GNU General Public
>> + *     License along with this library; if not, write to the Free
>> + *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + *     MA 02110-1301 USA
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/*
>> + * The A31s is the same die as the A31 in a different package, this is
>> + * reflected by it having different pinctrl compatible everything else is
>> + * identical.
>> + */
>> +
>> +/include/ "sun6i-a31.dtsi"
>> +
>> +/ {
>> +	soc@01c00000 {
>> +		pio: pinctrl@01c20800 {
>> +			compatible = "allwinner,sun6i-a31s-pinctrl";
>> +		};
>> +	};
>> +};
>
> Given your previous changes, you should also update the enable-method.

I've not added a new compatible for the enable-method, given that
this is the exact same die, so the 2 are 100?% compatible, just like you
insisted that "allwinner,sun4i-a10-mod0-clk" should be used for the ir-clk
since it was 100% compatible to that I believe that the enable method
should use the existing compatible and not invent a new one for something
which is 100% compatible.

> Also, for this patch and the next one, Arnd just warned me that we
> shouldn't duplicate the DT path, and that we should switch to the new
> trend on using label references (like what TI or Amlogic does for
> example).

Ok, so something like this, right ?  :

&pio {
	compatible = "allwinner,sun6i-a31s-pinctrl";
};

Once we've agreement on the enable-method I'll respin this patch and
the CSQ CS908 board patch.

Regards,

Hans

Re: [PATCH v2 06/13] clk: sunxi: Make the mod0 clk driver also a platform driver

[Hans de Goede]

Hi,

On 19-12-14 19:24, Maxime Ripard wrote:
> Hi,
>
> On Wed, Dec 17, 2014 at 06:18:17PM +0100, Hans de Goede wrote:
>> With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
>> through the mfd framework, and as such do not work with of_clk_declare, since
>> they do not have registers assigned to them yet at of_clk_declare init time.
>>
>> Silence the error on not finding registers in the of_clk_declare mod0 clk
>> setup method, and also register mod0-clk support as a platform driver to work
>> properly with mfd instantiated mod0 clocks.
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>>   drivers/clk/sunxi/clk-mod0.c | 41 ++++++++++++++++++++++++++++++++++++-----
>>   1 file changed, 36 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
>> index 658d74f..7ddab6f 100644
>> --- a/drivers/clk/sunxi/clk-mod0.c
>> +++ b/drivers/clk/sunxi/clk-mod0.c
>> @@ -17,6 +17,7 @@
>>   #include <linux/clk-provider.h>
>>   #include <linux/clkdev.h>
>>   #include <linux/of_address.h>
>> +#include <linux/platform_device.h>
>>
>>   #include "clk-factors.h"
>>
>> @@ -67,7 +68,7 @@ static struct clk_factors_config sun4i_a10_mod0_config = {
>>   	.pwidth = 2,
>>   };
>>
>> -static const struct factors_data sun4i_a10_mod0_data __initconst = {
>> +static const struct factors_data sun4i_a10_mod0_data = {
>>   	.enable = 31,
>>   	.mux = 24,
>>   	.muxmask = BIT(1) | BIT(0),
>> @@ -82,17 +83,47 @@ static void __init sun4i_a10_mod0_setup(struct device_node *node)
>>   	void __iomem *reg;
>>
>>   	reg = of_iomap(node, 0);
>> -	if (!reg) {
>> -		pr_err("Could not get registers for mod0-clk: %s\n",
>> -		       node->name);
>> +	if (!reg)
>>   		return;
>> -	}
>
> A comment here would be nice to mention that this is intentional.

Ok, I'll respin this patch adding such a comment.

Regards,

Hans

Re: [PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 5115 bytes --]

On Sat, Dec 20, 2014 at 11:24:55AM +0100, Hans de Goede wrote:
> Hi,
> 
> On 19-12-14 19:34, Maxime Ripard wrote:
> >On Wed, Dec 17, 2014 at 06:18:23PM +0100, Hans de Goede wrote:
> >>Add a dtsi file for A31s based boards.
> >>
> >>Since the  A31s is the same die as the A31 in a different package, this dtsi
> >>simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to
> >>reflect the different package, everything else is identical.
> >>
> >>Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>---
> >>Changes in v2:
> >>-include sun6i-a31.dtsi and override the pinctrl compatible, rather then
> >>  copying everything
> >>---
> >>  arch/arm/boot/dts/sun6i-a31s.dtsi | 62 +++++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 62 insertions(+)
> >>  create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
> >>
> >>diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
> >>new file mode 100644
> >>index 0000000..d0bd2b9
> >>--- /dev/null
> >>+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
> >>@@ -0,0 +1,62 @@
> >>+/*
> >>+ * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>+ *
> >>+ * This file is dual-licensed: you can use it either under the terms
> >>+ * of the GPL or the X11 license, at your option. Note that this dual
> >>+ * licensing only applies to this file, and not this project as a
> >>+ * whole.
> >>+ *
> >>+ *  a) This library is free software; you can redistribute it and/or
> >>+ *     modify it under the terms of the GNU General Public License as
> >>+ *     published by the Free Software Foundation; either version 2 of the
> >>+ *     License, or (at your option) any later version.
> >>+ *
> >>+ *     This library is distributed in the hope that it will be useful,
> >>+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>+ *     GNU General Public License for more details.
> >>+ *
> >>+ *     You should have received a copy of the GNU General Public
> >>+ *     License along with this library; if not, write to the Free
> >>+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> >>+ *     MA 02110-1301 USA
> >>+ *
> >>+ * Or, alternatively,
> >>+ *
> >>+ *  b) Permission is hereby granted, free of charge, to any person
> >>+ *     obtaining a copy of this software and associated documentation
> >>+ *     files (the "Software"), to deal in the Software without
> >>+ *     restriction, including without limitation the rights to use,
> >>+ *     copy, modify, merge, publish, distribute, sublicense, and/or
> >>+ *     sell copies of the Software, and to permit persons to whom the
> >>+ *     Software is furnished to do so, subject to the following
> >>+ *     conditions:
> >>+ *
> >>+ *     The above copyright notice and this permission notice shall be
> >>+ *     included in all copies or substantial portions of the Software.
> >>+ *
> >>+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >>+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> >>+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> >>+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> >>+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> >>+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >>+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >>+ *     OTHER DEALINGS IN THE SOFTWARE.
> >>+ */
> >>+
> >>+/*
> >>+ * The A31s is the same die as the A31 in a different package, this is
> >>+ * reflected by it having different pinctrl compatible everything else is
> >>+ * identical.
> >>+ */
> >>+
> >>+/include/ "sun6i-a31.dtsi"
> >>+
> >>+/ {
> >>+	soc@01c00000 {
> >>+		pio: pinctrl@01c20800 {
> >>+			compatible = "allwinner,sun6i-a31s-pinctrl";
> >>+		};
> >>+	};
> >>+};
> >
> >Given your previous changes, you should also update the enable-method.
> 
> I've not added a new compatible for the enable-method, given that
> this is the exact same die, so the 2 are 100?% compatible, just like you
> insisted that "allwinner,sun4i-a10-mod0-clk" should be used for the ir-clk
> since it was 100% compatible to that I believe that the enable method
> should use the existing compatible and not invent a new one for something
> which is 100% compatible.

Yeah, you have a point and I agree, but your patch 3 does add a
CPU_METHOD_OF_DECLARE for the A31s.

Since I was going to push the branch now that 3.19-rc1 is out, do you
want me to edit your patch before doing so?


> >Also, for this patch and the next one, Arnd just warned me that we
> >shouldn't duplicate the DT path, and that we should switch to the new
> >trend on using label references (like what TI or Amlogic does for
> >example).
> 
> Ok, so something like this, right ?  :
> 
> &pio {
> 	compatible = "allwinner,sun6i-a31s-pinctrl";
> };

Yep.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi

[Hans de Goede]

Hi,

On 21-12-14 23:39, Maxime Ripard wrote:
> On Sat, Dec 20, 2014 at 11:24:55AM +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 19-12-14 19:34, Maxime Ripard wrote:
>>> On Wed, Dec 17, 2014 at 06:18:23PM +0100, Hans de Goede wrote:
>>>> Add a dtsi file for A31s based boards.
>>>>
>>>> Since the  A31s is the same die as the A31 in a different package, this dtsi
>>>> simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to
>>>> reflect the different package, everything else is identical.
>>>>
>>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>> ---
>>>> Changes in v2:
>>>> -include sun6i-a31.dtsi and override the pinctrl compatible, rather then
>>>>   copying everything
>>>> ---
>>>>   arch/arm/boot/dts/sun6i-a31s.dtsi | 62 +++++++++++++++++++++++++++++++++++++++
>>>>   1 file changed, 62 insertions(+)
>>>>   create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
>>>>
>>>> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
>>>> new file mode 100644
>>>> index 0000000..d0bd2b9
>>>> --- /dev/null
>>>> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
>>>> @@ -0,0 +1,62 @@
>>>> +/*
>>>> + * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>> + *
>>>> + * This file is dual-licensed: you can use it either under the terms
>>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>>> + * licensing only applies to this file, and not this project as a
>>>> + * whole.
>>>> + *
>>>> + *  a) This library is free software; you can redistribute it and/or
>>>> + *     modify it under the terms of the GNU General Public License as
>>>> + *     published by the Free Software Foundation; either version 2 of the
>>>> + *     License, or (at your option) any later version.
>>>> + *
>>>> + *     This library is distributed in the hope that it will be useful,
>>>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>> + *     GNU General Public License for more details.
>>>> + *
>>>> + *     You should have received a copy of the GNU General Public
>>>> + *     License along with this library; if not, write to the Free
>>>> + *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>>>> + *     MA 02110-1301 USA
>>>> + *
>>>> + * Or, alternatively,
>>>> + *
>>>> + *  b) Permission is hereby granted, free of charge, to any person
>>>> + *     obtaining a copy of this software and associated documentation
>>>> + *     files (the "Software"), to deal in the Software without
>>>> + *     restriction, including without limitation the rights to use,
>>>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>>>> + *     sell copies of the Software, and to permit persons to whom the
>>>> + *     Software is furnished to do so, subject to the following
>>>> + *     conditions:
>>>> + *
>>>> + *     The above copyright notice and this permission notice shall be
>>>> + *     included in all copies or substantial portions of the Software.
>>>> + *
>>>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>>> + *     OTHER DEALINGS IN THE SOFTWARE.
>>>> + */
>>>> +
>>>> +/*
>>>> + * The A31s is the same die as the A31 in a different package, this is
>>>> + * reflected by it having different pinctrl compatible everything else is
>>>> + * identical.
>>>> + */
>>>> +
>>>> +/include/ "sun6i-a31.dtsi"
>>>> +
>>>> +/ {
>>>> +	soc@01c00000 {
>>>> +		pio: pinctrl@01c20800 {
>>>> +			compatible = "allwinner,sun6i-a31s-pinctrl";
>>>> +		};
>>>> +	};
>>>> +};
>>>
>>> Given your previous changes, you should also update the enable-method.
>>
>> I've not added a new compatible for the enable-method, given that
>> this is the exact same die, so the 2 are 100?% compatible, just like you
>> insisted that "allwinner,sun4i-a10-mod0-clk" should be used for the ir-clk
>> since it was 100% compatible to that I believe that the enable method
>> should use the existing compatible and not invent a new one for something
>> which is 100% compatible.
>
> Yeah, you have a point and I agree, but your patch 3 does add a
> CPU_METHOD_OF_DECLARE for the A31s.

Ah right, it does, my bad.

> Since I was going to push the branch now that 3.19-rc1 is out, do you
> want me to edit your patch before doing so?

Yes, please drop the addition of the extra CPU_METHOD_OF_DECLARE, or let
me know if you want a new version instead.

>>> Also, for this patch and the next one, Arnd just warned me that we
>>> shouldn't duplicate the DT path, and that we should switch to the new
>>> trend on using label references (like what TI or Amlogic does for
>>> example).
>>
>> Ok, so something like this, right ?  :
>>
>> &pio {
>> 	compatible = "allwinner,sun6i-a31s-pinctrl";
>> };
>
> Yep.

Regards,

Hans

Re: [PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 5310 bytes --]

Hi,

On Mon, Dec 22, 2014 at 02:46:12PM +0100, Hans de Goede wrote:
> On 21-12-14 23:39, Maxime Ripard wrote:
> >On Sat, Dec 20, 2014 at 11:24:55AM +0100, Hans de Goede wrote:
> >>Hi,
> >>
> >>On 19-12-14 19:34, Maxime Ripard wrote:
> >>>On Wed, Dec 17, 2014 at 06:18:23PM +0100, Hans de Goede wrote:
> >>>>Add a dtsi file for A31s based boards.
> >>>>
> >>>>Since the  A31s is the same die as the A31 in a different package, this dtsi
> >>>>simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to
> >>>>reflect the different package, everything else is identical.
> >>>>
> >>>>Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>>>---
> >>>>Changes in v2:
> >>>>-include sun6i-a31.dtsi and override the pinctrl compatible, rather then
> >>>>  copying everything
> >>>>---
> >>>>  arch/arm/boot/dts/sun6i-a31s.dtsi | 62 +++++++++++++++++++++++++++++++++++++++
> >>>>  1 file changed, 62 insertions(+)
> >>>>  create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
> >>>>
> >>>>diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
> >>>>new file mode 100644
> >>>>index 0000000..d0bd2b9
> >>>>--- /dev/null
> >>>>+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
> >>>>@@ -0,0 +1,62 @@
> >>>>+/*
> >>>>+ * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>>>+ *
> >>>>+ * This file is dual-licensed: you can use it either under the terms
> >>>>+ * of the GPL or the X11 license, at your option. Note that this dual
> >>>>+ * licensing only applies to this file, and not this project as a
> >>>>+ * whole.
> >>>>+ *
> >>>>+ *  a) This library is free software; you can redistribute it and/or
> >>>>+ *     modify it under the terms of the GNU General Public License as
> >>>>+ *     published by the Free Software Foundation; either version 2 of the
> >>>>+ *     License, or (at your option) any later version.
> >>>>+ *
> >>>>+ *     This library is distributed in the hope that it will be useful,
> >>>>+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>>>+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>>>+ *     GNU General Public License for more details.
> >>>>+ *
> >>>>+ *     You should have received a copy of the GNU General Public
> >>>>+ *     License along with this library; if not, write to the Free
> >>>>+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> >>>>+ *     MA 02110-1301 USA
> >>>>+ *
> >>>>+ * Or, alternatively,
> >>>>+ *
> >>>>+ *  b) Permission is hereby granted, free of charge, to any person
> >>>>+ *     obtaining a copy of this software and associated documentation
> >>>>+ *     files (the "Software"), to deal in the Software without
> >>>>+ *     restriction, including without limitation the rights to use,
> >>>>+ *     copy, modify, merge, publish, distribute, sublicense, and/or
> >>>>+ *     sell copies of the Software, and to permit persons to whom the
> >>>>+ *     Software is furnished to do so, subject to the following
> >>>>+ *     conditions:
> >>>>+ *
> >>>>+ *     The above copyright notice and this permission notice shall be
> >>>>+ *     included in all copies or substantial portions of the Software.
> >>>>+ *
> >>>>+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >>>>+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> >>>>+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> >>>>+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> >>>>+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> >>>>+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >>>>+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >>>>+ *     OTHER DEALINGS IN THE SOFTWARE.
> >>>>+ */
> >>>>+
> >>>>+/*
> >>>>+ * The A31s is the same die as the A31 in a different package, this is
> >>>>+ * reflected by it having different pinctrl compatible everything else is
> >>>>+ * identical.
> >>>>+ */
> >>>>+
> >>>>+/include/ "sun6i-a31.dtsi"
> >>>>+
> >>>>+/ {
> >>>>+	soc@01c00000 {
> >>>>+		pio: pinctrl@01c20800 {
> >>>>+			compatible = "allwinner,sun6i-a31s-pinctrl";
> >>>>+		};
> >>>>+	};
> >>>>+};
> >>>
> >>>Given your previous changes, you should also update the enable-method.
> >>
> >>I've not added a new compatible for the enable-method, given that
> >>this is the exact same die, so the 2 are 100?% compatible, just like you
> >>insisted that "allwinner,sun4i-a10-mod0-clk" should be used for the ir-clk
> >>since it was 100% compatible to that I believe that the enable method
> >>should use the existing compatible and not invent a new one for something
> >>which is 100% compatible.
> >
> >Yeah, you have a point and I agree, but your patch 3 does add a
> >CPU_METHOD_OF_DECLARE for the A31s.
> 
> Ah right, it does, my bad.
> 
> >Since I was going to push the branch now that 3.19-rc1 is out, do you
> >want me to edit your patch before doing so?
> 
> Yes, please drop the addition of the extra CPU_METHOD_OF_DECLARE, or let
> me know if you want a new version instead.

I just modified it, and pushed it, no need to resend it.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi

[Hans de Goede]

Hi,

On 05-01-15 10:08, Maxime Ripard wrote:
> Hi,
>
> On Mon, Dec 22, 2014 at 02:46:12PM +0100, Hans de Goede wrote:
>> On 21-12-14 23:39, Maxime Ripard wrote:
>>> On Sat, Dec 20, 2014 at 11:24:55AM +0100, Hans de Goede wrote:

<snip>

>>>>> Given your previous changes, you should also update the enable-method.
>>>>
>>>> I've not added a new compatible for the enable-method, given that
>>>> this is the exact same die, so the 2 are 100?% compatible, just like you
>>>> insisted that "allwinner,sun4i-a10-mod0-clk" should be used for the ir-clk
>>>> since it was 100% compatible to that I believe that the enable method
>>>> should use the existing compatible and not invent a new one for something
>>>> which is 100% compatible.
>>>
>>> Yeah, you have a point and I agree, but your patch 3 does add a
>>> CPU_METHOD_OF_DECLARE for the A31s.
>>
>> Ah right, it does, my bad.
>>
>>> Since I was going to push the branch now that 3.19-rc1 is out, do you
>>> want me to edit your patch before doing so?
>>
>> Yes, please drop the addition of the extra CPU_METHOD_OF_DECLARE, or let
>> me know if you want a new version instead.
>
> I just modified it, and pushed it, no need to resend it.

Thanks, while looking at your dt-for-3.20 branch I noticed that you've
merged v2 of "ARM: dts: sun6i: Add ir node", I did a v3 adding an ir:
label to the node, which I noticed was missing because you asked me to
move the a31s dt stuff to moving label references, can you fix this up, or
do you want me to do a follow up patch ?

Note that having this fixed is a pre-req for the csq-cs908 dts patch.

Regards,

Hans

Re: [PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 663 bytes --]

Hi,

On Mon, Jan 05, 2015 at 10:31:05AM +0100, Hans de Goede wrote:
> Thanks, while looking at your dt-for-3.20 branch I noticed that you've
> merged v2 of "ARM: dts: sun6i: Add ir node", I did a v3 adding an ir:
> label to the node, which I noticed was missing because you asked me to
> move the a31s dt stuff to moving label references, can you fix this up, or
> do you want me to do a follow up patch ?
> 
> Note that having this fixed is a pre-req for the csq-cs908 dts patch.

Ah, right. I edited your previous patch to add the label.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 01/13] pinctrl: sun6i: Add some missing functions

[Linus Walleij]

On Wed, Dec 17, 2014 at 6:18 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:

> While working on pinctrl for the A31s, I noticed that function 4 of
> PA15 - PA18 was missing, add these.
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> Changes in v2:
> -Drop the changes to the muxing of i2c3 this was based on
>  "A31s Datasheet v1.40.pdf", but all other A31 related info puts them at the
>  pins where we already have them, so leave this as is

Patch applied with Maxime's ACK.

Yours,
Linus Walleij

Re: [PATCH v2 02/13] pinctrl: sun6i: Add A31s pinctrl support

[Linus Walleij]

On Wed, Dec 17, 2014 at 6:18 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:

> The A31s is a stripped down version of the A31, as such it is missing some
> pins and some functions on some pins.
>
> The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
> with the missing pins and functions removed.
>
> Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
> prcm pins are identical between the A31 and the A31s.
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> Changes in v2:
> -Sync i2c3 muxing with v2 of "pinctrl: sun6i: Add some missing functions"
> -Add myself to the copyright header

Patch applied with Maxime's ACK.

Yours,
Linus Walleij

Re: [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller

[Chen-Yu Tsai]

Hi,

On Sat, Dec 20, 2014 at 6:20 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
> Hi,
>
>
> On 19-12-14 19:17, Maxime Ripard wrote:
>>
>> Hi,
>>
>> On Thu, Dec 18, 2014 at 09:50:26AM +0100, Hans de Goede wrote:
>>>
>>> Hi,
>>>
>>> On 18-12-14 03:48, Chen-Yu Tsai wrote:
>>>>
>>>> Hi,
>>>>
>>>> On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>> wrote:
>>>>>
>>>>> On sun6i the cir block is attached to the reset controller, add support
>>>>> for de-asserting the reset if a reset controller is specified in dt.
>>>>>
>>>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>>> Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
>>>>> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>>>> ---
>>>>>   .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
>>>>>   drivers/media/rc/sunxi-cir.c                       | 25
>>>>> ++++++++++++++++++++--
>>>>>   2 files changed, 25 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>> b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>> index 23dd5ad..6b70b9b 100644
>>>>> --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>> +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>> @@ -10,6 +10,7 @@ Required properties:
>>>>>
>>>>>   Optional properties:
>>>>>   - linux,rc-map-name : Remote control map name.
>>>>> +- resets : phandle + reset specifier pair
>>>>
>>>>
>>>> Should it be optional? Or should we use a sun6i compatible with
>>>> a mandatory reset phandle? I mean, the driver/hardware is not
>>>> going to work with the reset missing on sun6i.
>>>>
>>>> Seems we are doing it one way for some of our drivers, and
>>>> the other (optional) way for more generic ones, like USB.
>>>
>>>
>>> I do not believe that we should add a new compatible just because
>>> the reset line of a block is hooked up differently. It is the
>>> exact same ip-block. Only now the reset is not controlled
>>> through the apb-gate, but controlled separately.
>>
>>
>> He has a point though. Your driver might very well probe nicely and
>> everything, but still wouldn't be functional at all because the reset
>> line wouldn't have been specified in the DT.
>
>
> Right, just like other drivers we've, see e.g.:
>
> Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
>
> Which is dealing with this in the same way.
>
>> The easiest way to deal with that would be in the bindings doc to
>> update it with a compatible for the A31, and mentionning that the
>> reset property is mandatory there.
>
>
> No the easiest way to deal with this is to expect people writing
> the dts to know what they are doing, just like we do for a lot
> of the other blocks in sun6i.
>
> Maybe put a generic note somewhere that sun6i has a reset controller,
> and that for all the blocks with optional resets property it should
> be considered mandatory on sun6i ?
>
> I'm sorry but I'm not going to make this change for the ir bindings
> given that we've the same situation in a lot of other places.
>
> Consistency is important. Moreover I believe that having a sun6i
> specific compatible string is just wrong, since it is the exact
> same hardware block as on sun5i, just with its reset line routed
> differently, just like e.g. the mmc controller, the uarts or the gmac
> all of which also do not have a sun6i specific compatible to enforce
> reset controller usage.
>
> Regards,
>
> Hans
>
>
>
>
>> Note that the code itself might not change at all though. I'd just
>> like to avoid any potential breaking of the DT bindings themselves. If
>> we further want to refine the code, we can do that however we want.
>>
>> I have a slight preference for a clean error if reset is missing, but
>> I won't get in the way just for that.

Seems this patch and the following patch were overlooked after the
discussion. Any chance we could get this in? Hans has made a good
argument, so I take back any doubts I raised.

ChenYu

Re: [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller

[Hans de Goede]

Hi,

On 19-01-15 15:10, Chen-Yu Tsai wrote:
> Hi,
>
> On Sat, Dec 20, 2014 at 6:20 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
>> Hi,
>>
>>
>> On 19-12-14 19:17, Maxime Ripard wrote:
>>>
>>> Hi,
>>>
>>> On Thu, Dec 18, 2014 at 09:50:26AM +0100, Hans de Goede wrote:
>>>>
>>>> Hi,
>>>>
>>>> On 18-12-14 03:48, Chen-Yu Tsai wrote:
>>>>>
>>>>> Hi,
>>>>>
>>>>> On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>>> wrote:
>>>>>>
>>>>>> On sun6i the cir block is attached to the reset controller, add support
>>>>>> for de-asserting the reset if a reset controller is specified in dt.
>>>>>>
>>>>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>>>> Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
>>>>>> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>>>>> ---
>>>>>>    .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
>>>>>>    drivers/media/rc/sunxi-cir.c                       | 25
>>>>>> ++++++++++++++++++++--
>>>>>>    2 files changed, 25 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>>> b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>>> index 23dd5ad..6b70b9b 100644
>>>>>> --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>>> +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>>> @@ -10,6 +10,7 @@ Required properties:
>>>>>>
>>>>>>    Optional properties:
>>>>>>    - linux,rc-map-name : Remote control map name.
>>>>>> +- resets : phandle + reset specifier pair
>>>>>
>>>>>
>>>>> Should it be optional? Or should we use a sun6i compatible with
>>>>> a mandatory reset phandle? I mean, the driver/hardware is not
>>>>> going to work with the reset missing on sun6i.
>>>>>
>>>>> Seems we are doing it one way for some of our drivers, and
>>>>> the other (optional) way for more generic ones, like USB.
>>>>
>>>>
>>>> I do not believe that we should add a new compatible just because
>>>> the reset line of a block is hooked up differently. It is the
>>>> exact same ip-block. Only now the reset is not controlled
>>>> through the apb-gate, but controlled separately.
>>>
>>>
>>> He has a point though. Your driver might very well probe nicely and
>>> everything, but still wouldn't be functional at all because the reset
>>> line wouldn't have been specified in the DT.
>>
>>
>> Right, just like other drivers we've, see e.g.:
>>
>> Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
>>
>> Which is dealing with this in the same way.
>>
>>> The easiest way to deal with that would be in the bindings doc to
>>> update it with a compatible for the A31, and mentionning that the
>>> reset property is mandatory there.
>>
>>
>> No the easiest way to deal with this is to expect people writing
>> the dts to know what they are doing, just like we do for a lot
>> of the other blocks in sun6i.
>>
>> Maybe put a generic note somewhere that sun6i has a reset controller,
>> and that for all the blocks with optional resets property it should
>> be considered mandatory on sun6i ?
>>
>> I'm sorry but I'm not going to make this change for the ir bindings
>> given that we've the same situation in a lot of other places.
>>
>> Consistency is important. Moreover I believe that having a sun6i
>> specific compatible string is just wrong, since it is the exact
>> same hardware block as on sun5i, just with its reset line routed
>> differently, just like e.g. the mmc controller, the uarts or the gmac
>> all of which also do not have a sun6i specific compatible to enforce
>> reset controller usage.
>>
>> Regards,
>>
>> Hans
>>
>>
>>
>>
>>> Note that the code itself might not change at all though. I'd just
>>> like to avoid any potential breaking of the DT bindings themselves. If
>>> we further want to refine the code, we can do that however we want.
>>>
>>> I have a slight preference for a clean error if reset is missing, but
>>> I won't get in the way just for that.
>
> Seems this patch and the following patch were overlooked after the
> discussion. Any chance we could get this in?

I'm a linux/media sub-maintainer, so I've already send a pull-req for
these 2 to the linux/media maintainer, iow this is taken care of :)

Regards,

Hans

Re: [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller

[Chen-Yu Tsai]

On Mon, Jan 19, 2015 at 10:17 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
> Hi,
>
>
> On 19-01-15 15:10, Chen-Yu Tsai wrote:
>>
>> Hi,
>>
>> On Sat, Dec 20, 2014 at 6:20 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> wrote:
>>>
>>> Hi,
>>>
>>>
>>> On 19-12-14 19:17, Maxime Ripard wrote:
>>>>
>>>>
>>>> Hi,
>>>>
>>>> On Thu, Dec 18, 2014 at 09:50:26AM +0100, Hans de Goede wrote:
>>>>>
>>>>>
>>>>> Hi,
>>>>>
>>>>> On 18-12-14 03:48, Chen-Yu Tsai wrote:
>>>>>>
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>>>> wrote:
>>>>>>>
>>>>>>>
>>>>>>> On sun6i the cir block is attached to the reset controller, add
>>>>>>> support
>>>>>>> for de-asserting the reset if a reset controller is specified in dt.
>>>>>>>
>>>>>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>>>>> Acked-by: Mauro Carvalho Chehab <mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
>>>>>>> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>>>>>> ---
>>>>>>>    .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
>>>>>>>    drivers/media/rc/sunxi-cir.c                       | 25
>>>>>>> ++++++++++++++++++++--
>>>>>>>    2 files changed, 25 insertions(+), 2 deletions(-)
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>>>> b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>>>> index 23dd5ad..6b70b9b 100644
>>>>>>> --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>>>> +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
>>>>>>> @@ -10,6 +10,7 @@ Required properties:
>>>>>>>
>>>>>>>    Optional properties:
>>>>>>>    - linux,rc-map-name : Remote control map name.
>>>>>>> +- resets : phandle + reset specifier pair
>>>>>>
>>>>>>
>>>>>>
>>>>>> Should it be optional? Or should we use a sun6i compatible with
>>>>>> a mandatory reset phandle? I mean, the driver/hardware is not
>>>>>> going to work with the reset missing on sun6i.
>>>>>>
>>>>>> Seems we are doing it one way for some of our drivers, and
>>>>>> the other (optional) way for more generic ones, like USB.
>>>>>
>>>>>
>>>>>
>>>>> I do not believe that we should add a new compatible just because
>>>>> the reset line of a block is hooked up differently. It is the
>>>>> exact same ip-block. Only now the reset is not controlled
>>>>> through the apb-gate, but controlled separately.
>>>>
>>>>
>>>>
>>>> He has a point though. Your driver might very well probe nicely and
>>>> everything, but still wouldn't be functional at all because the reset
>>>> line wouldn't have been specified in the DT.
>>>
>>>
>>>
>>> Right, just like other drivers we've, see e.g.:
>>>
>>> Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
>>>
>>> Which is dealing with this in the same way.
>>>
>>>> The easiest way to deal with that would be in the bindings doc to
>>>> update it with a compatible for the A31, and mentionning that the
>>>> reset property is mandatory there.
>>>
>>>
>>>
>>> No the easiest way to deal with this is to expect people writing
>>> the dts to know what they are doing, just like we do for a lot
>>> of the other blocks in sun6i.
>>>
>>> Maybe put a generic note somewhere that sun6i has a reset controller,
>>> and that for all the blocks with optional resets property it should
>>> be considered mandatory on sun6i ?
>>>
>>> I'm sorry but I'm not going to make this change for the ir bindings
>>> given that we've the same situation in a lot of other places.
>>>
>>> Consistency is important. Moreover I believe that having a sun6i
>>> specific compatible string is just wrong, since it is the exact
>>> same hardware block as on sun5i, just with its reset line routed
>>> differently, just like e.g. the mmc controller, the uarts or the gmac
>>> all of which also do not have a sun6i specific compatible to enforce
>>> reset controller usage.
>>>
>>> Regards,
>>>
>>> Hans
>>>
>>>
>>>
>>>
>>>> Note that the code itself might not change at all though. I'd just
>>>> like to avoid any potential breaking of the DT bindings themselves. If
>>>> we further want to refine the code, we can do that however we want.
>>>>
>>>> I have a slight preference for a clean error if reset is missing, but
>>>> I won't get in the way just for that.
>>
>>
>> Seems this patch and the following patch were overlooked after the
>> discussion. Any chance we could get this in?
>
>
> I'm a linux/media sub-maintainer, so I've already send a pull-req for
> these 2 to the linux/media maintainer, iow this is taken care of :)

That's good to hear. I was going through the mainlining effort page,
and couldn't find these 2 in linux-next. I'll mark them as planned
for 3.20 then.


Chen-Yu