Re: [v3,3/9] clk: samsung: exynos5433: Add clocks for CMU_MSCL domain

[Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>]

Hi Chanwoo,

On Tuesday 03 February 2015 05:43 AM, Chanwoo Choi wrote:
> This patch adds the mux/divider/gate clocks for CMU_MSCL domain which
> generates the clocks for M2M (Memory to Memory) scaler, JPEG IPs.
>
> Cc: Sylwester Nawrocki <s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Cc: Tomasz Figa <tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Acked-by: Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>
> ---
> .../devicetree/bindings/clock/exynos5433-clock.txt |  20 +++
>   drivers/clk/samsung/clk-exynos5433.c               | 185 +++++++++++++++++++++
>   include/dt-bindings/clock/exynos5433.h             |  41 ++++-
>   3 files changed, 245 insertions(+), 1 deletion(-)
>

Verified clock tree, clock register and bitfield settings against UM.
Changes looks OK to me.

Reviewed-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

Thanks,
Pankaj Dubey
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