[PATCH 0/2] fix ehrpwm tbclk data on am33xx and am43xx

[PATCH 0/2] fix ehrpwm tbclk data on am33xx and am43xx

[Vignesh R]

In am33xx and am43xx, ehrpwm tbclk is derived from functional clock of
PWMSS. The schematics and TRMs show that there is only one input clock to
the PWMSS. But currently, tbclk is wrongly shown to be deriving from
dpll_per_m2_ck instead of functional clock l4ls_gclk in the DT.

Fixing ehrpwm tbclk data to reflect the right clk source.
Tested on beaglebone and am437x-gp-evm.

Vignesh R (2):
  ARM: dts: am33xx-clocks: Fix ehrpwm tbclk data on am33xx
  ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx

 arch/arm/boot/dts/am33xx-clocks.dtsi |  6 +++---
 arch/arm/boot/dts/am43xx-clocks.dtsi | 12 ++++++------
 2 files changed, 9 insertions(+), 9 deletions(-)

-- 
1.9.1

[PATCH 1/2] ARM: dts: am33xx-clocks: Fix ehrpwm tbclk data on am33xx

[Vignesh R]

ehrpwm tbclk is wrongly modelled as deriving from dpll_per_m2_ck.
The TRM says tbclk is derived from SYSCLKOUT. SYSCLKOUT nothing but the
functional clock of pwmss (l4ls_gclk).
Fix this by changing source of ehrpwmx_tbclk to l4ls_gclk.

Fixes: 9e100ebafb91: ("Fix ehrpwm tbclk data")
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/am33xx-clocks.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce7d6fb..071b56aa0c7e 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -99,7 +99,7 @@
 	ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <0>;
 		reg = <0x0664>;
 	};
@@ -107,7 +107,7 @@
 	ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <1>;
 		reg = <0x0664>;
 	};
@@ -115,7 +115,7 @@
 	ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <2>;
 		reg = <0x0664>;
 	};
-- 
1.9.1

[PATCH 2/2] ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx

[Vignesh R]

ehrpwm tbclk is wrongly modelled as deriving from dpll_per_m2_ck.
The TRM says tbclk is derived from SYSCLKOUT. SYSCLKOUT nothing but the
functional clock of pwmss (l4ls_gclk).
Fix this by changing source of ehrpwmx_tbclk to l4ls_gclk.

Fixes: 4da1c67719f61 ("add tbclk data for ehrpwm")
Signed-off-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/am43xx-clocks.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index c7dc9dab93a4..cfb49686ab6a 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -107,7 +107,7 @@
 	ehrpwm0_tbclk: ehrpwm0_tbclk {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <0>;
 		reg = <0x0664>;
 	};
@@ -115,7 +115,7 @@
 	ehrpwm1_tbclk: ehrpwm1_tbclk {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <1>;
 		reg = <0x0664>;
 	};
@@ -123,7 +123,7 @@
 	ehrpwm2_tbclk: ehrpwm2_tbclk {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <2>;
 		reg = <0x0664>;
 	};
@@ -131,7 +131,7 @@
 	ehrpwm3_tbclk: ehrpwm3_tbclk {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <4>;
 		reg = <0x0664>;
 	};
@@ -139,7 +139,7 @@
 	ehrpwm4_tbclk: ehrpwm4_tbclk {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <5>;
 		reg = <0x0664>;
 	};
@@ -147,7 +147,7 @@
 	ehrpwm5_tbclk: ehrpwm5_tbclk {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_per_m2_ck>;
+		clocks = <&l4ls_gclk>;
 		ti,bit-shift = <6>;
 		reg = <0x0664>;
 	};
-- 
1.9.1

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Re: [PATCH 0/2] fix ehrpwm tbclk data on am33xx and am43xx

[Tony Lindgren]

* Vignesh R <vigneshr@ti.com> [150209 22:43]:
> In am33xx and am43xx, ehrpwm tbclk is derived from functional clock of
> PWMSS. The schematics and TRMs show that there is only one input clock to
> the PWMSS. But currently, tbclk is wrongly shown to be deriving from
> dpll_per_m2_ck instead of functional clock l4ls_gclk in the DT.
> 
> Fixing ehrpwm tbclk data to reflect the right clk source.
> Tested on beaglebone and am437x-gp-evm.
> 
> Vignesh R (2):
>   ARM: dts: am33xx-clocks: Fix ehrpwm tbclk data on am33xx
>   ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx
> 
>  arch/arm/boot/dts/am33xx-clocks.dtsi |  6 +++---
>  arch/arm/boot/dts/am43xx-clocks.dtsi | 12 ++++++------
>  2 files changed, 9 insertions(+), 9 deletions(-)

Tero, care to check this one too and ack if OK?

Thanks,

Tony

Re: [PATCH 0/2] fix ehrpwm tbclk data on am33xx and am43xx

[Tero Kristo]

On 02/24/2015 07:15 PM, Tony Lindgren wrote:
> * Vignesh R <vigneshr@ti.com> [150209 22:43]:
>> In am33xx and am43xx, ehrpwm tbclk is derived from functional clock of
>> PWMSS. The schematics and TRMs show that there is only one input clock to
>> the PWMSS. But currently, tbclk is wrongly shown to be deriving from
>> dpll_per_m2_ck instead of functional clock l4ls_gclk in the DT.
>>
>> Fixing ehrpwm tbclk data to reflect the right clk source.
>> Tested on beaglebone and am437x-gp-evm.
>>
>> Vignesh R (2):
>>    ARM: dts: am33xx-clocks: Fix ehrpwm tbclk data on am33xx
>>    ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx
>>
>>   arch/arm/boot/dts/am33xx-clocks.dtsi |  6 +++---
>>   arch/arm/boot/dts/am43xx-clocks.dtsi | 12 ++++++------
>>   2 files changed, 9 insertions(+), 9 deletions(-)
>
> Tero, care to check this one too and ack if OK?

These look fine also, just verified from TRM. These two were actually 
buried in my mailbox, sorry about that.

Acked-by: Tero Kristo <t-kristo@ti.com>

Re: [PATCH 0/2] fix ehrpwm tbclk data on am33xx and am43xx

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [150224 23:39]:
> On 02/24/2015 07:15 PM, Tony Lindgren wrote:
> >* Vignesh R <vigneshr@ti.com> [150209 22:43]:
> >>In am33xx and am43xx, ehrpwm tbclk is derived from functional clock of
> >>PWMSS. The schematics and TRMs show that there is only one input clock to
> >>the PWMSS. But currently, tbclk is wrongly shown to be deriving from
> >>dpll_per_m2_ck instead of functional clock l4ls_gclk in the DT.
> >>
> >>Fixing ehrpwm tbclk data to reflect the right clk source.
> >>Tested on beaglebone and am437x-gp-evm.
> >>
> >>Vignesh R (2):
> >>   ARM: dts: am33xx-clocks: Fix ehrpwm tbclk data on am33xx
> >>   ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx
> >>
> >>  arch/arm/boot/dts/am33xx-clocks.dtsi |  6 +++---
> >>  arch/arm/boot/dts/am43xx-clocks.dtsi | 12 ++++++------
> >>  2 files changed, 9 insertions(+), 9 deletions(-)
> >
> >Tero, care to check this one too and ack if OK?
> 
> These look fine also, just verified from TRM. These two were actually buried
> in my mailbox, sorry about that.
> 
> Acked-by: Tero Kristo <t-kristo@ti.com>

Thanks applying both into omap-for-v4.0/fixes.

Tony