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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af47cd650basm240182766b.58.2025.07.25.02.30.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Jul 2025 02:31:00 -0700 (PDT) Message-ID: <54b617c1-bd1b-4244-b75d-57eaaa2c083d@oss.qualcomm.com> Date: Fri, 25 Jul 2025 11:30:57 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks To: Krzysztof Kozlowski , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250723-topic-8750_gpucc-v2-0-56c93b84c390@oss.qualcomm.com> <20250723-topic-8750_gpucc-v2-1-56c93b84c390@oss.qualcomm.com> <20250724-blazing-therapeutic-python-1e96ca@kuoka> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250724-blazing-therapeutic-python-1e96ca@kuoka> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: aneBRQqFlHZTP81W6mwNz9ka3qmEveW7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4MCBTYWx0ZWRfX/ozSzVY/GCHk uOTAP1P1GU5hA2HRFbDqRxdZkXYrECeyBAAvyFKCbhtvygaV2Yh2k5gwx/xbFGUdg7gdyK6wUf6 awYbfWkNzgYUYOxjzb69kKuG78Ii6yyfZV4oaxveHjBG2hR3tHO8e9Cpe5uyc76IkBP2ictjjn6 bv6a7qq5eA9e20enKi4nl5FtuajTB3n7mCCLzcxMf6Ag5iBwQqWQcy+yv3/PVu6QAyBPsvj4YRh S8X9lVWFGIC5TgERmCx5IgTFnQX5iP4ZS/6dcsQ6J7sjTUEPbUDVG5Ot5CN7j70SpP1yDg+uM5s ZFhsn2rmjNRuUmgGgyxp4BGglEKrKHc30hwVrF3RCifx/U5PsSwfZbDRsftEJxh+gQzbhEnnUmI XxU0Xq2+eyy6Df6qYXAyf1uPaaEpfFv20I3g3Xw9gLiO0RNE4RN2A7YHlRl4R11rz6mIzdIL X-Authority-Analysis: v=2.4 cv=d8b1yQjE c=1 sm=1 tr=0 ts=68834ed7 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=ZXpw8kv6nMavt5JzddgA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: aneBRQqFlHZTP81W6mwNz9ka3qmEveW7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 priorityscore=1501 phishscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250080 On 7/24/25 10:18 AM, Krzysztof Kozlowski wrote: > On Wed, Jul 23, 2025 at 10:38:48PM +0200, Konrad Dybcio wrote: >> From: Konrad Dybcio >> >> The SM8750 features a "traditional" GPU_CC block, much of which is >> controlled through the GMU microcontroller. Additionally, there's >> an separate GX_CC block, where the GX GDSC is moved. >> >> Add bindings to accommodate for that. >> >> Signed-off-by: Konrad Dybcio >> --- >> .../bindings/clock/qcom,sm8450-gpucc.yaml | 5 ++ >> .../bindings/clock/qcom,sm8750-gxcc.yaml | 61 ++++++++++++++++++++++ >> include/dt-bindings/clock/qcom,sm8750-gpucc.h | 53 +++++++++++++++++++ >> 3 files changed, 119 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml >> index 02968632fb3af34d6b3983a6a24aa742db1d59b1..d1b3557ab344b071d16dba4d5c6a267b7ab70573 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml >> @@ -20,6 +20,7 @@ description: | >> include/dt-bindings/clock/qcom,sm8550-gpucc.h >> include/dt-bindings/reset/qcom,sm8450-gpucc.h >> include/dt-bindings/reset/qcom,sm8650-gpucc.h >> + include/dt-bindings/reset/qcom,sm8750-gpucc.h >> include/dt-bindings/reset/qcom,x1e80100-gpucc.h >> >> properties: >> @@ -31,6 +32,7 @@ properties: >> - qcom,sm8475-gpucc >> - qcom,sm8550-gpucc >> - qcom,sm8650-gpucc >> + - qcom,sm8750-gpucc >> - qcom,x1e80100-gpucc >> - qcom,x1p42100-gpucc >> >> @@ -40,6 +42,9 @@ properties: >> - description: GPLL0 main branch source >> - description: GPLL0 div branch source >> >> + power-domains: >> + maxItems: 1 > > This should be a different binding or you need to restrict other > variants here. Actually looks like this is the same case as the recent videocc changes (15 year old technical debt catching up to us..) I'll send a mass-fixup for this. Some platforms require 2 and some require 3 entries here. Do I have to restrict them very specifically, or can I do: power-domains: description: Power domains required for the clock controller to operate minItems: 2 items: - description: CX power domain - description: MX power domain - description: MXC power domain ? Konrad