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AJvYcCUSNM97nW9o2qTtBZpukKAxJdqcUxXEyPa1adzSeFzQHewpuCh4sjf6pBqaFvnSoL+dVMtTwCfchJ/h@vger.kernel.org X-Gm-Message-State: AOJu0YySRwH5eY/rpmGzcOYcrM6KwZ/AItx14dQPRVR8cxwZhk7QQIST LiSe1rO0/6yaUSXmr6XM1i1nl64hLuuSt2Xq3t8TfhkoPik6vOs9M6kORd1BHhc= X-Google-Smtp-Source: AGHT+IFPdKSDwq2svM7AfN9p8jSbfkjJposupx9wGXez9ihUncQIuTAN9qQadaTGHwSVurVmNM9Yow== X-Received: by 2002:a05:600c:1ca1:b0:426:5cdf:2674 with SMTP id 5b1f17b1804b1-42c7b59e433mr70256085e9.4.1725348511256; Tue, 03 Sep 2024 00:28:31 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb73e20b7sm161574845e9.14.2024.09.03.00.28.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Sep 2024 00:28:30 -0700 (PDT) Message-ID: <54d60105-ee5b-48da-92f4-2bcb3dff5c92@tuxon.dev> Date: Tue, 3 Sep 2024 10:28:28 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Content-Language: en-US To: Biju Das , "geert+renesas@glider.be" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "alexandre.belloni@bootlin.com" , "magnus.damm@gmail.com" , "p.zabel@pengutronix.de" Cc: "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-rtc@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Claudiu Beznea References: <20240830130218.3377060-1-claudiu.beznea.uj@bp.renesas.com> <20240830130218.3377060-2-claudiu.beznea.uj@bp.renesas.com> From: claudiu beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03.09.2024 09:58, Biju Das wrote: > Hi Claudiu, > >> -----Original Message----- >> From: Claudiu >> Sent: Friday, August 30, 2024 2:02 PM >> Subject: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB >> >> From: Claudiu Beznea >> >> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small >> general usage memory of 128B. Add documentation for it. >> >> Signed-off-by: Claudiu Beznea >> --- >> >> Changes in v3: >> - moved the file to clock dt bindings directory as it is the >> only functionality supported at the moment; the other functionalities >> (tamper detector, SRAM) are offered though register spreaded >> though the address space of the VBATTB IP and not actually >> individual devices; the other functionalities are not >> planned to be supported soon and if they will be I think they >> fit better on auxiliary bus than MFD >> - dropped interrupt names as requested in the review process >> - dropped the inner node for clock controller >> - added #clock-cells >> - added rtx clock >> - updated description for renesas,vbattb-load-nanofarads >> - included dt-bindings/interrupt-controller/irq.h in examples section >> >> Changes in v2: >> - changed file name and compatible >> - updated title, description sections >> - added clock controller part documentation and drop dedicated file >> for it included in v1 >> - used items to describe interrupts, interrupt-names, clocks, clock-names, >> resets >> - dropped node labels and status >> - updated clock-names for clock controller to cope with the new >> logic on detecting the necessity to setup bypass >> >> .../clock/renesas,r9a08g045-vbattb.yaml | 81 +++++++++++++++++++ >> 1 file changed, 81 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml >> >> diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml >> b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml >> new file mode 100644 >> index 000000000000..29df0e01fae5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.y >> +++ aml >> @@ -0,0 +1,81 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Renesas Battery Backup Function (VBATTB) >> + >> +description: >> + Renesas VBATTB is an always on powered module (backed by battery) >> +which >> + controls the RTC clock (VBATTCLK), tamper detection logic and a small >> + general usage memory (128B). >> + >> +maintainers: >> + - Claudiu Beznea >> + >> +properties: >> + compatible: >> + const: renesas,r9a08g045-vbattb >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + items: >> + - description: tamper detector interrupt >> + >> + clocks: >> + items: >> + - description: VBATTB module clock >> + - description: RTC input clock (crystal oscillator or external >> + clock device) >> + >> + clock-names: >> + items: >> + - const: bclk >> + - const: rtx >> + >> + '#clock-cells': >> + const: 1 >> + >> + power-domains: >> + maxItems: 1 > > Not sure, you need to document "PD_VBATT" power domain > as per Table 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT) > > Power Mode PD_ISOVCC PD_VCC PD_VBATT > ALL_ON ON ON ON > AWO OFF ON ON > VBATT OFF OFF ON > ALL_OFF OFF OFF OFF > > PD_VBATT domain is the area where the RTC/backup register is located, works on battery power when the power of > PD_VCC and PD_ISOVCC domain are turned off. In Linux, the CPG is the power domain provider for all the IPs in RZ/G3S SoC (modeled though MSTOP CPG support). This is how it is currently implemented. Then groups of IPs are part of power domains PD_ISOVCC, PD_VCC, PD_VBATT. These power domains are i2c controlled with the help of firmware (at least at the moment). >From HW manual: - PD_VCC domain always powered on area. - PD_ISOVCC domain is the area where the power can be turned off. - PD_VBATT domain is the area where the RTC/backup register is located, works on battery power when the power of . The power to these domains are controlled with the help of firmware. Linux cannot do control itself as the CPU is in the PD_ISOVCC. If you look at picture 41.3 Power mode transition [1] it is mentioned the relation b/w these power domains (controlled by PMIC though firmware) and the supported power saving modes: ALL_ON, AWO, VBATT. Thank you, Claudiu Beznea [1] https://pasteboard.co/4ureEUnyCfV8.png > > Cheers, > Biju > >> + >> + resets: >> + items: >> + - description: VBATTB module reset >> + >> + renesas,vbattb-load-nanofarads: >> + description: load capacitance of the on board crystal oscillator >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 4000, 7000, 9000, 12500 ] >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + - power-domains >> + - resets >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + >> + vbattb@1005c000 { >> + compatible = "renesas,r9a08g045-vbattb"; >> + reg = <0x1005c000 0x1000>; >> + interrupts = ; >> + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; >> + clock-names = "bclk", "rtx"; >> + #clock-cells = <1>; >> + power-domains = <&cpg>; >> + resets = <&cpg R9A08G045_VBAT_BRESETN>; >> + renesas,vbattb-load-nanofarads = <12500>; >> + }; >> -- >> 2.39.2 >> >