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[82.64.67.166]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42ac679214asm4687520f8f.38.2025.11.07.02.29.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Nov 2025 02:29:59 -0800 (PST) Message-ID: <54fd0f0c-fd76-4230-9cae-cae6037b5b08@linaro.org> Date: Fri, 7 Nov 2025 11:29:57 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH RFC] arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks To: Abel Vesa , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar Cc: Taniya Das , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/3/25 17:51, Abel Vesa wrote: > It seems the USB combo SS1 and SS2 ref clocks have another gate, unlike > the SS0. These gates are part of the TCSR clock controller. > > At least on Dell XPS 13 (9345), if the ref clock provided by the TCSR > clock controller for SS1 PHY is disabled on the clk_disable_unused late > initcall, the PHY fails to initialize. It doesn't happen on the SS0 PHY > and the SS2 is not used on this device. > > This doesn't seem to be a problem on CRD though. It might be that the > RPMh has a vote for it from some other consumer and does not actually > disable it when ther kernel drops its vote. > > Either way, these TCSR provided clocks seem to be the correct ones for > the SS1 and SS2, so use them instead. > > Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") > Signed-off-by: Abel Vesa > --- > I dropped the clk_ignore_unused on my XPS13 a while ago, but only > realized now that usb_1_ss1_qmpphy (the left hand Type-C port) > doesn't initialize successfully. > > Traced it to the TCSR_USB_4_2_CLKREF_EN and then checked the Glymur DT > patchset. It seems it already does this for the SS1 and SS2 PHYs: > https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-23-24b601bbecc0@oss.qualcomm.com/ > > I think replacing the bi_tcxo is the better option, since the bi_tcxo > is already the parent of every clock provided by the TCSR, including > these for the SS1 and SS2 combo PHYs. > --- > arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi > index a17900eacb20396a9792efcfcd6ce6dd877435d1..9c9e567731556ff532fa64c7595e2570b0597da3 100644 > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi > @@ -2937,7 +2937,7 @@ usb_1_ss1_qmpphy: phy@fda000 { > reg = <0 0x00fda000 0 0x4000>; > > clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, > - <&rpmhcc RPMH_CXO_CLK>, > + <&tcsr TCSR_USB4_1_CLKREF_EN>, > <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, > <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; > clock-names = "aux", > @@ -3008,7 +3008,7 @@ usb_1_ss2_qmpphy: phy@fdf000 { > reg = <0 0x00fdf000 0 0x4000>; > > clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, > - <&rpmhcc RPMH_CXO_CLK>, > + <&tcsr TCSR_USB4_2_CLKREF_EN>, > <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, > <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; > clock-names = "aux", > > --- > base-commit: 131f3d9446a6075192cdd91f197989d98302faa6 > change-id: 20251103-dts-qcom-x1e80100-fix-combo-ref-clks-bcbffeb4269d > > Best regards, Reviewed-by: Neil Armstrong