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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b79f4975dc1sm345503666b.32.2025.12.05.04.03.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Dec 2025 04:03:13 -0800 (PST) Message-ID: <551b45ae-0980-4bd5-bb83-2fac6d7e2ce7@oss.qualcomm.com> Date: Fri, 5 Dec 2025 13:03:11 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/6] drm/msm/a6xx: Retrieve gmu core range by index To: rob.clark@oss.qualcomm.com Cc: Akhil P Oommen , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Jessica Zhang , Dan Carpenter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20251122-qcs615-spin-2-v3-0-9f4d4c87f51d@oss.qualcomm.com> <20251122-qcs615-spin-2-v3-1-9f4d4c87f51d@oss.qualcomm.com> <9cc55934-6980-4673-8501-2d1efe2f816e@oss.qualcomm.com> <936b6a48-a5e5-4efb-be7c-215ac670677d@oss.qualcomm.com> <7b4bcb6e-fbb1-45f6-921e-dd1340a8cece@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=T92BjvKQ c=1 sm=1 tr=0 ts=6932ca04 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=QGPp5zjhHj0ErSlcMgEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-GUID: BrjfyDHlpPqXS4UmvFPr7qrBVv4g0R4l X-Proofpoint-ORIG-GUID: BrjfyDHlpPqXS4UmvFPr7qrBVv4g0R4l X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA1MDA4NiBTYWx0ZWRfX+l+4lEfcV2Yk 0ynVa27nyoJVCHZUii2rzmsng9UMOWLX3Q+vmEalgjnEk8vqK5y8gPc7qGD5KMc0jSBaPDNuhE6 yLW76pOj448fEZpU4RkH+prmYEJ3IkWUBTn4zCBtNOktaFkwp6qfZ9hQbQWtQTUTXiD23QkyRu+ hW+IMfCDwBW3JIKObWLrk9oDowVFVCe9qkk5FXjwTZ8cNbirUD5DZv/GAZ2SYkWw9yKSgOQn1pE ZkoqJzzccCsu4Dak4h/1R7vd9B+Lixu+CUXIaBBjvK/VK2zvC/Fko3NxmGDR2MBhlP3WiAh0UBs dDpP6slbdncGYS7b72NL73bT2bxgcJIDKSShN0Jxw/RQPbb8c59Q+kIkjmBg2Ddr1uClWcyoPHj uvg8HT6PvwN4edH3vSbIgDUi+lJIbw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_04,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 bulkscore=0 impostorscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512050086 On 12/4/25 3:34 PM, Rob Clark wrote: > On Thu, Dec 4, 2025 at 5:30 AM Konrad Dybcio > wrote: >> >> On 12/4/25 2:10 PM, Akhil P Oommen wrote: >>> On 11/22/2025 7:08 PM, Konrad Dybcio wrote: >>>> On 11/21/25 10:52 PM, Akhil P Oommen wrote: >>>>> Some GPUs like A612 doesn't use a named register range resource. This >>>>> is because the reg-name property is discouraged when there is just a >>>>> single resource. >>>>> >>>>> To address this, retrieve the 'gmu' register range by its index. It is >>>>> always guaranteed to be at index 0. >>>>> >>>>> Signed-off-by: Akhil P Oommen >>>>> --- >>>>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++-------- >>>>> 1 file changed, 6 insertions(+), 8 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>> index 5903cd891b49..9662201cd2e9 100644 >>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>> @@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb, >>>>> return 0; >>>>> } >>>>> >>>>> -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, >>>>> - const char *name, resource_size_t *start) >>>>> +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start) >>>> >>>> Can we drop this and just use devm_platform_get_and_ioremap_resource()? >>> >>> This API seems to lock the io region and fails with -EBUSY if the region >>> is already in use. I am worried it may regress other chipsets. So, I >>> dropped this idea at the last moment. >> >> Is there any specific platform where this would be an issue? > > IIRC we've had this problem before and ended up reverting a similar > change, due to gpucc and gpu overlap Argh, sm8350.dtsi for example seems to be affected.. Hopefully one day we can fix that.. Konrad