From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>,
linux-edac@vger.kernel.org
Cc: git@amd.com, devicetree@vger.kernel.org, michal.simek@xilinx.com,
rric@kernel.org, james.morse@arm.com, tony.luck@intel.com,
mchehab@kernel.org, bp@alien8.de, robh+dt@kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC
Date: Wed, 2 Nov 2022 15:35:39 -0400 [thread overview]
Message-ID: <5520fc8b-e59f-d17b-33c8-5a6e869c6408@linaro.org> (raw)
In-Reply-To: <20221102084608.28894-2-shubhrajyoti.datta@amd.com>
On 02/11/2022 04:46, Shubhrajyoti Datta wrote:
> This patch adds device tree bindings for Xilinx Versal EDAC for DDR
Do not use "This commit/patch".
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95
> controller.
>
> Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> ---
>
> .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++
> 1 file changed, 57 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
> new file mode 100644
> index 000000000000..6717bc0f3be9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
> +
> +maintainers:
> + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> +
> +description:
> + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
> + 4X memory interfaces. Versal DDR memory controller has an optional ECC support
> + which correct single bit ECC errors and detect double bit ECC errors.
> +
> +properties:
> + compatible:
> + const: xlnx,versal-ddrmc-edac
Drop "edac". That's a Linuxism.
> +
> + reg:
> + items:
> + - description: DDR Memory Controller registers
> + - description: NOC registers corresponding to DDR Memory Controller
> +
> + reg-names:
> + items:
> + - const: ddrmc_base
> + - const: ddrmc_noc_base
Drop redundant parts from names, so these could be "base" and "noc" or
"ddrmc" and "noc". Or anything a bit more reasonable...
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-11-02 19:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-02 8:46 [PATCH 0/2] edac: xilinx: Added EDAC support for Xilinx DDR controller Shubhrajyoti Datta
2022-11-02 8:46 ` [PATCH 1/2] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC Shubhrajyoti Datta
2022-11-02 19:35 ` Krzysztof Kozlowski [this message]
2022-11-02 8:46 ` [PATCH 2/2] edac: xilinx: Added EDAC support for Xilinx DDR controller Shubhrajyoti Datta
2022-11-02 19:31 ` Krzysztof Kozlowski
2022-11-02 22:38 ` kernel test robot
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