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From: Inki Dae <inki.dae@samsung.com>
To: Hyungwon Hwang <human.hwang@samsung.com>
Cc: devicetree@vger.kernel.org, sw0312.kim@samsung.com,
	dh09.lee@samsung.com, cw00.choi@samsung.com,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v5 04/12] drm/exynos: dsi: rename pll_clk to sclk_clk
Date: Wed, 15 Apr 2015 10:24:21 +0900	[thread overview]
Message-ID: <552DBDC5.1080701@samsung.com> (raw)
In-Reply-To: <1428645330-1043-5-git-send-email-human.hwang@samsung.com>

On 2015년 04월 10일 14:55, Hyungwon Hwang wrote:
> This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
> is actually not the pll input clock for dsi. The pll input clock comes
> from the board's oscillator directly.
> 
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> ---
> Changes for v3:
> - Newly added
> 
> Changes for v4:
> - None
> 
> Changes for v5:
> - None
>  .../devicetree/bindings/video/exynos_dsim.txt      |  7 ++---
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c            | 31 ++++++++--------------
>  2 files changed, 15 insertions(+), 23 deletions(-)
> 
    ...snip...
> @@ -1350,7 +1341,7 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
>  
>  	phy_power_off(dsi->phy);
>  
> -	clk_disable_unprepare(dsi->pll_clk);
> +	clk_disable_unprepare(dsi->sclk_clk);
>  	clk_disable_unprepare(dsi->bus_clk);
>  
>  	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
> @@ -1713,10 +1704,10 @@ static int exynos_dsi_probe(struct platform_device *pdev)
>  		return -EPROBE_DEFER;
>  	}
>  
> -	dsi->pll_clk = devm_clk_get(dev, "pll_clk");
> -	if (IS_ERR(dsi->pll_clk)) {
> -		dev_info(dev, "failed to get dsi pll input clock\n");
> -		ret = PTR_ERR(dsi->pll_clk);
> +	dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi");

As I mentioned before, this patch makes existing device tree to be
broken so this cannot be merged even though you posted an another patch
which resolves the dt broken issue. That is because each patch shouldn't
incur any problem on working. So it'd be better to integrate this patch
and patch 9.

Thanks,
Inki Dae

> +	if (IS_ERR(dsi->sclk_clk)) {
> +		dev_info(dev, "failed to get dsi sclk clock\n");
> +		ret = PTR_ERR(dsi->sclk_clk);
>  		goto err_del_component;
>  	}
>  
> 

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  reply	other threads:[~2015-04-15  1:24 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-10  5:55 [PATCH v5 00/12] Add drivers for Exynos5433 display Hyungwon Hwang
2015-04-10  5:55 ` [PATCH v5 03/12] drm/exynos: mic: add MIC driver Hyungwon Hwang
2015-04-10  5:55 ` [PATCH v5 04/12] drm/exynos: dsi: rename pll_clk to sclk_clk Hyungwon Hwang
2015-04-15  1:24   ` Inki Dae [this message]
2015-04-10  5:55 ` [PATCH v5 05/12] drm/exynos: dsi: add macros for register access Hyungwon Hwang
2015-04-10  5:55 ` [PATCH v5 06/12] drm/exynos: dsi: make use of driver data for static values Hyungwon Hwang
2015-04-10  5:55 ` [PATCH v5 07/12] drm/exynos: dsi: make use of array for clock access Hyungwon Hwang
2015-04-10  5:55 ` [PATCH v5 08/12] drm/exynos: dsi: add support for Exynos5433 Hyungwon Hwang
2015-04-10  5:55 ` [PATCH v5 09/12] drm/exynos: dsi: add the backward compatibility for the renamed clock Hyungwon Hwang
     [not found] ` <1428645330-1043-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-04-10  5:55   ` [PATCH v5 01/12] drm/exynos: add Exynos5433 decon driver Hyungwon Hwang
     [not found]     ` <1428645330-1043-2-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-04-10  6:05       ` Varka Bhadram
2015-04-10  6:38         ` Hyungwon Hwang
2015-04-10  5:55   ` [PATCH v5 02/12] of: add helper for getting endpoint node of specific identifiers Hyungwon Hwang
2015-04-10  5:55   ` [PATCH v5 10/12] drm/exynos: dsi: add support for MIC driver as a bridge Hyungwon Hwang
2015-04-10  5:55 ` [PATCH v5 11/12] drm/exynos: dsi: do not set TE GPIO direction by input Hyungwon Hwang
2015-04-10  5:55 ` [PATCH v5 12/12] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi' Hyungwon Hwang

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