From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: William Qiu <william.qiu@starfivetech.com>,
devicetree@vger.kernel.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Ziv Xu <ziv.xu@starfivetech.com>
Subject: Re: [PATCH v4 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
Date: Tue, 4 Jul 2023 11:43:52 +0200 [thread overview]
Message-ID: <552d39ee-0fa0-94c0-89b9-245e39e8586d@linaro.org> (raw)
In-Reply-To: <20230704090453.83980-4-william.qiu@starfivetech.com>
On 04/07/2023 11:04, William Qiu wrote:
> Add the quad spi controller node for the StarFive JH7110 SoC.
>
> Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
> Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
...
> + qspi: spi@13010000 {
> + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
> + reg = <0x0 0x13010000 0x0 0x10000>,
> + <0x0 0x21000000 0x0 0x400000>;
> + interrupts = <25>;
> + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
> + <&syscrg JH7110_SYSCLK_QSPI_AHB>,
> + <&syscrg JH7110_SYSCLK_QSPI_APB>;
> + clock-names = "ref", "ahb", "apb";
> + resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
> + <&syscrg JH7110_SYSRST_QSPI_AHB>,
> + <&syscrg JH7110_SYSRST_QSPI_REF>;
> + reset-names = "qspi", "qspi-ocp", "rstc_ref";
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
Bus nodes are usually disabled by default and enabled when needed for
specific boards.
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-07-04 9:44 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 9:04 [PATCH v4 0/3] Add initialization of clock for StarFive JH7110 SoC William Qiu
2023-07-04 9:04 ` [PATCH v4 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks " William Qiu
2023-07-04 9:04 ` [PATCH v4 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI William Qiu
2023-07-04 16:36 ` Conor Dooley
2023-07-04 16:41 ` Mark Brown
2023-07-05 7:02 ` William Qiu
2023-07-05 6:21 ` Krzysztof Kozlowski
2023-07-05 7:04 ` William Qiu
2023-07-05 7:23 ` Krzysztof Kozlowski
2023-07-05 8:31 ` William Qiu
2023-07-04 9:04 ` [PATCH v4 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC William Qiu
2023-07-04 9:43 ` Krzysztof Kozlowski [this message]
2023-07-05 7:05 ` William Qiu
2023-07-17 17:13 ` Aurelien Jarno
2023-07-18 6:12 ` William Qiu
2023-08-04 19:04 ` (subset) [PATCH v4 0/3] Add initialization of clock " Mark Brown
-- strict thread matches above, loose matches on Subject: below --
2023-07-04 9:19 [PATCH v1 0/2] Add SPI module " William Qiu
2023-07-04 9:19 ` [PATCH v4 3/3] riscv: dts: starfive: Add QSPI controller node " William Qiu
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