Re: [PATCH v3 10/37] devicetree: document Ingenic SoC interrupt controller binding

[Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>]

Hello.

On 04/21/2015 05:46 PM, Paul Burton wrote:

> Add binding documentation for Ingenic SoC interrupt controllers.

> Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
> Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> Changes in v3:
>    - Merge documentation for various Ingenic SoCs, which only differ by
>      their compatible strings.

> Changes in v2:
>    - None.
> ---
>   .../bindings/interrupt-controller/ingenic,intc.txt | 25 ++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt

> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
> new file mode 100644
> index 0000000..5d652e4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
> @@ -0,0 +1,25 @@
> +Ingenic SoC Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : should be "ingenic,<socname>-intc". For example
> +  "ingenic,jz4740-intc" or "ingenic,jz4780-intc".
> +- reg : Specifies base physical address and size of the registers.
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> +  interrupt source. The value shall be 1.
> +- interrupt-parent : phandle of the CPU interrupt controller.
> +- interrupts : Specifies the CPU interrupt the controller is connected to.
> +
> +Example:
> +
> +intc: intc@10001000 {

    The node should be named "interrupt-controller@10001000", according to the 
epAPR standard.

WBR, Sergei

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