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AJvYcCViELpTT+AUvRVeYs+l3oDCnCD6OgkX//qlDBRlfl4YdGLhdlETWM5R35lYwDrYouQXrxIL/Dn7SIV8@vger.kernel.org X-Gm-Message-State: AOJu0Yy3hHQyeWgmTDXFL6v4ttsVOhWxX052REjosW5Qh8lR8/qWnPHO 39pOHWDQ9sx1Q0fylFCH4X5Ygcy+lzG394Bm0Xj+pW8Mh+nKvNB1xFtrHW17zzQ= X-Google-Smtp-Source: AGHT+IFKP+TMYUf8hSyMMTGOziIULq1HvfnDIOTbDSCryKJ5amdlOmDWug+wIx0ZuZ/E3sdbRQoVKA== X-Received: by 2002:a05:6512:15a5:b0:52e:9e70:d068 with SMTP id 2adb3069b0e04-53546afad74mr5564997e87.4.1725266847009; Mon, 02 Sep 2024 01:47:27 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8988fef4c3sm525445666b.32.2024.09.02.01.47.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Sep 2024 01:47:26 -0700 (PDT) Message-ID: <5556d176-cca7-492c-ba21-48256d5d6338@tuxon.dev> Date: Mon, 2 Sep 2024 11:47:24 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/16] Add initial USB support for the Renesas RZ/G3S SoC Content-Language: en-US To: Biju Das , Ulf Hansson Cc: "vkoul@kernel.org" , "kishon@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "p.zabel@pengutronix.de" , "geert+renesas@glider.be" , "magnus.damm@gmail.com" , "gregkh@linuxfoundation.org" , "mturquette@baylibre.com" , "sboyd@kernel.org" , Yoshihiro Shimoda , "linux-phy@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "linux-usb@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" , "linux-pm@vger.kernel.org" , Claudiu Beznea References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> <99bef301-9f6c-4797-b47e-c83e56dfbda9@tuxon.dev> From: claudiu beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Biju, On 02.09.2024 10:54, Biju Das wrote: > Hi Claudiu, > >> -----Original Message----- >> From: Biju Das >> Sent: Saturday, August 31, 2024 6:14 AM >> Subject: RE: [PATCH 00/16] Add initial USB support for the Renesas RZ/G3S SoC >> >> Hi Claudiu, >> >>> -----Original Message----- >>> From: claudiu beznea >>> Sent: Friday, August 30, 2024 9:23 AM >>> Subject: Re: [PATCH 00/16] Add initial USB support for the Renesas >>> RZ/G3S SoC >>> >>> Hi, Ulf, >>> >>> On 29.08.2024 18:26, Ulf Hansson wrote: >>>> On Thu, 22 Aug 2024 at 17:28, Claudiu wrote: >>>>> >>>>> From: Claudiu Beznea >>>>> >>>>> Hi, >>>>> >>>>> Series adds initial USB support for the Renesas RZ/G3S SoC. >>>>> >>>>> Series is split as follows: >>>>> >>>>> - patch 01/16 - add clock reset and power domain support for USB >>>>> - patch 02-04/16 - add reset control support for a USB signal >>>>> that need to be controlled before/after >>>>> the power to USB area is turned on/off. >>>>> >>>>> Philipp, Ulf, Geert, all, >>>>> >>>>> I detailed my approach for this in patch >>>>> 04/16, please have a look and let me know >>>>> your input. >>>> >>>> I have looked briefly. Your suggested approach may work, but I have >>>> a few thoughts, see below. >>>> >>>> If I understand correctly, it is the consumer driver for the device >>>> that is attached to the USB power domain that becomes responsible >>>> for asserting/de-asserting this new signal. Right? >>> >>> Right! >>> >>>> >>>> In this regard, please note that the consumer driver doesn't really >>>> know when the power domain really gets powered-on/off. Calling >>>> pm_runtime_get|put*() is dealing with the reference counting. For >>>> example, a call to pm_runtime_get*() just makes sure that the PM >>>> domain gets-or-remains powered-on. Could this be a problem from the >>>> reset-signal point of view? >>> >>> It should be safe. From the HW manual I understand the hardware block is something like the >> following: >>> >>> >>> USB area >>> +-------------------------+ >>> | | >>> | PHY --->USB controller | >>> SYSC --> | ^ | >>> | | | >>> | PHY reset | >>> +-------------------------+ >> >> How USB PWRRDY signal is connected to USB? >> >> USB block consists of PHY control, PHY, USB HOST and USB OTG Controller IPs. >> >> Is it connected to top level block or connected to each IP's for turning off the USB region power? >> >> ? Or Just PHY (HW manual mentions for AWO, the USB PWRRDY signal->USB PHY PWRRDY signal control)? > > As per the update from HW team, > > "SYS_USB_PWRRDY and SYS_PCIE_RST_RSM_B are used when transition from ALL_ON to AWO (or from AWO to ALL_ON). > > Refer to step 8,9 in Table 41.10 Example Transition Flow Outline from ALL_ON Mode to AWO Mode. > Refer to step 9,10 in Table 41.11 Example Transition Flow Outline from AWO Mode to ALL_ON Mode. All this is not new information. >From experiments, we need to control these signals also when booting as intermediary booting application may control and leave it in improper state. W/o having SYSC signals configured properly there is no chance for USB to work (it should be the same for PCIe but I haven't explored it yet). > > When turning off USB PHY and PCIe PHY, if they are not controlled, PHY may break." >From experiments, I know this, as this is the reason the SYSC USB PWRRDY has been implemented in Linux and proposed in this series. > > Do you have any plan to control this power transitions(ALL_ON to AWO and vice versa) in linux? As you know, the RZ/G3S USB PM code is already prepared. This is also configuring these signals when going to suspend/exiting from resume. W/o configuring properly these signals the USB is not working after a suspend/resume cycle. Thank you, Claudiu Beznea > Cheers, > Biju >