[PATCH v4 1/3] drivers: hwspinlock: add CSR atlas7 implementation

[PATCH v4 1/3] drivers: hwspinlock: add CSR atlas7 implementation

[Barry Song]

From: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>

Add hwspinlock support for the CSR atlas7 SoC.

The Hardware Spinlock device on atlas7 provides hardware assistance
for synchronization between the multiple processors in the system
(dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).

Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
Signed-off-by: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
---
 -v4: fix the error handler for iomap;
 fix a checkpatch issue;
 thanks suman!

 drivers/hwspinlock/Kconfig           |  12 ++++
 drivers/hwspinlock/Makefile          |   1 +
 drivers/hwspinlock/sirf_hwspinlock.c | 136 +++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 drivers/hwspinlock/sirf_hwspinlock.c

diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
index b5b4f52..73a4016 100644
--- a/drivers/hwspinlock/Kconfig
+++ b/drivers/hwspinlock/Kconfig
@@ -30,6 +30,18 @@ config HWSPINLOCK_QCOM
 
 	  If unsure, say N.
 
+config HWSPINLOCK_SIRF
+	tristate "SIRF Hardware Spinlock device"
+	depends on ARCH_SIRF
+	select HWSPINLOCK
+	help
+	  Say y here to support the SIRF Hardware Spinlock device, which
+	  provides a synchronisation mechanism for the various processors
+	  on the SoC.
+
+	  It's safe to say n here if you're not interested in SIRF hardware
+	  spinlock or just want a bare minimum kernel.
+
 config HSEM_U8500
 	tristate "STE Hardware Semaphore functionality"
 	depends on ARCH_U8500
diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile
index 68f95d9..6b59cb5a 100644
--- a/drivers/hwspinlock/Makefile
+++ b/drivers/hwspinlock/Makefile
@@ -5,4 +5,5 @@
 obj-$(CONFIG_HWSPINLOCK)		+= hwspinlock_core.o
 obj-$(CONFIG_HWSPINLOCK_OMAP)		+= omap_hwspinlock.o
 obj-$(CONFIG_HWSPINLOCK_QCOM)		+= qcom_hwspinlock.o
+obj-$(CONFIG_HWSPINLOCK_SIRF)		+= sirf_hwspinlock.o
 obj-$(CONFIG_HSEM_U8500)		+= u8500_hsem.o
diff --git a/drivers/hwspinlock/sirf_hwspinlock.c b/drivers/hwspinlock/sirf_hwspinlock.c
new file mode 100644
index 0000000..1601854
--- /dev/null
+++ b/drivers/hwspinlock/sirf_hwspinlock.c
@@ -0,0 +1,136 @@
+/*
+ * SIRF hardware spinlock driver
+ *
+ * Copyright (c) 2015 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/hwspinlock.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "hwspinlock_internal.h"
+
+struct sirf_hwspinlock {
+	void __iomem *io_base;
+	struct hwspinlock_device bank;
+};
+
+/* Number of Hardware Spinlocks*/
+#define	HW_SPINLOCK_NUMBER	30
+
+/* Hardware spinlock register offsets */
+#define HW_SPINLOCK_BASE	0x404
+#define HW_SPINLOCK_OFFSET(x)	(HW_SPINLOCK_BASE + 0x4 * (x))
+
+static int sirf_hwspinlock_trylock(struct hwspinlock *lock)
+{
+	void __iomem *lock_addr = lock->priv;
+
+	/* attempt to acquire the lock by reading value == 1 from it */
+	return !!readl(lock_addr);
+}
+
+static void sirf_hwspinlock_unlock(struct hwspinlock *lock)
+{
+	void __iomem *lock_addr = lock->priv;
+
+	/* release the lock by writing 0 to it */
+	writel(0, lock_addr);
+}
+
+static const struct hwspinlock_ops sirf_hwspinlock_ops = {
+	.trylock = sirf_hwspinlock_trylock,
+	.unlock = sirf_hwspinlock_unlock,
+};
+
+static int sirf_hwspinlock_probe(struct platform_device *pdev)
+{
+	struct sirf_hwspinlock *hwspin;
+	struct hwspinlock *hwlock;
+	int idx, ret;
+
+	if (!pdev->dev.of_node)
+		return -ENODEV;
+
+	hwspin = devm_kzalloc(&pdev->dev, sizeof(*hwspin) +
+			sizeof(*hwlock) * HW_SPINLOCK_NUMBER, GFP_KERNEL);
+	if (!hwspin)
+		return -ENOMEM;
+
+	/* retrieve io base */
+	hwspin->io_base = of_iomap(pdev->dev.of_node, 0);
+	if (!hwspin->io_base)
+		return -ENOMEM;
+
+	for (idx = 0; idx < HW_SPINLOCK_NUMBER; idx++) {
+		hwlock = &hwspin->bank.lock[idx];
+		hwlock->priv = hwspin->io_base + HW_SPINLOCK_OFFSET(idx);
+	}
+
+	platform_set_drvdata(pdev, hwspin);
+
+	pm_runtime_enable(&pdev->dev);
+
+	ret = hwspin_lock_register(&hwspin->bank, &pdev->dev,
+				   &sirf_hwspinlock_ops, 0,
+				   HW_SPINLOCK_NUMBER);
+	if (ret)
+		goto reg_failed;
+
+	return 0;
+
+reg_failed:
+	pm_runtime_disable(&pdev->dev);
+	iounmap(hwspin->io_base);
+
+	return ret;
+}
+
+static int sirf_hwspinlock_remove(struct platform_device *pdev)
+{
+	struct sirf_hwspinlock *hwspin = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = hwspin_lock_unregister(&hwspin->bank);
+	if (ret) {
+		dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	pm_runtime_disable(&pdev->dev);
+
+	iounmap(hwspin->io_base);
+
+	return 0;
+}
+
+static const struct of_device_id sirf_hwpinlock_ids[] = {
+	{ .compatible = "sirf,hwspinlock", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, sirf_hwpinlock_ids);
+
+static struct platform_driver sirf_hwspinlock_driver = {
+	.probe = sirf_hwspinlock_probe,
+	.remove = sirf_hwspinlock_remove,
+	.driver = {
+		.name = "atlas7_hwspinlock",
+		.of_match_table = of_match_ptr(sirf_hwpinlock_ids),
+	},
+};
+
+module_platform_driver(sirf_hwspinlock_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("SIRF Hardware spinlock driver");
+MODULE_AUTHOR("Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>");
-- 
2.3.5

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[PATCH v4 2/3] Documentation: dt: add the CSR atlas7 hwspinlock bindings document

[Barry Song]

From: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>

The Hardware Spinlock device on atlas7 provides hardware assistance
for synchronization between the multiple processors in the system
(dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
This patch adds the DT bindings information for this hwspinlock
module.

Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
Signed-off-by: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
---
 -v4: add description for "#hwlock-cells"
 thanks suman!

 .../devicetree/bindings/hwlock/sirf,hwspinlock.txt | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt

diff --git a/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt
new file mode 100644
index 0000000..9bb1240a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt
@@ -0,0 +1,28 @@
+SIRF Hardware spinlock device Binding
+-----------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+	"sirf,hwspinlock"
+
+- reg : the register address of hwspinlock
+
+- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
+	hwlock, so the number of cells should be <1> here.
+
+Please look at the generic hwlock binding for usage information for consumers,
+"Documentation/devicetree/bindings/hwlock/hwlock.txt"
+
+Example of hwlock provider:
+	hwlock {
+		compatible = "sirf,hwspinlock";
+		reg = <0x13240000 0x00010000>;
+		#hwlock-cells = <1>;
+	};
+
+Example of hwlock users:
+	node {
+		...
+		hwlocks = <&hwlock 2>;
+		...
+	};
-- 
2.3.5

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Re: [PATCH v4 2/3] Documentation: dt: add the CSR atlas7 hwspinlock bindings document

[Suman Anna]

On 05/26/2015 03:28 AM, Barry Song wrote:
> From: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
> 
> The Hardware Spinlock device on atlas7 provides hardware assistance
> for synchronization between the multiple processors in the system
> (dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
> This patch adds the DT bindings information for this hwspinlock
> module.
> 
> Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
> Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
> Signed-off-by: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
> Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
> ---

Reviewed-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>

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Re: [PATCH v4 2/3] Documentation: dt: add the CSR atlas7 hwspinlock bindings document

[Bjorn Andersson]

On Tue, May 26, 2015 at 1:28 AM, Barry Song <21cnbao-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
[..]
> diff --git a/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt
[..]
> +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
> +       hwlock, so the number of cells should be <1> here.
> +

Jfyi, you could have gotten away with:

#hwlock-cells: must be 1

> +Please look at the generic hwlock binding for usage information for consumers,
> +"Documentation/devicetree/bindings/hwlock/hwlock.txt"

Reviewed-by: Bjorn Andersson <bjorn.andersson-/MT0OVThwyLZJqsBc5GL+g@public.gmane.org>

Regards,
Bjorn
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[PATCH v3 3/3] ARM: dts: atlas7: use general dt-binding for hwspinlock

[Barry Song]

From: Wei Chen <Wei.Chen-kQvG35nSl+M@public.gmane.org>

This patch moves to use generic dt-binding for hwspinlock providers and
clients.
add #hwlock-cells for the provider and hwlocks for clients.

Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
Signed-off-by: Wei Chen <Wei.Chen-kQvG35nSl+M@public.gmane.org>
Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
---
 arch/arm/boot/dts/atlas7.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi
index a753178..66d3f0e 100644
--- a/arch/arm/boot/dts/atlas7.dtsi
+++ b/arch/arm/boot/dts/atlas7.dtsi
@@ -84,17 +84,17 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			hwspinlock {
+			hwlock: hwspinlock {
 				compatible = "sirf,hwspinlock";
 				reg = <0x13240000 0x00010000>;
-
-				num-spinlocks = <30>;
+				#hwlock-cells = <1>;
 			};
 
 			ns_m3_rproc@0 {
 				compatible = "sirf,ns2m30-rproc";
 				reg = <0x13240000 0x00010000>;
 				interrupts = <0 123 0>;
+				hwlocks = <&hwlock 0>, <&hwlock 1>;
 			};
 
 			ns_m3_rproc@1 {
-- 
2.3.5

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Re: [PATCH v3 3/3] ARM: dts: atlas7: use general dt-binding for hwspinlock

[Suman Anna]

Barry,

On 05/26/2015 03:28 AM, Barry Song wrote:
> From: Wei Chen <Wei.Chen-kQvG35nSl+M@public.gmane.org>
> 
> This patch moves to use generic dt-binding for hwspinlock providers and
> clients.
> add #hwlock-cells for the provider and hwlocks for clients.
> 
> Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
> Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
> Signed-off-by: Wei Chen <Wei.Chen-kQvG35nSl+M@public.gmane.org>
> Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
> ---
>  arch/arm/boot/dts/atlas7.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi
> index a753178..66d3f0e 100644
> --- a/arch/arm/boot/dts/atlas7.dtsi
> +++ b/arch/arm/boot/dts/atlas7.dtsi
> @@ -84,17 +84,17 @@
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  
> -			hwspinlock {
> +			hwlock: hwspinlock {
>  				compatible = "sirf,hwspinlock";
>  				reg = <0x13240000 0x00010000>;

An unrelated question here, why the reg is same for all the child nodes
of the  parent ipc node? If this is partitioned properly, then the
driver can be simplified a bit by using platform_get_resource and
devm_ioremap_resource?

> -
> -				num-spinlocks = <30>;
> +				#hwlock-cells = <1>;
>  			};
>  
>  			ns_m3_rproc@0 {
>  				compatible = "sirf,ns2m30-rproc";
>  				reg = <0x13240000 0x00010000>;
>  				interrupts = <0 123 0>;
> +				hwlocks = <&hwlock 0>, <&hwlock 1>;

Does this need to be added for the other nodes like ns_m3_rproc@1 as well?

regards
Suman

>  			};
>  
>  			ns_m3_rproc@1 {
> 

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Re: [PATCH v3 3/3] ARM: dts: atlas7: use general dt-binding for hwspinlock

[Bjorn Andersson]

On Thu, May 28, 2015 at 2:30 PM, Suman Anna <s-anna-l0cyMroinI0@public.gmane.org> wrote:
[..]
>>                               reg = <0x13240000 0x00010000>;
>
> An unrelated question here, why the reg is same for all the child nodes
> of the  parent ipc node? If this is partitioned properly, then the
> driver can be simplified a bit by using platform_get_resource and
> devm_ioremap_resource?
>

Good catch Suman, I missed that.

Barry, if these blocks represents various functionalities of the same
hw block then you should consider moving them to be part of a
simple-mfd.

Regards,
Bjorn
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Re: [PATCH v3 3/3] ARM: dts: atlas7: use general dt-binding for hwspinlock

[Barry Song]

2015-05-29 23:50 GMT+08:00 Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>:
> On Thu, May 28, 2015 at 2:30 PM, Suman Anna <s-anna-l0cyMroinI0@public.gmane.org> wrote:
> [..]
>>>                               reg = <0x13240000 0x00010000>;
>>
>> An unrelated question here, why the reg is same for all the child nodes
>> of the  parent ipc node? If this is partitioned properly, then the
>> driver can be simplified a bit by using platform_get_resource and
>> devm_ioremap_resource?
>>
>
> Good catch Suman, I missed that.
>
> Barry, if these blocks represents various functionalities of the same
> hw block then you should consider moving them to be part of a
> simple-mfd.

the hwspinlock and the IPC, which works for kicking interrupts between
multiple cores in the SoC,  are in one bus node but there is no
overlapping register.
hwspinlock:
begin from 0x13240000 + 0x400
IPC:
begin from 0x13240000, and end at begin from 0x13240000 + 0x400 - 0x4 ?

so i guess we can refine the dts memory region to avoid MFD?

>
> Regards,
> Bjorn

-barry
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Re: [PATCH v3 3/3] ARM: dts: atlas7: use general dt-binding for hwspinlock

[Suman Anna]

On 06/01/2015 12:31 AM, Barry Song wrote:
> 2015-05-29 23:50 GMT+08:00 Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>:
>> On Thu, May 28, 2015 at 2:30 PM, Suman Anna <s-anna-l0cyMroinI0@public.gmane.org> wrote:
>> [..]
>>>>                               reg = <0x13240000 0x00010000>;
>>>
>>> An unrelated question here, why the reg is same for all the child nodes
>>> of the  parent ipc node? If this is partitioned properly, then the
>>> driver can be simplified a bit by using platform_get_resource and
>>> devm_ioremap_resource?
>>>
>>
>> Good catch Suman, I missed that.
>>
>> Barry, if these blocks represents various functionalities of the same
>> hw block then you should consider moving them to be part of a
>> simple-mfd.
> 
> the hwspinlock and the IPC, which works for kicking interrupts between
> multiple cores in the SoC,  are in one bus node but there is no
> overlapping register.
> hwspinlock:
> begin from 0x13240000 + 0x400
> IPC:
> begin from 0x13240000, and end at begin from 0x13240000 + 0x400 - 0x4 ?
> 
> so i guess we can refine the dts memory region to avoid MFD?

Yeah, that should be fine from the hwspinlock perspective, all its
registers are self-contained.

regards
Suman
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Re: [PATCH v3 3/3] ARM: dts: atlas7: use general dt-binding for hwspinlock

[Barry Song]

2015-05-29 5:30 GMT+08:00 Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>:
> Barry,
>
> On 05/26/2015 03:28 AM, Barry Song wrote:
>> From: Wei Chen <Wei.Chen-kQvG35nSl+M@public.gmane.org>
>>
>> This patch moves to use generic dt-binding for hwspinlock providers and
>> clients.
>> add #hwlock-cells for the provider and hwlocks for clients.
>>
>> Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
>> Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
>> Signed-off-by: Wei Chen <Wei.Chen-kQvG35nSl+M@public.gmane.org>
>> Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
>> ---
>>  arch/arm/boot/dts/atlas7.dtsi | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi
>> index a753178..66d3f0e 100644
>> --- a/arch/arm/boot/dts/atlas7.dtsi
>> +++ b/arch/arm/boot/dts/atlas7.dtsi
>> @@ -84,17 +84,17 @@
>>                       #address-cells = <1>;
>>                       #size-cells = <1>;
>>
>> -                     hwspinlock {
>> +                     hwlock: hwspinlock {
>>                               compatible = "sirf,hwspinlock";
>>                               reg = <0x13240000 0x00010000>;
>
> An unrelated question here, why the reg is same for all the child nodes
> of the  parent ipc node? If this is partitioned properly, then the
> driver can be simplified a bit by using platform_get_resource and
> devm_ioremap_resource?
>
>> -
>> -                             num-spinlocks = <30>;
>> +                             #hwlock-cells = <1>;
>>                       };
>>
>>                       ns_m3_rproc@0 {
>>                               compatible = "sirf,ns2m30-rproc";
>>                               reg = <0x13240000 0x00010000>;
>>                               interrupts = <0 123 0>;
>> +                             hwlocks = <&hwlock 0>, <&hwlock 1>;
>
> Does this need to be added for the other nodes like ns_m3_rproc@1 as well?

now the hwlock-cells are only added for the nodes who are really using
it. other users have not used it.

>
> regards
> Suman
>
>>                       };
>>
>>                       ns_m3_rproc@1 {
>>
>

-barry
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Re: [PATCH v3 3/3] ARM: dts: atlas7: use general dt-binding for hwspinlock

[Suman Anna]

On 06/01/2015 12:33 AM, Barry Song wrote:
> 2015-05-29 5:30 GMT+08:00 Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>:
>> Barry,
>>
>> On 05/26/2015 03:28 AM, Barry Song wrote:
>>> From: Wei Chen <Wei.Chen-kQvG35nSl+M@public.gmane.org>
>>>
>>> This patch moves to use generic dt-binding for hwspinlock providers and
>>> clients.
>>> add #hwlock-cells for the provider and hwlocks for clients.
>>>
>>> Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
>>> Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
>>> Signed-off-by: Wei Chen <Wei.Chen-kQvG35nSl+M@public.gmane.org>
>>> Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
>>> ---
>>>  arch/arm/boot/dts/atlas7.dtsi | 6 +++---
>>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi
>>> index a753178..66d3f0e 100644
>>> --- a/arch/arm/boot/dts/atlas7.dtsi
>>> +++ b/arch/arm/boot/dts/atlas7.dtsi
>>> @@ -84,17 +84,17 @@
>>>                       #address-cells = <1>;
>>>                       #size-cells = <1>;
>>>
>>> -                     hwspinlock {
>>> +                     hwlock: hwspinlock {
>>>                               compatible = "sirf,hwspinlock";
>>>                               reg = <0x13240000 0x00010000>;
>>
>> An unrelated question here, why the reg is same for all the child nodes
>> of the  parent ipc node? If this is partitioned properly, then the
>> driver can be simplified a bit by using platform_get_resource and
>> devm_ioremap_resource?
>>
>>> -
>>> -                             num-spinlocks = <30>;
>>> +                             #hwlock-cells = <1>;
>>>                       };
>>>
>>>                       ns_m3_rproc@0 {
>>>                               compatible = "sirf,ns2m30-rproc";
>>>                               reg = <0x13240000 0x00010000>;
>>>                               interrupts = <0 123 0>;
>>> +                             hwlocks = <&hwlock 0>, <&hwlock 1>;
>>
>> Does this need to be added for the other nodes like ns_m3_rproc@1 as well?
> 
> now the hwlock-cells are only added for the nodes who are really using
> it. other users have not used it.

OK, may be split it out then and add these in a subsequent patch with
proper usage description.

regards
Suman

> 
>>
>> regards
>> Suman
>>
>>>                       };
>>>
>>>                       ns_m3_rproc@1 {
>>>
>>
> 
> -barry
> 

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Re: [PATCH v4 1/3] drivers: hwspinlock: add CSR atlas7 implementation

[Suman Anna]

On 05/26/2015 03:28 AM, Barry Song wrote:
> From: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
> 
> Add hwspinlock support for the CSR atlas7 SoC.
> 
> The Hardware Spinlock device on atlas7 provides hardware assistance
> for synchronization between the multiple processors in the system
> (dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
> 
> Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
> Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
> Signed-off-by: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
> Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>

Reviewed-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>

regards
Suman

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Re: [PATCH v4 1/3] drivers: hwspinlock: add CSR atlas7 implementation

[Bjorn Andersson]

On Tue, May 26, 2015 at 1:28 AM, Barry Song <21cnbao-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> From: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
>
> Add hwspinlock support for the CSR atlas7 SoC.
>
> The Hardware Spinlock device on atlas7 provides hardware assistance
> for synchronization between the multiple processors in the system
> (dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
>
> Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
> Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson-/MT0OVThwyLZJqsBc5GL+g@public.gmane.org>

> Signed-off-by: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
> Signed-off-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
> ---

Regards,
Bjorn
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Re: [PATCH v4 1/3] drivers: hwspinlock: add CSR atlas7 implementation

[Ohad Ben-Cohen]

> On Tue, May 26, 2015 at 1:28 AM, Barry Song <21cnbao-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > From: Wei Chen <wei.chen-kQvG35nSl+M@public.gmane.org>
> >
> > Add hwspinlock support for the CSR atlas7 SoC.
> >
> > The Hardware Spinlock device on atlas7 provides hardware assistance
> > for synchronization between the multiple processors in the system
> > (dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
> >
> > Cc: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
> > Cc: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
>
> Reviewed-by: Bjorn Andersson <bjorn.andersson-/MT0OVThwyLZJqsBc5GL+g@public.gmane.org>

Applied first two patches. Thanks Suman and Bjorn for making the time
to review them!
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