From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tero Kristo Subject: Re: [PATCHv4 03/10] arm/dts: dra7xx: add 'ti,set-rate-parent' for dss_dss_clk Date: Tue, 2 Jun 2015 09:57:35 +0300 Message-ID: <556D53DF.7070006@ti.com> References: <1433139798-23450-1-git-send-email-tomi.valkeinen@ti.com> <1433139798-23450-4-git-send-email-tomi.valkeinen@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1433139798-23450-4-git-send-email-tomi.valkeinen@ti.com> Sender: linux-omap-owner@vger.kernel.org To: Tomi Valkeinen , Tony Lindgren , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: paul@pwsan.com, Nishanth Menon , devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org On 06/01/2015 09:23 AM, Tomi Valkeinen wrote: > We need set-rate-parent flags for the display's clock path so that the > DSS driver can change the clock rate of the PLL. > > This patchs adds the ti,set-rate-parent flag to 'dss_dss_clk' clock > node, which is only a gate clock, allowing the setting of the clock rate > to propagate to the PLL. > > Signed-off-by: Tomi Valkeinen > Cc: devicetree@vger.kernel.org Acked-by: Tero Kristo > --- > arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi > index 470f39c4e326..357bedeebfac 100644 > --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi > +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi > @@ -1531,6 +1531,7 @@ > clocks = <&dpll_per_h12x2_ck>; > ti,bit-shift = <8>; > reg = <0x1120>; > + ti,set-rate-parent; > }; > > dss_hdmi_clk: dss_hdmi_clk { >