From: Stephen Boyd <sboyd@codeaurora.org>
To: Rob Herring <robherring2@gmail.com>,
Viresh Kumar <viresh.kumar@linaro.org>
Cc: Rafael Wysocki <rjw@rjwysocki.net>,
"linaro-kernel@lists.linaro.org" <linaro-kernel@lists.linaro.org>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
Arnd Bergmann <arnd.bergmann@linaro.org>,
Nishanth Menon <nm@ti.com>, Mark Brown <broonie@kernel.org>,
Mike Turquette <mike.turquette@linaro.org>,
Grant Likely <grant.likely@linaro.org>,
Olof Johansson <olof@lixom.net>,
Sudeep Holla <Sudeep.Holla@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Viswanath Puttagunta <viswanath.puttagunta@linaro.org>,
Lucas Stach <l.stach@pengutronix.de>,
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Thomas Abraham <ta.omasab@gmail.com>,
Abhilash Kesavan <kesavan.abhilash@gmail.com>,
Kevin Hilman <khilman@linaro.org>,
Santosh Shilimkar <santosh.shilimkar@oracle.com>
Subject: Re: [PATCH V7 2/3] OPP: Allow multiple OPP tables to be passed via DT
Date: Wed, 17 Jun 2015 18:30:24 -0700 [thread overview]
Message-ID: <55821F30.2090802@codeaurora.org> (raw)
In-Reply-To: <CAL_Jsq+SdgAf7=Yq7Jk_1d9jTpAOLCEuEDCZvD=-h=2MWsNfFw@mail.gmail.com>
On 06/17/2015 06:47 AM, Rob Herring wrote:
> On Wed, Jun 17, 2015 at 8:33 AM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>> On 17-06-15, 08:23, Rob Herring wrote:
>>>> + operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>;
>>> You've made a fundamental change here in that this can now be a list
>>> of phandles. There should be some description on what a list means
>>> (merge the tables?, select one?).
>> Did you miss the description I wrote few lines earlier or are you
>> asking for something else? This is what I wrote earlier:
>>
>>>> +Devices may want to choose OPP tables at runtime and so can provide a list of
>>>> +phandles here. But only *one* of them should be chosen at runtime.
>> So, clearly only ONE of the tables should be used.
> Yes, never mind.
>
>>> I think this needs to have a defined order and the platform should
>>> know what that is. For example, if you read the efuses and decide you
>>> need the "slow" table, you know to pick the first entry. Then you
>>> don't need opp-name. Does that work for QCom?
>> Why forcing on the order here? For example, consider a case where the
>> platform can have four tables, A B C D. Now DT is free to pass all
>> four or just a subset of those. Like, for some boards table B doesn't
>> stand valid. And so it may wanna pass just A C D. And so keeping these
>> tables in order is going to break for sure. Flexibility is probably
>> better in this case.
> Defined order is a key part of DT bindings. We solve the variable
> length problem with name lists associated with variable length
> property like:
>
> operating-point-names = "slow", "fast";
>
> I'm not a fan of doing this if we can avoid it, but we should at least
> follow the same pattern. Don't send me a patch with that yet, I want
> to hear from Stephen.
>
> You can also use "status" to disable specific tables rather than
> removing from the list.
>
An operating-point(s?)-names property seems ok... but doesn't that mean
that every CPU that uses the OPP has to have the same list of
operating-point-names? It would make sense to me if the operating points
were called something different depending on *which* CPU is using them,
but in this case the only name for the operating point is "slow" or
"fast", etc.
In reality we've assigned them names like speedX-binY-vZ so that we know
which speed bin, voltage bin, and version they're part of. Maybe OPP
node properties like qcom,speed-bin = <u32>, qcom,pvs-bin = <u32>, etc.
would be better? It would make the parsing code slightly more
complicated because it needs to look for 2 or 3 properties instead of a
name property though. Or would having different node names be
acceptable? That would avoid this list of strings.
At the least, operating-points-names will be required on qcom platforms.
A fixed ordering known to the platform would mean that we know exactly
how many voltage bins and speed bins and how many voltage bins per speed
bin are used for a particular SoC, which we've avoided knowing so far.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-06-18 1:30 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-04 16:20 [PATCH V7 0/3] OPP: Introduce OPP (V2) bindings Viresh Kumar
[not found] ` <cover.1433434659.git.viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-06-04 16:20 ` [PATCH V7 1/3] OPP: Add new bindings to address shortcomings of existing bindings Viresh Kumar
2015-06-04 18:37 ` Stephen Boyd
2015-06-05 2:41 ` Viresh Kumar
2015-06-16 13:34 ` Nishanth Menon
2015-06-04 16:20 ` [PATCH V7 2/3] OPP: Allow multiple OPP tables to be passed via DT Viresh Kumar
2015-06-17 13:23 ` Rob Herring
2015-06-17 13:33 ` Viresh Kumar
2015-06-17 13:47 ` Rob Herring
2015-06-17 14:42 ` Viresh Kumar
2015-06-18 1:30 ` Stephen Boyd [this message]
2015-06-18 2:25 ` Viresh Kumar
2015-06-18 2:50 ` Viresh Kumar
2015-06-19 18:47 ` Stephen Boyd
[not found] ` <20150619184747.GD22132-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-06-19 18:52 ` Rob Herring
[not found] ` <CAL_JsqJfWDO4r_FP6xHSxRkMM-pSnbEUB=d9Gj6mhvPY+ouLxA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-06-20 2:24 ` Viresh Kumar
2015-06-19 18:44 ` Stephen Boyd
2015-06-20 2:18 ` Viresh Kumar
2015-06-04 16:20 ` [PATCH V7 3/3] OPP: Add binding for 'opp-suspend' Viresh Kumar
2015-06-13 8:40 ` Viresh Kumar
2015-06-15 22:30 ` Rafael J. Wysocki
2015-06-15 23:35 ` Rob Herring
[not found] ` <CAL_JsqJb4P2Z2esgm5ffjWV37MU2KUF4gBdUpwSV8+21iTD1Bg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-06-16 0:31 ` Viresh Kumar
2015-06-16 2:54 ` Viresh Kumar
2015-06-16 19:23 ` Rob Herring
2015-06-16 21:21 ` Rafael J. Wysocki
2015-06-17 2:38 ` Viresh Kumar
2015-06-17 9:38 ` Rafael J. Wysocki
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