Re: [PATCH v2 0/3] ARM: keystone: add ecc error interrupt handling

[Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]

On 06/25/2015 08:04 AM, santosh shilimkar wrote:
> On 6/25/2015 7:31 AM, Vitaly Andrianov wrote:
>> This patch series adds support for arm L1/L2 ecc and ddr3 ecc error
>> handling
>> for Keystone devices
>>
>> Change Log
>>
>> v2:
>> - removing unused and sorting headers of keystone.c are moved to a
>> separate
>>    patch.
>> - l1l2 ecc and ddr3 ecc error handling are split it to separate patches
>> - removed unused headers from keystone_ecc.c
>> - platsmp.c removed from the patch.
>> - return IRQ_HANDLED for 1 bit error in l1l2 ecc handler
>> - checked and handled existing echttps://lwn.net/Articles/593336/c
>> error before enabling ddr3 interrupt
>> - 1 bit ddr3 interrupt is disabled, because it is handled by hardware
>> and
>>    there is no reason to handle it by software
>>
> This version looks good to me. As already commented, I would have liked
> the patch 2/3(L2 ECC) code in ARM generic code so will give some more
> time for others to come back. Otherwise I will queue this up for next
> window.

Why not make this into an edac driver? I sent out an L1/L2 error
detection edac driver for Krait processors a year ago, but it stalled
due to some DT binding stuff[1]. This looks fairly similar.

[1] https://lwn.net/Articles/593336/

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html