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From: Zhou Wang <wangzhou1@hisilicon.com>
To: James Morse <james.morse@arm.com>
Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Jingoo Han <jg1.han@samsung.com>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Arnd Bergmann <arnd@arndb.de>, Liviu Dudau <Liviu.Dudau@arm.com>,
	"kishon@ti.com" <kishon@ti.com>,
	"xobs@kosagi.com" <xobs@kosagi.com>,
	"m-karicheri2@ti.com" <m-karicheri2@ti.com>,
	"Minghuan.Lian@freescale.com" <Minghuan.Lian@freescale.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Yuanzhichang <yuanzhichang@hisilicon.com>,
	Zhudacai <zhudacai@hisilicon.com>,
	zhangjukuo <zhangjukuo@huawei.com>,
	qiuzhenfa <qiuzhenfa@hisilicon.com>,
	"liguozhu@hisilicon.com" <liguozhu@hisilicon.com>
Subject: Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support
Date: Thu, 2 Jul 2015 09:38:29 +0800	[thread overview]
Message-ID: <55949615.1070304@hisilicon.com> (raw)
In-Reply-To: <55942441.3050705@arm.com>

On 2015/7/2 1:32, James Morse wrote:
> Gabriele Paoloni wrote:
>>> Both series are applied to v4.1, use the same .config file, and the
>>> same dtb.
>>> I will investigate further.
>>>
>>> (Re-testing v2 works, so this isn't an interim hardware failure)
>>
>> This is a bit weird....
>>
>> Patch 2/5 is the only one that affect platforms different from Hisilicon
>>
>> The only difference between V3 patch[2/5] and v2 patch[2/4] is
> 
> Between v3:2/5 and your replacement for v2:2/4, which arrived after I had
> tested the v2 series. As the patch has been replaced with a different one -
> neither 'tested-by' is true any more.
>

Hi James,

Firstly, many thanks for your test!

Yes. v3:2/5 had merged Gabriele's codes in. So if you made test on original
v2 patchset and v3 patchset, I think the differences include Gabriele's codes
and codes in pci-keystone-dw.c.

As the patch has been replaced with a different one, I think I should have
added 'tested-by' after it passes your test, is this right?

> It looks like the BAR containing the bridge window is not being assigned,
> so no devices on bus 1 are discovered.
> 
> I will send the full v2 and v3 dmesg output separately.
> 

Thanks, I will debug the problem according your log.

Regards,
Zhou

> 
> Thanks,
> 
> James
> 
> 
> .
> 

  reply	other threads:[~2015-07-02  1:38 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-01  9:43 [PATCH v3 0/5] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05 Zhou Wang
2015-07-01  9:43 ` [PATCH v3 1/5] ARM/PCI: remove align_resource callback in pcibios_align_resource Zhou Wang
2015-07-02 17:50   ` Liviu Dudau
2015-07-07  5:44     ` Zhou Wang
     [not found]       ` <559B6721.4080305-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
2015-07-07  9:22         ` Liviu Dudau
2015-07-17 10:02           ` Gabriele Paoloni
2015-07-21  3:26             ` Zhou Wang
2015-07-01  9:43 ` [PATCH v3 2/5] PCI: designware: Add ARM64 support Zhou Wang
2015-07-01 13:29   ` Gabriele Paoloni
2015-07-01 14:26     ` James Morse
     [not found]       ` <5593F899.6050306-5wv7dgnIgG8@public.gmane.org>
2015-07-01 16:47         ` Gabriele Paoloni
2015-07-01 17:32           ` James Morse
2015-07-02  1:38             ` Zhou Wang [this message]
2015-07-02  7:24             ` Gabriele Paoloni
2015-07-02 17:40               ` James Morse
2015-07-07  3:44         ` Zhou Wang
2015-07-10  8:53           ` Gabriele Paoloni
2015-07-10  9:36             ` Zhou Wang
2015-07-02  1:16     ` Zhou Wang
2015-07-01  9:43 ` [PATCH v3 3/5] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05 Zhou Wang
     [not found] ` <1435743817-19083-1-git-send-email-wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
2015-07-01  9:43   ` [PATCH v3 4/5] Documentation: DT: Add Hisilicon PCIe host binding Zhou Wang
2015-07-01  9:43 ` [PATCH v3 5/5] MAINTAINERS: Add pcie-hisi maintainer Zhou Wang

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