From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Subject: Re: [PATCH 0/2] Add MT8173 MMPLL change rate support
Date: Wed, 08 Jul 2015 17:44:31 -0700
Message-ID: <559DC3EF.90401@codeaurora.org>
References: <1436344666-25645-1-git-send-email-jamesjj.liao@mediatek.com>
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To: James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>, Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Mike Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>, Heiko Stubner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
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On 07/08/2015 01:37 AM, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
>
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
>
> James Liao (2):
>   clk: mediatek: Fix PLL registers setting flow
>   clk: mediatek: Add MT8173 MMPLL change rate support
>

Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
it's not clear and makes me want to defer these until v4.3. Furthermore,
the subject starts with "Add" so it sounds like a new feature.

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a Linux Foundation Collaborative Project

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