Re: [PATCH 03/12] mtd: nand: omap: Move IRQ handling from GPMC to NAND driver

From: Roger Quadros <rogerq@ti.com>
To: nick <xerofoify@gmail.com>, Tony Lindgren <tony@atomide.com>
Cc: devicetree@vger.kernel.org, computersforpeace@gmail.com,
	linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
	ezequiel@vanguardiasur.com.ar, bcousson@baylibre.com,
	linux-omap@vger.kernel.org, dwmw2@infradead.org
Subject: Re: [PATCH 03/12] mtd: nand: omap: Move IRQ handling from GPMC to NAND driver
Date: Wed, 29 Jul 2015 16:52:57 +0300	[thread overview]
Message-ID: <55B8DAB9.7070602@ti.com> (raw)
In-Reply-To: <55B8C364.4030203@gmail.com>

On 29/07/15 15:13, nick wrote:
> 
> 
> On 2015-07-29 08:06 AM, Roger Quadros wrote:
>> Tony,
>>
>> On 13/07/15 15:40, Tony Lindgren wrote:
>>> * Roger Quadros <rogerq@ti.com> [150713 03:07]:
>>>> Tony,
>>>>
>>>> On 13/07/15 10:10, Tony Lindgren wrote:
>>>>> * Roger Quadros <rogerq@ti.com> [150710 05:26]:
>>>>>> Since the Interrupt Events are used only by the NAND driver,
>>>>>> there is no point in managing the Interrupt registers
>>>>>> in the GPMC driver and complicating it with irqchip modeling.
>>>>>
>>>>> I don't think it's a good idea to allow external drivers to
>>>>> tinker directly with GPMC registers. How about just set up GPMC
>>>>> as an irqchip for the edge detection interrupts?
>>>>>
>>>>> I think we already have devices with multiple NAND chips. And
>>>>> there's nothing stopping other drivers from using the edge
>>>>> detection interrupts.
>>>>
>>>> OK. The GPMC_IRQ registers manage 2 NAND specific interrupts
>>>> (terminalcount and fifo) and 'n' WAIT pin edge interrupts.
>>>>
>>>>  So we can model this as a irqchip with 'n + 2' interrupts.
>>>
>>> OK
>>
>> For the wait pins irqchip is not sufficient and it needs to be gpiochip
>> with irqchip. Waitpin status can be read from GPIO_STATUS register.
>>
>> Just getting the interrupt is not enough and we want to know if the
>> line is high or low. That is how nand->dev_ready works.
>>
>> How about having 2 IRQ domains?
>> One is irqchip with 2 interrupts (terminalcount and fifo) and second is
>> gpiochip + irqchip for the n wait pins.
>>
>> The nand driver can then be modified to use GPIO to get Read/Busy
>> pin status from the wait pin.
>>
>> cheers,
>> -roger
>>
> Doesn't OMAP boards support shared IRQs and if so why not share them across one
> IRQ domain if possible to save IRQ domains for other hardware that needs its 
> own IRQ domain. This is just a suggestion through as I don't have the hardware
> spec sheet on me Roger.

IRQ domain is a virtual abstraction introduced to prevent kernel irq number overlapping
in a single flat domain. I don't see what you can save by domain reuse.
Some memory maybe at most.

Shared interrupt is something totally different but we're trying to add real
hardware interrupts here. Didn't understand what you will share it with.

cheers,
-roger

> Nick 
>>>  
>>>> We need to take care that if a GPMC chip select needs a
>>>> wait pin then it can't be used as a generic interrupt.
>>>>
>>>> We need to get rid of omap_dev_ready() in nand/omap2.c as
>>>> it accesses the GPMC_STATUS register directly. Plus it is
>>>> hard coded to only monitor wait0 pin.
>>>
>>> OK
>>>  
>>>> What is the best map we should use for irqchip?
>>>> Some Socs have 4 WAIT pins, some have 3 and some have 2.
>>>>
>>>> Should we start with 0,1,2, for the wait pins and use the next
>>>> available free one for the NAND?
>>>
>>> Maybe we can just use the bits defined for each SoC in the
>>> GPMC_IRQSTATUS register for the mapping?  
>>> Regards,
>>>
>>> Tony
>>>
>>
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