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From: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Martin Kepplinger
	<martink-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Martin Kepplinger
	<martin.kepplinger-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>
Cc: "knaack.h-Mmb7MZpHnFY@public.gmane.org"
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	<christoph.muellner-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>
Subject: Re: [PATCH 8/8] iio: mma8452: add devicetree property to allow all pin wirings
Date: Sun, 2 Aug 2015 17:24:24 +0100	[thread overview]
Message-ID: <55BE4438.3000302@kernel.org> (raw)
In-Reply-To: <55B80C6D.5040607-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>

On 29/07/15 00:12, Martin Kepplinger wrote:
> Am 2015-07-28 um 11:28 schrieb Mark Rutland:
>> On Tue, Jul 28, 2015 at 10:11:29AM +0100, Martin Kepplinger wrote:
>>>
>>>
>>> On 2015-07-27 19:33, Mark Rutland wrote:
>>>> On Mon, Jul 27, 2015 at 03:37:48PM +0100, Martin Kepplinger wrote:
>>>>> Am 2015-07-27 um 16:23 schrieb Mark Rutland:
>>>>>> On Mon, Jul 27, 2015 at 03:08:15PM +0100, Martin Kepplinger wrote:
>>>>>>> For the devices supported by the mma8452 driver, two interrupt pins are
>>>>>>> available to route the interrupt signals to. By default INT1 is assumed.
>>>>>>>
>>>>>>> This adds a bitmask DT property for users to configure interrupt sources
>>>>>>> for INT2, if that is the wired interrupt pin for them.
>>>>>>
>>>>>> This sounds like configureation rather than a HW property. Why does this
>>>>>> need to be in the DT?
>>>>>
>>>>> It's a hardware property of the board that uses the device. There might
>>>>> be boards that connect just one of them at random, which is the reason
>>>>> for this DT property. There also might be exotic users who will want
>>>>> to use both pins to route different interrupt sources to (not yet
>>>>> supported, but no problem with such a bitmask).
>>>>
>>>> Ok, so I'm somewhat confused as to what the hardware looks like and what
>>>> this means.
>>>>
>>>> Could you elaborate on how INT1 and INT2 are used? It looks like they're
>>>> used as output pins, and so interrupt-names would seem appropriate for
>>>> describing the combination which is wired up.
>>>
>>> They are just the chip's two possible interrupt lines for us to get
>>> notified about event.
>>
>> Ok. So that matches my understanding.
>>
>>> You build a board, you use one of these 4 chips, wiring up just one of
>>> the 2 interrupt pins. By far most people won't ever need both pins.
>>>
>>> DT describes your hardware, right? So you describe how you built your
>>> board (wired the accelerometer chip) with this DT property.
>>
>> Ok.
>>
>>>> w.r.t. configuring the choice of output(s), that sounds like a runtime
>>>> decision rather than something which needs to be configured statically.
>>>
>>> This won't be useful during runtime. (De)activating events is what you
>>> do in iio sysfs.
>>>
>>> Even in the rare case (maybe supported in the future) when you want one
>>> interrupt source on one pin and another source on the other pin, that
>>> describes your hardware. You wire, say, data-ready to Linux and
>>> motion-detection to some strange alarm system. When you change your
>>> hardware (say, use Linux for both pins), I think it would justify
>>> changing a DT property.
>>
>> In that case you would need additional properties anyway.
>>
>>> Btw, we are talking about very theoretical stuff here. For now (and even
>>> possibly forever) we just don't ever want to break a DT propery we
>>> introduce here, thus the bitmask.
>>
>> I don't think you need the bitmask.
>>
>> I think all you need is interrupt-names, e.g.
>>
>> dev1 {
>> 	/* both wired up */
>> 	interrupts = <&some_ic 0 47>, <&some_ic 5 62>;
>> 	interrupt-names = "INT1", "INT2";
>> }
>>
>> dev2 {
>> 	/* only INT2 wired up */
>> 	interrupts = <&some_ic 3 96>;
>> 	interrupt-names = "INT2";
>> }
>>
>> You can figure out which interrupts are wired up by trying to acquire
>> them by name, then falling back to acquiting an anonymouos interrupt
>> (assuming it's INT1) to keep compatible with existing DTBs. You can
>> choose which to use arbitrarily, try to load balance, or whatever you'd
>> like.
>>
>> If it's later necessary to route some interrupts to another device,
>> additional properties can be added to accomodate that. We already know
>> that the bitmask alone is not sufficient for that case.
>>
> 
> Yes, this sounds reasonable indeed. I like the idea. I'm sorry I won't
> rewrite patch 8/8 now. Relocation and a lot to do before holidays. I'll
> be happy to write and test this properly in one month from now, if not
> done by somebody until then.
> 
> Until then, since patches 1-7 only introduce a bindings document, they
> shouldn't be problematic for devicetree people.
> 
> 
> So if Jonathan and IIO people find anybody for review, feel free to take
> patches 1-7. In any case, there is direct register access via debugfs to
> at least somehow make the driver work for everybody ;)
> 
> so long, thanks.
>                     martin
Cool, will kick this one into the long grass until you get back most
likely!

Have a good holiday when you get to it!

Jonathan

  parent reply	other threads:[~2015-08-02 16:24 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-27 14:08 [PATCH v5 0/8] iio: mma8452: improve driver and support more chips Martin Kepplinger
2015-07-27 14:08 ` [PATCH 1/8] iio: mma8452: refactor for seperating chip specific data Martin Kepplinger
2015-07-27 14:08 ` [PATCH 2/8] iio: mma8452: add support for MMA8453Q accelerometer chip Martin Kepplinger
     [not found] ` <1438006095-26920-1-git-send-email-martink-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>
2015-07-27 14:08   ` [PATCH 3/8] iio: mma8452: add freefall / motion interrupt source Martin Kepplinger
2015-07-27 14:08   ` [PATCH 4/8] iio: mma8452: add support for MMA8652FC and MMA8653FC accelerometers Martin Kepplinger
2015-08-08 16:42   ` [PATCH v5 0/8] iio: mma8452: improve driver and support more chips Jonathan Cameron
2015-07-27 14:08 ` [PATCH 5/8] iio: mma8452: add devicetree binding document Martin Kepplinger
2015-07-27 14:20   ` Mark Rutland
2015-07-27 14:59     ` [PATCHv2 " Martin Kepplinger
2015-07-27 14:08 ` [PATCH 6/8] iio: mma8452: add copyright notice comment Martin Kepplinger
2015-07-27 14:08 ` [PATCH 7/8] iio: mma8452: leave sysfs namings to the iio core Martin Kepplinger
2015-07-27 14:08 ` [PATCH 8/8] iio: mma8452: add devicetree property to allow all pin wirings Martin Kepplinger
2015-07-27 14:23   ` Mark Rutland
2015-07-27 14:37     ` Martin Kepplinger
     [not found]       ` <55B6423C.7030301-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>
2015-07-27 17:33         ` Mark Rutland
2015-07-28  9:11           ` Martin Kepplinger
2015-07-28  9:28             ` Mark Rutland
2015-07-28 23:12               ` Martin Kepplinger
     [not found]                 ` <55B80C6D.5040607-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>
2015-08-02 16:24                   ` Jonathan Cameron [this message]
2015-07-27 14:56     ` [PATCHv2 " Martin Kepplinger
  -- strict thread matches above, loose matches on Subject: below --
2015-07-06 12:34 [PATCH v4 0/8] iio:mma8452: improve driver and support more chips Martin Kepplinger
     [not found] ` <1436186062-5766-1-git-send-email-martink-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>
2015-07-06 12:34   ` [PATCH 8/8] iio: mma8452: add devicetree property to allow all pin wirings Martin Kepplinger
     [not found]     ` <1436186062-5766-9-git-send-email-martink-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>
2015-07-19 13:47       ` Jonathan Cameron
     [not found]         ` <55ABAA8B.3080706-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2015-07-19 18:42           ` Martin Kepplinger
2015-07-20  8:38           ` Martin Fuzzey
     [not found]             ` <55ACB393.8000603-mB3Nsq4MPf1BDgjK7y7TUQ@public.gmane.org>
2015-07-20 10:01               ` Martin Kepplinger

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