[RFCv3 0/4] Adding support for Zynq Reset Controller

[RFCv3 0/4] Adding support for Zynq Reset Controller

[Moritz Fischer]

Hi all,

I made another RFC addressing most of the feedback that I got so far.

I haven't completly given up on Sören's idea of getting rid of having
some sort of protection against people using wrong bits by accident,
but haven't come up with a clean way to do so yet (especially when looking at
the possiblity of also supporting the upcoming Zynq's reset controller).

I changed the reg property to <0x200 0x48> but I'm not sure if that's correct.
At 0x24C there's the RS_AWDT_CTRL which is not a reset. The last legit one
is A9_CPU_RST_CTRL at 0x244.

As Michal requested I removed the #include syntax from the devicetree bindings.

Thanks for your reviews,

Moritz

Moritz Fischer (4):
  docs: dts: Added documentation for Xilinx Zynq Reset Controller
    bindings.
  dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
  reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
  ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER

 .../devicetree/bindings/reset/zynq-reset.txt       |  68 +++++++++
 arch/arm/boot/dts/zynq-7000.dtsi                   |   8 ++
 arch/arm/mach-zynq/Kconfig                         |   1 +
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-zynq.c                         | 155 +++++++++++++++++++++
 5 files changed, 233 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
 create mode 100644 drivers/reset/reset-zynq.c

-- 
2.4.3

[RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.

[Moritz Fischer]

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
---
 .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt

diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
new file mode 100644
index 0000000..498c037a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
@@ -0,0 +1,68 @@
+Xilinx Zynq Reset Manager
+
+The Zynq AP-SoC has several different resets.
+
+See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
+
+Required properties:
+- compatible: "xlnx,zynq-reset"
+- reg: SLCR offset and size taken via syscon <0x200 0x48>
+- syscon: <&slcr>
+  This should be a phandle to the Zynq's SLCR register.
+- #reset-cells: Must be 1
+
+The Zynq Reset Manager needs to be a childnode of the SLCR.
+
+Example:
+	rstc: rstc@200 {
+		compatible = "xlnx,zynq-reset";
+		reg = <0x200 0x48>;
+		#reset-cells = <1>;
+		syscon = <&slcr>;
+	};
+
+Reset outputs:
+ 0  : soft reset
+ 32 : ddr reset
+ 64 : topsw reset
+ 96 : dmac reset
+ 128: usb0 reset
+ 129: usb1 reset
+ 160: gem0 reset
+ 161: gem1 reset
+ 164: gem0 rx reset
+ 165: gem1 rx reset
+ 166: gem0 ref reset
+ 167: gem1 ref reset
+ 192: sdio0 reset
+ 193: sdio1 reset
+ 196: sdio0 ref reset
+ 197: sdio1 ref reset
+ 224: spi0 reset
+ 225: spi1 reset
+ 226: spi0 ref reset
+ 227: spi1 ref reset
+ 256: can0 reset
+ 257: can1 reset
+ 258: can0 ref reset
+ 259: can1 ref reset
+ 288: i2c0 reset
+ 289: i2c1 reset
+ 320: uart0 reset
+ 321: uart1 reset
+ 322: uart0 ref reset
+ 323: uart1 ref reset
+ 352: gpio reset
+ 384: lqspi reset
+ 385: qspi ref reset
+ 416: smc reset
+ 417: smc ref reset
+ 448: ocm reset
+ 512: fpga0 out reset
+ 513: fpga1 out reset
+ 514: fpga2 out reset
+ 515: fpga3 out reset
+ 544: a9 reset 0
+ 545: a9 reset 1
+ 552: peri reset
+
-- 
2.4.3

Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.

[Philipp Zabel]

Hi Moritz,

Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
> Signed-off-by: Moritz Fischer <moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>
> ---
>  .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
> 
> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
> new file mode 100644
> index 0000000..498c037a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
> @@ -0,0 +1,68 @@
> +Xilinx Zynq Reset Manager
> +
> +The Zynq AP-SoC has several different resets.
> +
> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
> +
> +Required properties:
> +- compatible: "xlnx,zynq-reset"
> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
> +- syscon: <&slcr>
> +  This should be a phandle to the Zynq's SLCR register.

                                                 ^ register singular?

I still think the syscon phandle property is superfluous,
but I'm fine with keeping it for consistency.
It could always be made optional later.

> +- #reset-cells: Must be 1
> +
> +The Zynq Reset Manager needs to be a childnode of the SLCR.
> +
> +Example:
> +	rstc: rstc@200 {
> +		compatible = "xlnx,zynq-reset";
> +		reg = <0x200 0x48>;
> +		#reset-cells = <1>;
> +		syscon = <&slcr>;
> +	};
> +
> +Reset outputs:
> + 0  : soft reset
> + 32 : ddr reset
> + 64 : topsw reset
> + 96 : dmac reset
> + 128: usb0 reset
> + 129: usb1 reset
> + 160: gem0 reset
> + 161: gem1 reset
> + 164: gem0 rx reset
> + 165: gem1 rx reset
> + 166: gem0 ref reset
> + 167: gem1 ref reset
> + 192: sdio0 reset
> + 193: sdio1 reset
> + 196: sdio0 ref reset
> + 197: sdio1 ref reset
> + 224: spi0 reset
> + 225: spi1 reset
> + 226: spi0 ref reset
> + 227: spi1 ref reset
> + 256: can0 reset
> + 257: can1 reset
> + 258: can0 ref reset
> + 259: can1 ref reset
> + 288: i2c0 reset
> + 289: i2c1 reset
> + 320: uart0 reset
> + 321: uart1 reset
> + 322: uart0 ref reset
> + 323: uart1 ref reset
> + 352: gpio reset
> + 384: lqspi reset
> + 385: qspi ref reset
> + 416: smc reset
> + 417: smc ref reset
> + 448: ocm reset
> + 512: fpga0 out reset
> + 513: fpga1 out reset
> + 514: fpga2 out reset
> + 515: fpga3 out reset
> + 544: a9 reset 0
> + 545: a9 reset 1
> + 552: peri reset
> +

regards
Philipp

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Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.

[Michal Simek]

On 08/04/2015 10:09 AM, Philipp Zabel wrote:
> Hi Moritz,
> 
> Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
>> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
>> ---
>>  .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
>>  1 file changed, 68 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
>>
>> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> new file mode 100644
>> index 0000000..498c037a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> @@ -0,0 +1,68 @@
>> +Xilinx Zynq Reset Manager
>> +
>> +The Zynq AP-SoC has several different resets.
>> +
>> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
>> +
>> +Required properties:
>> +- compatible: "xlnx,zynq-reset"
>> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>> +- syscon: <&slcr>
>> +  This should be a phandle to the Zynq's SLCR register.
> 
>                                                  ^ register singular?
> 
> I still think the syscon phandle property is superfluous,
> but I'm fine with keeping it for consistency.
> It could always be made optional later.

Great.

Philipp: I expect you want to take at least 1/4 and 3/4 via your tree.
I am fine if you also want to add 2/4 and 4/4 via your tree.
If you think that they should go via arm-soc please let me know and I
will add them to the queue.

Thanks,
Michal

Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.

[Moritz Fischer]

Hi Philip,

On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> Hi Moritz,
>
> Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
>> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
>> ---
>>  .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
>>  1 file changed, 68 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
>>
>> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> new file mode 100644
>> index 0000000..498c037a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> @@ -0,0 +1,68 @@
>> +Xilinx Zynq Reset Manager
>> +
>> +The Zynq AP-SoC has several different resets.
>> +
>> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
>> +
>> +Required properties:
>> +- compatible: "xlnx,zynq-reset"
>> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>> +- syscon: <&slcr>
>> +  This should be a phandle to the Zynq's SLCR register.
>
>                                                  ^ register singular?
Do you want me to resend the entire set, or are you cool with just git
amending the 's' for registers?

> I still think the syscon phandle property is superfluous,
> but I'm fine with keeping it for consistency.

Thanks.
> It could always be made optional later.
>
>> +- #reset-cells: Must be 1
>> +
>> +The Zynq Reset Manager needs to be a childnode of the SLCR.
>> +
>> +Example:
>> +     rstc: rstc@200 {
>> +             compatible = "xlnx,zynq-reset";
>> +             reg = <0x200 0x48>;
>> +             #reset-cells = <1>;
>> +             syscon = <&slcr>;
>> +     };
>> +
>> +Reset outputs:
>> + 0  : soft reset
>> + 32 : ddr reset
>> + 64 : topsw reset
>> + 96 : dmac reset
>> + 128: usb0 reset
>> + 129: usb1 reset
>> + 160: gem0 reset
>> + 161: gem1 reset
>> + 164: gem0 rx reset
>> + 165: gem1 rx reset
>> + 166: gem0 ref reset
>> + 167: gem1 ref reset
>> + 192: sdio0 reset
>> + 193: sdio1 reset
>> + 196: sdio0 ref reset
>> + 197: sdio1 ref reset
>> + 224: spi0 reset
>> + 225: spi1 reset
>> + 226: spi0 ref reset
>> + 227: spi1 ref reset
>> + 256: can0 reset
>> + 257: can1 reset
>> + 258: can0 ref reset
>> + 259: can1 ref reset
>> + 288: i2c0 reset
>> + 289: i2c1 reset
>> + 320: uart0 reset
>> + 321: uart1 reset
>> + 322: uart0 ref reset
>> + 323: uart1 ref reset
>> + 352: gpio reset
>> + 384: lqspi reset
>> + 385: qspi ref reset
>> + 416: smc reset
>> + 417: smc ref reset
>> + 448: ocm reset
>> + 512: fpga0 out reset
>> + 513: fpga1 out reset
>> + 514: fpga2 out reset
>> + 515: fpga3 out reset
>> + 544: a9 reset 0
>> + 545: a9 reset 1
>> + 552: peri reset
>> +
>
> regards
> Philipp
>

Cheers,

Moritz

Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.

[Philipp Zabel]

Hi Moritz,

Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer:
> Hi Philip,
> 
> On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> > Hi Moritz,
> >
> > Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
[...]
> >> +Required properties:
> >> +- compatible: "xlnx,zynq-reset"
> >> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
> >> +- syscon: <&slcr>
> >> +  This should be a phandle to the Zynq's SLCR register.
> >
> >                                                  ^ register singular?
> Do you want me to resend the entire set, or are you cool with just git
> amending the 's' for registers?

Amended and applied, thanks.

regards
Philipp

Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.

[Moritz Fischer]

Michal,

On Tue, Aug 4, 2015 at 8:10 AM, Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> Hi Moritz,
>
> Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer:
>> Hi Philip,
>>
>> On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>> > Hi Moritz,
>> >
>> > Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
> [...]
>> >> +Required properties:
>> >> +- compatible: "xlnx,zynq-reset"
>> >> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>> >> +- syscon: <&slcr>
>> >> +  This should be a phandle to the Zynq's SLCR register.
>> >
>> >                                                  ^ register singular?
>> Do you want me to resend the entire set, or are you cool with just git
>> amending the 's' for registers?
>
> Amended and applied, thanks.

Will you take 4/4 and 2/4 via your tree?
>
> regards
> Philipp
>

Thanks,

Moritz
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Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.

[Michal Simek]

On 08/05/2015 09:43 PM, Moritz Fischer wrote:
> Michal,
> 
> On Tue, Aug 4, 2015 at 8:10 AM, Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>> Hi Moritz,
>>
>> Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer:
>>> Hi Philip,
>>>
>>> On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>>>> Hi Moritz,
>>>>
>>>> Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
>> [...]
>>>>> +Required properties:
>>>>> +- compatible: "xlnx,zynq-reset"
>>>>> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>>>>> +- syscon: <&slcr>
>>>>> +  This should be a phandle to the Zynq's SLCR register.
>>>>
>>>>                                                  ^ register singular?
>>> Do you want me to resend the entire set, or are you cool with just git
>>> amending the 's' for registers?
>>
>> Amended and applied, thanks.
> 
> Will you take 4/4 and 2/4 via your tree?

Applied to zynq/dt and zynq/soc.

Thanks,
Michal

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[RFCv3 2/4] dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.

[Moritz Fischer]

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
---
 arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 0691508..6bebf02 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -1,5 +1,6 @@
 /*
  *  Copyright (C) 2011 - 2014 Xilinx
+ *  Copyright (C) 2015 National Instruments Corp.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -258,6 +259,13 @@
 				reg = <0x100 0x100>;
 			};
 
+			rstc: rstc@200 {
+				compatible = "xlnx,zynq-reset";
+				reg = <0x200 0x48>;
+				#reset-cells = <1>;
+				syscon = <&slcr>;
+			};
+
 			pinctrl0: pinctrl@700 {
 				compatible = "xlnx,pinctrl-zynq";
 				reg = <0x700 0x200>;
-- 
2.4.3

Re: [RFCv3 2/4] dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.

[Michal Simek]

On 07/31/2015 03:13 AM, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer <moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index 0691508..6bebf02 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -1,5 +1,6 @@
>  /*
>   *  Copyright (C) 2011 - 2014 Xilinx
> + *  Copyright (C) 2015 National Instruments Corp.
>   *
>   * This software is licensed under the terms of the GNU General Public
>   * License version 2, as published by the Free Software Foundation, and
> @@ -258,6 +259,13 @@
>  				reg = <0x100 0x100>;
>  			};
>  
> +			rstc: rstc@200 {
> +				compatible = "xlnx,zynq-reset";
> +				reg = <0x200 0x48>;
> +				#reset-cells = <1>;
> +				syscon = <&slcr>;
> +			};
> +
>  			pinctrl0: pinctrl@700 {
>  				compatible = "xlnx,pinctrl-zynq";
>  				reg = <0x700 0x200>;
> 

Acked-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>

Thanks,
Michal
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[RFCv3 3/4] reset: reset-zynq: Adding support for Xilinx Zynq reset controller.

[Moritz Fischer]

This adds a reset controller driver to control the Xilinx Zynq
AP-SoC's various resets.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
---
 drivers/reset/Makefile     |   1 +
 drivers/reset/reset-zynq.c | 155 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 156 insertions(+)
 create mode 100644 drivers/reset/reset-zynq.c

diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..3fe50e7 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
 obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
diff --git a/drivers/reset/reset-zynq.c b/drivers/reset/reset-zynq.c
new file mode 100644
index 0000000..89318a5
--- /dev/null
+++ b/drivers/reset/reset-zynq.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2015, National Instruments Corp.
+ *
+ * Xilinx Zynq Reset controller driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+struct zynq_reset_data {
+	struct regmap *slcr;
+	struct reset_controller_dev rcdev;
+	u32 offset;
+};
+
+#define to_zynq_reset_data(p)		\
+	container_of((p), struct zynq_reset_data, rcdev)
+
+static int zynq_reset_assert(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
+
+	int bank = id / BITS_PER_LONG;
+	int offset = id % BITS_PER_LONG;
+
+	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
+		 bank, offset);
+
+	return regmap_update_bits(priv->slcr,
+				  priv->offset + (bank * 4),
+				  BIT(offset),
+				  BIT(offset));
+}
+
+static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
+
+	int bank = id / BITS_PER_LONG;
+	int offset = id % BITS_PER_LONG;
+
+	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
+		 bank, offset);
+
+	return regmap_update_bits(priv->slcr,
+				  priv->offset + (bank * 4),
+				  BIT(offset),
+				  ~BIT(offset));
+}
+
+static int zynq_reset_status(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
+
+	int bank = id / BITS_PER_LONG;
+	int offset = id % BITS_PER_LONG;
+	int ret;
+	u32 reg;
+
+	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
+		 bank, offset);
+
+	ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg);
+	if (ret)
+		return ret;
+
+	return !!(reg & BIT(offset));
+}
+
+static struct reset_control_ops zynq_reset_ops = {
+	.assert		= zynq_reset_assert,
+	.deassert	= zynq_reset_deassert,
+	.status		= zynq_reset_status,
+};
+
+static int zynq_reset_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct zynq_reset_data *priv;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, priv);
+
+	priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+						     "syscon");
+	if (IS_ERR(priv->slcr)) {
+		dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
+		return PTR_ERR(priv->slcr);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "missing IO resource\n");
+		return -ENODEV;
+	}
+
+	priv->offset = res->start;
+
+	priv->rcdev.owner = THIS_MODULE;
+	priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG;
+	priv->rcdev.ops = &zynq_reset_ops;
+	priv->rcdev.of_node = pdev->dev.of_node;
+	reset_controller_register(&priv->rcdev);
+
+	return 0;
+}
+
+static int zynq_reset_remove(struct platform_device *pdev)
+{
+	struct zynq_reset_data *priv = platform_get_drvdata(pdev);
+
+	reset_controller_unregister(&priv->rcdev);
+
+	return 0;
+}
+
+static const struct of_device_id zynq_reset_dt_ids[] = {
+	{ .compatible = "xlnx,zynq-reset", },
+	{ /* sentinel */ },
+};
+
+static struct platform_driver zynq_reset_driver = {
+	.probe	= zynq_reset_probe,
+	.remove	= zynq_reset_remove,
+	.driver = {
+		.name		= KBUILD_MODNAME,
+		.of_match_table	= zynq_reset_dt_ids,
+	},
+};
+module_platform_driver(zynq_reset_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
+MODULE_DESCRIPTION("Zynq Reset Controller Driver");
-- 
2.4.3

[RFCv3 4/4] ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER

[Moritz Fischer]

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
---
 arch/arm/mach-zynq/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 78e5e00..77d7df7 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_ZYNQ
 	bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
+	select ARCH_HAS_RESET_CONTROLLER
 	select ARCH_SUPPORTS_BIG_ENDIAN
 	select ARM_AMBA
 	select ARM_GIC
-- 
2.4.3

Re: [RFCv3 4/4] ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER

[Michal Simek]

On 07/31/2015 03:13 AM, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
> ---
>  arch/arm/mach-zynq/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> index 78e5e00..77d7df7 100644
> --- a/arch/arm/mach-zynq/Kconfig
> +++ b/arch/arm/mach-zynq/Kconfig
> @@ -1,5 +1,6 @@
>  config ARCH_ZYNQ
>  	bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
> +	select ARCH_HAS_RESET_CONTROLLER
>  	select ARCH_SUPPORTS_BIG_ENDIAN
>  	select ARM_AMBA
>  	select ARM_GIC
> 

Reviewed-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal

Re: [RFCv3 4/4] ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER

[Sören Brinkmann]

On Fri, 2015-07-31 at 10:09AM +0200, Michal Simek wrote:
> On 07/31/2015 03:13 AM, Moritz Fischer wrote:
> > Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
> > ---
> >  arch/arm/mach-zynq/Kconfig | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> > index 78e5e00..77d7df7 100644
> > --- a/arch/arm/mach-zynq/Kconfig
> > +++ b/arch/arm/mach-zynq/Kconfig
> > @@ -1,5 +1,6 @@
> >  config ARCH_ZYNQ
> >  	bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
> > +	select ARCH_HAS_RESET_CONTROLLER
> >  	select ARCH_SUPPORTS_BIG_ENDIAN
> >  	select ARM_AMBA
> >  	select ARM_GIC
> > 
> 
> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>

I personally, would prefer to decouple the logical outputs of the
reset-controller from the HW. But, as Moritz pointed out, that seems
rather uncommon for reset controllers. I think this is good to go.

	Thanks,
	Sören

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Re: [RFCv3 4/4] ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER

[Philipp Zabel]

Hi,

Am Freitag, den 31.07.2015, 09:47 -0700 schrieb Sören Brinkmann:
> On Fri, 2015-07-31 at 10:09AM +0200, Michal Simek wrote:
[...]
> > Reviewed-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Acked-by: Sören Brinkmann <soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>

I'll assume these apply to the whole series and queue patches 1 and 3.

best regards
Philipp

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Re: [RFCv3 4/4] ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER

[Sören Brinkmann]

Hi Philipp,

On Tue, 2015-08-04 at 10:38AM +0200, Philipp Zabel wrote:
> Hi,
> 
> Am Freitag, den 31.07.2015, 09:47 -0700 schrieb Sören Brinkmann:
> > On Fri, 2015-07-31 at 10:09AM +0200, Michal Simek wrote:
> [...]
> > > Reviewed-by: Michal Simek <michal.simek@xilinx.com>
> > Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
> 
> I'll assume these apply to the whole series and queue patches 1 and 3.

For me, yes, that was meant for the whole series. Sorry, for not making
that obvious.

	Thanks,
	Sören