Re: [PATCH V7 2/2] mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller.

From: Graham Moore <grmoore@opensource.altera.com>
To: vikas <vikas.manocha@st.com>
Cc: Marek Vasut <marex@denx.de>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Alan Tull <atull@opensource.altera.com>,
	Yves Vandervennet <yvanderv@opensource.altera.com>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	Dinh Nguyen <dinguyen@opensource.altera.com>,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH V7 2/2] mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller.
Date: Tue, 18 Aug 2015 14:17:42 -0500	[thread overview]
Message-ID: <55D384D6.9040303@opensource.altera.com> (raw)
In-Reply-To: <55D299CD.2070809@st.com>

Hi Vikas,

On 08/17/2015 09:34 PM, vikas wrote:
 > Hi Marek,
 >

[...]

 >> +
>> +/* Operation timeout value */
>> +#define CQSPI_TIMEOUT_MS                       500
>> +#define CQSPI_READ_TIMEOUT_MS                  10
>
> please add some comment about the timeouts value selection.
>

I wish I could comment, but I don't know the origin of these values. 
The 500 ms value is probably just "a very long time".

[...]

>> +
>> +       cqspi->irq_mask = CQSPI_IRQ_MASK_RD;
>> +       writel(cqspi->irq_mask, reg_base + CQSPI_REG_IRQMASK);
>
> here interrupt mask is being configured for every read, better would be to move it in init.
>

[...]

>> +
>> +       cqspi->irq_mask = CQSPI_IRQ_MASK_WR;
>> +       writel(cqspi->irq_mask, reg_base + CQSPI_REG_IRQMASK);
>
> same like read, it should be moved to init.
>

It uses different masks for read and write

[...]

BR,
Graham

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