Re: [PATCH V7 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver.

[vikas <vikas.manocha-qxv4g6HH51o@public.gmane.org>]

Hi,

On 08/18/2015 12:03 PM, Graham Moore wrote:
> Hi all,
> 
> On 08/18/2015 12:48 AM, Vikas MANOCHA wrote:
> 
> [...]
> 
>>>>> +Required properties:
>>>>> +- compatible : Should be "cdns,qspi-nor".
>>>>> +- reg : Contains two entries, each of which is a tuple consisting of a
>>>>> +    physical address and length.  The first entry is the address and
>>>>> +    length of the controller register set.  The second entry is the
>>>>> +    address and length of the QSPI Controller data area.
>>>>
>>>> "Controller data area", i think it means mapped NOR Flash address ?
>>>
>>> Probably ; Graham ?
>>>
>>>> If yes, it would be more clear with "Physical base address & size of NOR
>>>> Flash".
>>>
>>> This is the Direct mode thing, correct ? We don't support this, so I think
>>> we should drop this bit altogether and keep only one single address in this
>>> field.
>>
>> No it's not.
>>
> 
> It's the location of the SRAM fifo.  Also direct mode location I think, 
> if that were ever used.

Hmm...It is the base address of NOR flash. SRAM is not memory mapped.

> 
> The size is determined by a configuration parameter during system 
> design.  On Altera Cyclone5 the size is really big compared to SRAM 
> fifo.  I don't know why, maybe some hw engineer thought it would be 
> better to have a large size in case direct mode was used.

my comment is about second parameter of property "reg" which is NOR flash address, so above explanation does not
make sense for it.
Also in direct mode, sram does not come into play.

Rgds,
Vikas

> 
> BR,
> Graham
> .
> 
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