Re: [PATCH v5 2/4] Documentation: arm64/arm: dt bindings for numa.

[Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

On 14/08/15 18:39, Ganapatrao Kulkarni wrote:
> DT bindings for numa map for memory, cores and IOs using
> arm,associativity device node property.
>
> Signed-off-by: Ganapatrao Kulkarni <gkulkarni-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
> ---
>   Documentation/devicetree/bindings/arm/numa.txt | 212 +++++++++++++++++++++++++
>   1 file changed, 212 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/arm/numa.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/numa.txt b/Documentation/devicetree/bindings/arm/numa.txt
> new file mode 100644
> index 0000000..dc3ef86
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/numa.txt
> @@ -0,0 +1,212 @@
> +==============================================================================
> +NUMA binding description.
> +==============================================================================
> +
> +==============================================================================
> +1 - Introduction
> +==============================================================================
> +
> +Systems employing a Non Uniform Memory Access (NUMA) architecture contain
> +collections of hardware resources including processors, memory, and I/O buses,
> +that comprise what is commonly known as a NUMA node.
> +Processor accesses to memory within the local NUMA node is generally faster
> +than processor accesses to memory outside of the local NUMA node.
> +DT defines interfaces that allow the platform to convey NUMA node
> +topology information to OS.
> +
> +==============================================================================
> +2 - arm,associativity
> +==============================================================================
> +The mapping is done using arm,associativity device property.
> +this property needs to be present in every device node which needs to to be
> +mapped to numa nodes.
> +
> +arm,associativity property is set of 32-bit integers which defines level of
> +topology and boundary in the system at which a significant difference in
> +performance can be measured between cross-device accesses within
> +a single location and those spanning multiple locations.
> +The first cell always contains the broadest subdivision within the system,
> +while the last cell enumerates the individual devices, such as an SMT thread
> +of a CPU, or a bus bridge within an SoC".
> +
> +ex:
> +	/* board 0, socket 0, cluster 0, core 0  thread 0 */
> +	arm,associativity = <0 0 0 0 0>;
> +
> +==============================================================================
> +3 - arm,associativity-reference-points
> +==============================================================================
> +This property is a set of 32-bit integers, each representing an index into
> +the arm,associativity nodes. The first integer is the most significant
> +NUMA boundary and the following are progressively less significant boundaries.
> +There can be more than one level of NUMA.
> +
> +Ex:
> +	arm,associativity-reference-points = <0 1>;
> +	The board Id(index 0) used first to calculate the associativity (node
> +	distance), then follows the  socket id(index 1).
> +
> +	arm,associativity-reference-points = <1 0>;
> +	The socket Id(index 1) used first to calculate the associativity,
> +	then follows the board id(index 0).
> +
> +	arm,associativity-reference-points = <0>;
> +	Only the board Id(index 0) used to calculate the associativity.
> +
> +	arm,associativity-reference-points = <1>;
> +	Only socket Id(index 1) used to calculate the associativity.
> +
> +==============================================================================
> +4 - Example dts
> +==============================================================================
> +
> +Example: 2 Node system consists of 2 boards and each board having one socket
> +and 8 core in each socket.
> +
> +	arm,associativity-reference-points = <0>;
> +
> +	memory@00c00000 {
> +		device_type = "memory";
> +		reg = <0x0 0x00c00000 0x0 0x80000000>;
> +		/* board 0, socket 0, no specific core */
> +		arm,associativity = <0 0 0xffff>;
> +	};
> +
> +	memory@10000000000 {
> +		device_type = "memory";
> +		reg = <0x100 0x00000000 0x0 0x80000000>;
> +		/* board 1, socket 0, no specific core */
> +		arm,associativity = <1 0 0xffff>;
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu@000 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x000>;
> +			enable-method = "psci";
> +			/* board 0, socket 0, core 0*/
> +			arm,associativity = <0 0 0>;
> +		};
> +		cpu@001 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x001>;
> +			enable-method = "psci";
> +			arm,associativity = <0 0 1>;
> +		};
> +		cpu@002 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x002>;
> +			enable-method = "psci";
> +			arm,associativity = <0 0 2>;
> +		};
> +		cpu@003 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x003>;
> +			enable-method = "psci";
> +			arm,associativity = <0 0 3>;
> +		};
> +		cpu@004 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x004>;
> +			enable-method = "psci";
> +			arm,associativity = <0 0 4>;
> +		};
> +		cpu@005 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x005>;
> +			enable-method = "psci";
> +			arm,associativity = <0 0 5>;
> +		};
> +		cpu@006 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x006>;
> +			enable-method = "psci";
> +			arm,associativity = <0 0 6>;
> +		};
> +		cpu@007 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x007>;
> +			enable-method = "psci";
> +			arm,associativity = <0 0 7>;
> +		};
> +		cpu@008 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x008>;
> +			enable-method = "psci";
> +			/* board 1, socket 0, core 0*/
> +			arm,associativity = <1 0 0>;
> +		};
> +		cpu@009 {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x009>;
> +			enable-method = "psci";
> +			arm,associativity = <1 0 1>;
> +		};
> +		cpu@00a {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x00a>;
> +			enable-method = "psci";
> +			arm,associativity = <0 0 2>;

Nit: this should be
arm,associativity = <1 0 2>;

> +		};
> +		cpu@00b {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x00b>;
> +			enable-method = "psci";
> +			arm,associativity = <1 0 3>;
> +		};
> +		cpu@00c {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x00c>;
> +			enable-method = "psci";
> +			arm,associativity = <1 0 4>;
> +		};
> +		cpu@00d {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x00d>;
> +			enable-method = "psci";
> +			arm,associativity = <1 0 5>;
> +		};
> +		cpu@00e {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x00e>;
> +			enable-method = "psci";
> +			arm,associativity = <1 0 6>;
> +		};
> +		cpu@00f {
> +			device_type = "cpu";
> +			compatible =  "arm,armv8";
> +			reg = <0x0 0x00f>;
> +			enable-method = "psci";
> +			arm,associativity = <1 0 7>;
> +		};
> +	};
> +
> +	pcie0: pcie0@0x8480,00000000 {
> +		compatible = "arm,armv8";
> +		device_type = "pci";
> +		bus-range = <0 255>;
> +		#size-cells = <2>;
> +		#address-cells = <3>;
> +		reg = <0x8480 0x00000000 0 0x10000000>;  /* Configuration space */
> +		ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>; /* mem ranges */
> +		/* board 0, socket 0, pci bus 0*/
> +		arm,associativity = <0 0 0>;
> +        };
>

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